JPS641798Y2 - - Google Patents
Info
- Publication number
- JPS641798Y2 JPS641798Y2 JP4890180U JP4890180U JPS641798Y2 JP S641798 Y2 JPS641798 Y2 JP S641798Y2 JP 4890180 U JP4890180 U JP 4890180U JP 4890180 U JP4890180 U JP 4890180U JP S641798 Y2 JPS641798 Y2 JP S641798Y2
- Authority
- JP
- Japan
- Prior art keywords
- voltage system
- circuit
- positive voltage
- negative voltage
- disconnected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Description
【考案の詳細な説明】
本考案は一般電子装置における異極性電源で動
作する回路間のデジタル情報の伝達、特に
TTLIC等正電圧系の信号で負電圧系のランプ・
リレー等をドライブするような場合のレベル変換
回路に関するものである。[Detailed description of the invention] This invention is intended for the transmission of digital information between circuits operating with different polarity power supplies in general electronic equipment, especially
Positive voltage signals such as TTLIC can be used to detect negative voltage lamps and
This relates to a level conversion circuit used to drive relays, etc.
従来この種の変換回路としては第１図に示すよ
うに抵抗４，５を論理回路出力１に対して接続し
た回路が考えられるが、この場合論理回路出力１
の正電圧系が断になるとドライブ用トランジスタ
２がONとなり負荷３が駆動されてしまう欠点が
あつた。これを防ぐ為第２図に示すように負電圧
系に変換するためトランジスタ６及び抵抗７から
成るインバータ回路を第１図の回路に追加する回
路も考えられるが、この場合には負電圧系が断と
なる過渡状態において一瞬ドライブ用トランジス
タ２がONとなり負荷３が駆動されてしまう欠点
が残る。 A conventional conversion circuit of this type is a circuit in which resistors 4 and 5 are connected to the logic circuit output 1 as shown in FIG.
There was a drawback that when the positive voltage system was disconnected, the drive transistor 2 was turned on and the load 3 was driven. To prevent this, a circuit can be considered in which an inverter circuit consisting of a transistor 6 and a resistor 7 is added to the circuit shown in Fig. 1 to convert it to a negative voltage system, as shown in Fig. 2, but in this case, the negative voltage system is There remains a drawback that the drive transistor 2 is momentarily turned on in a transient state of disconnection, causing the load 3 to be driven.
本考案は変換回路の電源供給方法及びしきい値
電圧の与え方を工夫する事になり、上記欠点を除
去した正電圧系から負電圧系への２値デジタル信
号レベル変換回路を提供するものである。 The present invention devises the power supply method and the threshold voltage application method of the conversion circuit, and provides a binary digital signal level conversion circuit from a positive voltage system to a negative voltage system that eliminates the above-mentioned drawbacks. be.
本考案は正電圧系、負電圧系の両方から電源を
供給される差動増幅回路と正電圧系の正常あるい
は断により電圧が正負に変化するバイアス回路か
らの電圧をしきい値として差動増幅回路で入力信
号の判定を行ない負電圧系回路に伝えることによ
り正電圧系断時に負電圧系負荷が駆動されること
がないようにしたものである。又負電圧系断時も
正電圧系により差動増幅回路は動作しているので
過渡的に負電圧系負荷が駆動されることもない。 This invention uses the voltage from the differential amplifier circuit, which is supplied with power from both the positive voltage system and the negative voltage system, and the bias circuit, whose voltage changes between positive and negative depending on whether the positive voltage system is normal or disconnected, as the threshold, to perform differential amplification. By determining the input signal in the circuit and transmitting it to the negative voltage system circuit, the negative voltage system load is prevented from being driven when the positive voltage system is disconnected. Furthermore, even when the negative voltage system is disconnected, the differential amplifier circuit is operated by the positive voltage system, so that the negative voltage system load is not driven transiently.
以下図面を参照して本考案の一実施例を説明す
る。 An embodiment of the present invention will be described below with reference to the drawings.
第３図に本考案の実施例を示す。図において１
は論理回路出力、２はトランジスタ、３は負荷、
９は差動増幅回路、１０〜１３は抵抗、１４はレ
ベルシフトダイオード、１５はクランプダイオー
ドを示す。 FIG. 3 shows an embodiment of the present invention. In the figure 1
is the logic circuit output, 2 is the transistor, 3 is the load,
9 is a differential amplifier circuit, 10 to 13 are resistors, 14 is a level shift diode, and 15 is a clamp diode.
抵抗１２，１３及びダイオード１４，１５でバ
イアス回路を構成し、抵抗１３とダイオード１４
の接続点の電圧が正の一定電圧で且つ通常論理回
路のしきい値付近になるように抵抗１２，１３の
値は選択される。正電圧系断時この電圧は負の一
定電圧、すなわちダイオード１４，１５の電圧降
下の和となる。なおバイアス回路は本考案の回路
複数並列使用する場合でも共通に１つあればよ
い。差動増幅回路９は上記バイアス回路の電圧と
論理回路出力１を比較し結果を抵抗１０を介して
トランジスタ２に出力する。なお、論理回路出力
は負論理に、すなわち負荷を駆動するときしきい
値以下、負荷を駆動しないときしきい値以上とな
るようにしておく。従つて第３図の回路は正電圧
系が正常時は普通のレベル変換回路として働き、
負荷を駆動しない状態、すなわち入力がしきい値
以上のとき正電圧系が断となつてもしきい値が下
がることにより差動増幅回路９は同じ入力状態を
保つので負荷３が駆動されることはない。又負電
圧系が断となつた場合でも正電圧系により差動増
幅回路９は動作しており、バイアス回路よりのし
きい値電圧もダイオード１４により一定範囲に保
たれ差動増幅回路９の出力が反転することはなく
負荷３が駆動されることもない。 Resistors 12 and 13 and diodes 14 and 15 constitute a bias circuit, and resistor 13 and diode 14
The values of the resistors 12 and 13 are selected so that the voltage at the connection point is a constant positive voltage and is usually near the threshold of the logic circuit. When the positive voltage system is interrupted, this voltage becomes a constant negative voltage, that is, the sum of the voltage drops across the diodes 14 and 15. Note that even when a plurality of circuits of the present invention are used in parallel, only one bias circuit is required in common. The differential amplifier circuit 9 compares the voltage of the bias circuit with the logic circuit output 1 and outputs the result to the transistor 2 via the resistor 10. Note that the logic circuit output is set to negative logic, that is, below the threshold value when driving the load, and above the threshold value when not driving the load. Therefore, when the positive voltage system is normal, the circuit in Figure 3 works as a normal level conversion circuit.
When the load is not being driven, that is, when the input is above the threshold, even if the positive voltage system is disconnected, the threshold drops and the differential amplifier circuit 9 maintains the same input state, so the load 3 is not driven. do not have. Furthermore, even if the negative voltage system is disconnected, the differential amplifier circuit 9 is operated by the positive voltage system, and the threshold voltage from the bias circuit is also maintained within a certain range by the diode 14, so that the output of the differential amplifier circuit 9 is not reversed and the load 3 is not driven.
以上説明したように正電圧系の正常・断により
正・負に変化する電圧を発生するバイアス回路を
正・負両電圧系から電源を供給される差動増幅回
路を組み合せることにより正・負どちらの電圧系
が断となつても負荷を誤つて駆動することなくそ
れだけ信頼度が高くかつ扱いが容易なレベル変換
を行なうことができる。 As explained above, a bias circuit that generates a voltage that changes between positive and negative depending on whether the positive voltage system is normal or disconnected can be combined with a differential amplifier circuit that is supplied with power from both the positive and negative voltage systems. Even if either voltage system is disconnected, the load will not be erroneously driven, and level conversion can be performed with higher reliability and ease of handling.
第１図及び第２図は従来のレベル変換回路図、
第３図は本考案の一実施例を示す回路図である。
図において、１……論理回路の出力、２……負
荷駆動用トランジスタ、３……負荷、４，５……
抵抗、６……トランジスタ、７，８……抵抗、９
……差動増幅回路、１０〜１３……抵抗、１４…
…レベルシフトダイオード、１５……クランプダ
イオード。
Figures 1 and 2 are conventional level conversion circuit diagrams,
FIG. 3 is a circuit diagram showing an embodiment of the present invention. In the figure, 1...Output of logic circuit, 2...Load driving transistor, 3...Load, 4, 5...
Resistor, 6... Transistor, 7, 8... Resistor, 9
... Differential amplifier circuit, 10 to 13 ... Resistor, 14 ...
...Level shift diode, 15...Clamp diode.
Claims (1)
が断のとき負の一定電圧を発生するバイアス回路
の出力を正電圧系、負電圧系から電源が係給され
る差動増幅回路の一方の入力に接続し、前記正電
圧系又は負電圧系が断のとき負電圧系への出力が
必ず論理「０」となるように構成することにより
正電圧系から負電圧系への２値デジタル信号レベ
ル変換を行なうことを特徴とするレベル変換回
路。 The output of the bias circuit, which generates a constant positive voltage when the positive voltage system is normal and a constant negative voltage when the positive voltage system is disconnected, is connected to the output of the differential amplifier circuit, which is supplied with power from the positive voltage system and the negative voltage system. By connecting to one input and configuring so that when the positive voltage system or the negative voltage system is disconnected, the output to the negative voltage system is always logic "0", the binary value from the positive voltage system to the negative voltage system can be changed. A level conversion circuit characterized by performing digital signal level conversion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4890180U JPS641798Y2 (en) | 1980-04-11 | 1980-04-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4890180U JPS641798Y2 (en) | 1980-04-11 | 1980-04-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56150130U JPS56150130U (en) | 1981-11-11 |
| JPS641798Y2 true JPS641798Y2 (en) | 1989-01-17 |
Family
ID=29643890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4890180U Expired JPS641798Y2 (en) | 1980-04-11 | 1980-04-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS641798Y2 (en) |
-
1980
- 1980-04-11 JP JP4890180U patent/JPS641798Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56150130U (en) | 1981-11-11 |
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