JPS6415823A - Shifter device - Google Patents

Shifter device

Info

Publication number
JPS6415823A
JPS6415823A JP17186187A JP17186187A JPS6415823A JP S6415823 A JPS6415823 A JP S6415823A JP 17186187 A JP17186187 A JP 17186187A JP 17186187 A JP17186187 A JP 17186187A JP S6415823 A JPS6415823 A JP S6415823A
Authority
JP
Japan
Prior art keywords
characters
character
data
register
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17186187A
Other languages
Japanese (ja)
Inventor
Shigenori Takegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17186187A priority Critical patent/JPS6415823A/en
Publication of JPS6415823A publication Critical patent/JPS6415823A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To increase the working speed of a shifter containing a put-close-to- right function for operand data by suppressing all characters set at higher levels than a start character. CONSTITUTION:A suppression circuit 19 delivers the characters in number corresponding to those characters stored in a length register 17 including the lowest level one out of the shift output data. At the same time, the circuit 19 suppresses other characters. In this case, a character valid signal generating part 41 uses three lower level bits P0-P2 received from the register 17 as inputs and delivers the character valid signals a0-a6. For instance, the signal a0 is valid only when the bits P0-P2 are equal to '0' (the character number multiplied by 8). Then a selector 20 selects the output of the circuit 19 when the control is needed for data characters and then selects the data stored in a 3rd register 13 when said control is not needed respectively.
JP17186187A 1987-07-09 1987-07-09 Shifter device Pending JPS6415823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17186187A JPS6415823A (en) 1987-07-09 1987-07-09 Shifter device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17186187A JPS6415823A (en) 1987-07-09 1987-07-09 Shifter device

Publications (1)

Publication Number Publication Date
JPS6415823A true JPS6415823A (en) 1989-01-19

Family

ID=15931145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17186187A Pending JPS6415823A (en) 1987-07-09 1987-07-09 Shifter device

Country Status (1)

Country Link
JP (1) JPS6415823A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710470A (en) * 1991-04-04 1998-01-20 Ebara Corporation Hydrodynamic bearing assembly
WO2003090964A1 (en) * 2002-04-23 2003-11-06 Sony Corporation Polishing system and polishing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710470A (en) * 1991-04-04 1998-01-20 Ebara Corporation Hydrodynamic bearing assembly
WO2003090964A1 (en) * 2002-04-23 2003-11-06 Sony Corporation Polishing system and polishing method

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