JPS6413747U - - Google Patents
Info
- Publication number
- JPS6413747U JPS6413747U JP1987110391U JP11039187U JPS6413747U JP S6413747 U JPS6413747 U JP S6413747U JP 1987110391 U JP1987110391 U JP 1987110391U JP 11039187 U JP11039187 U JP 11039187U JP S6413747 U JPS6413747 U JP S6413747U
- Authority
- JP
- Japan
- Prior art keywords
- housing
- led chip
- conductive pattern
- current limiting
- limiting resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 230000000694 effects Effects 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Description
第1図は本考案に係る灯具の一実施例を示す一
部破断状態の平面図、第2図及び第3図は同実施
例の正面図及び側面図、第4図は同実施例におけ
るLEDチツプの実装状態を示す正面図、第5図
は第4図の−線断面図、第6図は従来例を示
す一部破断状態の平面図である。 1……ハウジング、1A……反射枠、2……導
電パターン、3……LEDチツプ、4……金線、
5……透明樹脂、6……電流制限用抵抗、7……
ワイヤーハーネス、8……アウターレンズ。
部破断状態の平面図、第2図及び第3図は同実施
例の正面図及び側面図、第4図は同実施例におけ
るLEDチツプの実装状態を示す正面図、第5図
は第4図の−線断面図、第6図は従来例を示
す一部破断状態の平面図である。 1……ハウジング、1A……反射枠、2……導
電パターン、3……LEDチツプ、4……金線、
5……透明樹脂、6……電流制限用抵抗、7……
ワイヤーハーネス、8……アウターレンズ。
Claims (1)
- ハウジングの後部内面に所定数の反射枠を一体
に成形するとともに、所定形状の導電パターンを
形成してLEDチツプ、電流制限用抵抗、逆電圧
保護ダイオードなどを装着し、更にLEDチツプ
の部分を透明樹脂によりレンズ作用を持つように
被覆し、ハウジングの前面にアウターレンズを取
付けたことを特徴とする灯具。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987110391U JPH0514530Y2 (ja) | 1987-07-17 | 1987-07-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987110391U JPH0514530Y2 (ja) | 1987-07-17 | 1987-07-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6413747U true JPS6413747U (ja) | 1989-01-24 |
JPH0514530Y2 JPH0514530Y2 (ja) | 1993-04-19 |
Family
ID=31347505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987110391U Expired - Lifetime JPH0514530Y2 (ja) | 1987-07-17 | 1987-07-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0514530Y2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010111231A (ko) * | 2000-06-09 | 2001-12-17 | 김윤철 | 칩 엘이디의 구조 및 그 제조방법 |
JP2010524260A (ja) * | 2007-04-13 | 2010-07-15 | フェアチャイルド セミコンダクター コーポレイション | 光カプラ・パッケージ |
-
1987
- 1987-07-17 JP JP1987110391U patent/JPH0514530Y2/ja not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010111231A (ko) * | 2000-06-09 | 2001-12-17 | 김윤철 | 칩 엘이디의 구조 및 그 제조방법 |
JP2010524260A (ja) * | 2007-04-13 | 2010-07-15 | フェアチャイルド セミコンダクター コーポレイション | 光カプラ・パッケージ |
Also Published As
Publication number | Publication date |
---|---|
JPH0514530Y2 (ja) | 1993-04-19 |