JPS6410391A - Condition change detecting device - Google Patents

Abstract

PURPOSE:To detect the condition change of the supervising signals of numerous types with a simple constitution by providing a parallel/serial converter to convert the parallely fetched supervising signal to a serial signal. CONSTITUTION:By a load signal LP of a frequency (f) from a counter 16, supervising signals D1-D8 are fetched to a parallel/serial converter 10, synchronized to a clock signal phi1 of a frequency 8f from a dividing circuit 11 and converted to a serial signal C of eight bits. The converted serial signal C is successively inputted to shift registers 12 and 13. A condition change detecting device 14 compares the respective bits of the supervising signal C in a present sample period from the converter 10, a signal B in the preceding time from the register 12 and a supervising signal A twice before from the register 13 and a signal SCP according to the logic that a condition change output=AB'C'+A'BC. The signal SCP is stored by an FIFO15 and a control part reads it through a data bus DB and detects the condition change. In this expression, the A', B' and C' respectively express the reversing signals of the A, B and C.