JPS639749B2 - - Google Patents
Info
- Publication number
- JPS639749B2 JPS639749B2 JP57080936A JP8093682A JPS639749B2 JP S639749 B2 JPS639749 B2 JP S639749B2 JP 57080936 A JP57080936 A JP 57080936A JP 8093682 A JP8093682 A JP 8093682A JP S639749 B2 JPS639749 B2 JP S639749B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- semiconductor element
- ceramic substrate
- metal ring
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 48
- 239000004065 semiconductor Substances 0.000 claims description 36
- 239000000919 ceramic Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 17
- 230000005611 electricity Effects 0.000 claims 1
- 239000010931 gold Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 239000006023 eutectic alloy Substances 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置にかかり、とくにセラミツ
ク基板に搭載され、金属シールにより気密封止さ
れる半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device mounted on a ceramic substrate and hermetically sealed with a metal seal.
本発明は、第1図aに示すように、セラミツク
基板1にキヤビテイと称する凹部2を設け、その
底に半導体素子3を固着し、半導体素子の電極と
ボンデイングパツド4とを金属細線5で接続した
後、セラミツク基板上に半導体素子を取り囲むよ
うにロウ付けされた金属リング6に金属キヤツプ
7をかぶせ、その周囲を溶融して封止するいわゆ
るシームウエルド法による半導体装置や、第1図
bのように、金属リングを設けずに、タングステ
ンWやモリブデンMoメタライズした後にニツケ
ルNi及び金Auをめつきして環状の金属層(図示
せず)を設け、この上に例えば金Auと錫Snの合
金板を挾んでセラミツクキヤツプや金属板をシー
ルする共晶合金シール法など、半導体素子の周囲
に気密封止するための環状の金属層を設けた半導
体装置を含むものである。 As shown in FIG. 1a, the present invention provides a recessed portion 2 called a cavity in a ceramic substrate 1, a semiconductor element 3 is fixed to the bottom of the recessed part 2, and an electrode of the semiconductor element and a bonding pad 4 are connected with a thin metal wire 5. After connection, a metal ring 6 brazed on a ceramic substrate so as to surround the semiconductor element is covered with a metal cap 7, and the periphery thereof is melted to seal the semiconductor device. As shown in the figure, a ring-shaped metal layer (not shown) is formed by metallizing tungsten W or molybdenum Mo without providing a metal ring, and then plating nickel Ni and gold Au, and on top of this, for example, gold Au and tin Sn are plated. This includes semiconductor devices in which a ring-shaped metal layer is provided around a semiconductor element for airtight sealing, such as the eutectic alloy sealing method in which a ceramic cap or metal plate is sealed by sandwiching an alloy plate.
以上のような環状金属部封止型の半導体装置に
用いられるセラミツク基板は、その外部リードピ
ン8の数が同じで外形形状が同一であつても、そ
れに搭載する半導体素子3の回路機能によつて、
内部の配線パタンを変える必要があつた。即ち、
環状金属層の電位を半導体素子3と同じ接地の電
位にしたい場合、第2図のように、キヤビテイ2
の底面から延在した金属配線をスルーホール9を
介してキヤツプ7と接続するなどの工夫が必要と
なり、スルーホールのあるものとないものの2種
類を用意しなければならなかつた。 Even if the ceramic substrate used in the above-mentioned ring-shaped metal sealed semiconductor device has the same number of external lead pins 8 and the same external shape, the circuit function of the semiconductor element 3 mounted on it differs. ,
It was necessary to change the internal wiring pattern. That is,
If you want the potential of the annular metal layer to be the same as the ground potential of the semiconductor element 3, as shown in FIG.
It was necessary to devise measures such as connecting the metal wiring extending from the bottom of the cap to the cap 7 via the through hole 9, and two types had to be prepared: one with a through hole and one without.
このことは、セラミツク基板の種類が増加する
ことになり、ひいては半導体装置のコスト・アツ
プを招くことになる。 This results in an increase in the types of ceramic substrates, which in turn leads to an increase in the cost of semiconductor devices.
本発明は、上記の欠点を解消するためになされ
たものであり、金属リングの内側のセラミツク基
板表面に金属リングから延びた金属ターミナルを
設け、更に半導体素子の裏面または電極と導通し
た金属配線の延長部が前記金属ターミナルに接近
しかつ電気的に離れて設けられ、両者間は金属細
線により電気的導通を可能としたことを特徴とす
るものであり、その目的とするところは同一セラ
ミツク基板を用いて種々の半導体素子が搭載でき
るよう汎用性を持たせることにより、半導体装置
のコスト・ダウンを計ることにある。 The present invention has been made to eliminate the above-mentioned drawbacks, and includes a metal terminal extending from the metal ring on the surface of the ceramic substrate inside the metal ring, and further a metal terminal connected to the back surface of the semiconductor element or the electrode. The extension part is provided close to the metal terminal and electrically separated from the metal terminal, and electrical continuity is enabled between the two by means of a thin metal wire, and its purpose is to connect the same ceramic substrate. The purpose is to reduce the cost of semiconductor devices by making them versatile so that various semiconductor elements can be mounted thereon.
以下に、本発明を詳細に説明する。 The present invention will be explained in detail below.
半導体素子裏面と金属リングとを同一電位に維
持する場合の実施例を第3図に示す。第3図は、
金属リング6の内部を一部分切り出して描いた断
面斜視図である。セラミツク基板1に設けたキヤ
ビテイ2の底部にはアイランドと称する金属層1
0を設け、これに半導体素子3を固着する。アイ
ランドは通常セラミツク基板の焼成前にタングス
テンWやモリブデンMoの粒子を分散させたイン
クをスクリーン印刷し、焼成した後、ニツケル
Ni更に金Auをめつきして形成される。半導体素
子3のアイランド10上への固着は金Auとシリ
コンSiの共晶合金やハンダで行なわれる。次に半
導体素子3の電極11とボンデイングパツト4と
を金AuやアルミニウムAlを主成分とする金属細
線5で接続する。ボンデイングパツドはそれぞれ
外部リードピンに電気的に導通している。アイラ
ンド10からは、図中に破線で示したように延長
部12があり、これはスルーホール13を通して
セラミツク基板表面のパツド14に接続されてい
る。一方、金属リング6からは金属ターミナル1
5がパツド14に接近して延びている。以上の構
造を有することにより、金属リングがアイランド
と同電位を維持する必要のある時は、金属細線1
6でパツド14と金属ターミナル15とを接続す
ればよいし、不要な場合はこの接続をしなければ
よく、同一のセラミツク基板が使用できる。 FIG. 3 shows an embodiment in which the back surface of the semiconductor element and the metal ring are maintained at the same potential. Figure 3 shows
2 is a cross-sectional perspective view depicting a partially cut out interior of the metal ring 6. FIG. A metal layer 1 called an island is provided at the bottom of a cavity 2 provided on a ceramic substrate 1.
0 is provided, and the semiconductor element 3 is fixed to this. Islands are usually made by screen-printing ink containing particles of tungsten W or molybdenum Mo before firing the ceramic substrate, and then printing it with nickel after firing.
Formed by plating Ni with gold and Au. The semiconductor element 3 is fixed onto the island 10 using a eutectic alloy of gold (Au) and silicon (Si) or solder. Next, the electrode 11 of the semiconductor element 3 and the bonding pad 4 are connected with a thin metal wire 5 whose main component is gold Au or aluminum Al. Each bonding pad is electrically connected to an external lead pin. From the island 10 there is an extension 12, as indicated by the broken line in the figure, which is connected through a through hole 13 to a pad 14 on the surface of the ceramic substrate. On the other hand, metal terminal 1 is connected from metal ring 6.
5 extends close to pad 14. With the above structure, when the metal ring needs to maintain the same potential as the island, the thin metal wire 1
6, the pad 14 and the metal terminal 15 may be connected, or if unnecessary, this connection may be omitted, and the same ceramic substrate can be used.
また、同様の構造で、第4図に示したように、
特定のボンデイングパツド4と金属リングとを同
電位に保ちたい時も、そのボンデイングパツドの
延長部からスルーホール13を介して設けたパツ
ド14と、金属リングから延びた金属ターミナル
とを接近させておけば、金属細線16を接続する
ことにより行なえる。 Also, with a similar structure, as shown in Figure 4,
When it is desired to keep a specific bonding pad 4 and a metal ring at the same potential, the pad 14 provided through the through hole 13 from the extension of the bonding pad and the metal terminal extending from the metal ring are brought close to each other. This can be done by connecting the thin metal wires 16.
パツド14とアイランドまたは内部配線との接
続を必らずしもスルーホールを介する必要はな
い。例えば、第5図のように、階段状の凹部の壁
面を金属配線を這わせ(側面メタライズ)、パツ
ド14に接続してもよい。本例の場合、アイラン
ド10と内部配線とパツドと半導体素子の電極と
を全て接続した例で示した。 The connection between the pad 14 and the island or internal wiring does not necessarily have to be through a through hole. For example, as shown in FIG. 5, metal wiring may be run along the wall surface of the stepped recess (side surface metallization) and connected to the pad 14. In this example, the island 10, internal wiring, pads, and electrodes of the semiconductor element are all connected.
また、第6図のようにアイランド10から延在
した内部配線12が、スルーホール17を介して
接続し更に上段でパツド14に接続する一方、金
属リング6の直下からスルーホール18を介して
金属ターミナル15を形成し、両者を金属細線1
6で接続することもできる。 Further, as shown in FIG. 6, the internal wiring 12 extending from the island 10 is connected through the through hole 17 and further connected to the pad 14 at the upper stage, while the metal wiring 12 is connected through the through hole 18 from directly below the metal ring 6. A terminal 15 is formed, and both are connected by a thin metal wire 1.
6 can also be connected.
以上は、代表的な半導体装置であるDIP(Dual
Inline Package)型について説明したが、本発
明はその外形形状には制約されない。例えば、
PIP(Plug In Package)型やチツプキヤリア型
シングルインライン型等の半導体装置にも適用で
きる。 The above is a typical semiconductor device, DIP (Dual
Although the Inline Package type has been described, the present invention is not limited to its external shape. for example,
It can also be applied to semiconductor devices such as PIP (Plug In Package) type and chip carrier type single in-line type.
また組立方式は、ワイヤ・ボンデイング法に限
られることはなく、TAB法など他の組立法によ
る半導体装置にも適用できる。 Furthermore, the assembly method is not limited to the wire bonding method, and can also be applied to semiconductor devices using other assembly methods such as the TAB method.
更に、使用される材料も以上に挙げたものに限
らず他の材料も使用できることは言うまでもな
い。 Furthermore, it goes without saying that the materials used are not limited to those listed above, and other materials can also be used.
以上、詳細に説明したように本発明によれば、
半導体素子を搭載するセラミツク基板の汎用性が
高くなり、1種類のセラミツク基板で多種類の半
導体素子の搭載が可能となり、ひいては半導体装
置のコストダウンを可能とすることができる。 As described above in detail, according to the present invention,
The versatility of the ceramic substrate on which semiconductor elements are mounted is increased, and it becomes possible to mount many types of semiconductor elements on one type of ceramic substrate, thereby making it possible to reduce the cost of semiconductor devices.
第1図a,bは金属封止型セラミツク半導体装
置を説明する断面図、第2図は従来の半導体装置
の断面図、第3図乃至第6図は本発明の実施例を
示す断面斜視図である。
図中で、1……セラミツク基板、2……キヤビ
テイ、3……半導体素子、4……ボンデイングパ
ツド、5……金属細線、6……金属リング、7…
…キヤツプ、8……外部リードピン、9……スル
ーホール、10……アイランド、11……電極、
12……内部配線の延長部、13……スルーホー
ル、14……パツド、15……金属ターミナル、
16……金属細線である。
FIGS. 1a and 1b are cross-sectional views illustrating a metal-sealed ceramic semiconductor device, FIG. 2 is a cross-sectional view of a conventional semiconductor device, and FIGS. 3 to 6 are cross-sectional perspective views showing embodiments of the present invention. It is. In the figure, 1...ceramic substrate, 2...cavity, 3...semiconductor element, 4...bonding pad, 5...metal thin wire, 6...metal ring, 7...
... Cap, 8 ... External lead pin, 9 ... Through hole, 10 ... Island, 11 ... Electrode,
12... Internal wiring extension, 13... Through hole, 14... Pad, 15... Metal terminal,
16...It is a thin metal wire.
Claims (1)
ミツク基板と、このセラミツク基板に接着し前記
半導体素子を取り囲むように形成した金属リング
と、その金属リングに固着されたキヤツプとを備
えた半導体装置において、前記金属リングに取り
囲まれた領域内の、前記セラミツク基板の表面に
接着しその金属リングと電気的に導通した金属タ
ーミナルの近くに、前記半導体素子の裏面または
前記半導体素子の表面の電極と電気的に導電した
導電層が設けられ、前記金属ターミナルと前記導
電層とは両者間を金属細線で接続したときに導通
状態となり、金属細線で接続しないときは電気的
に離れた状態となることを特徴とする半導体装
置。1. A semiconductor device comprising a semiconductor element, a ceramic substrate on which the semiconductor element is mounted, a metal ring bonded to the ceramic substrate and formed to surround the semiconductor element, and a cap fixed to the metal ring, In the area surrounded by the metal ring, near the metal terminal that is adhered to the surface of the ceramic substrate and electrically conductive with the metal ring, there is a metal terminal that is electrically connected to the back surface of the semiconductor element or the electrode on the front surface of the semiconductor element. A conductive layer that conducts electricity is provided, and the metal terminal and the conductive layer are in a conductive state when they are connected with a thin metal wire, and are electrically separated when not connected with a thin metal wire. semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57080936A JPS58197863A (en) | 1982-05-14 | 1982-05-14 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57080936A JPS58197863A (en) | 1982-05-14 | 1982-05-14 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58197863A JPS58197863A (en) | 1983-11-17 |
JPS639749B2 true JPS639749B2 (en) | 1988-03-01 |
Family
ID=13732342
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57080936A Granted JPS58197863A (en) | 1982-05-14 | 1982-05-14 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58197863A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4705917A (en) * | 1985-08-27 | 1987-11-10 | Hughes Aircraft Company | Microelectronic package |
US5027191A (en) * | 1989-05-11 | 1991-06-25 | Westinghouse Electric Corp. | Cavity-down chip carrier with pad grid array |
-
1982
- 1982-05-14 JP JP57080936A patent/JPS58197863A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS58197863A (en) | 1983-11-17 |
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