JPS639307A - Current mirror circuit - Google Patents
Current mirror circuitInfo
- Publication number
- JPS639307A JPS639307A JP61154377A JP15437786A JPS639307A JP S639307 A JPS639307 A JP S639307A JP 61154377 A JP61154377 A JP 61154377A JP 15437786 A JP15437786 A JP 15437786A JP S639307 A JPS639307 A JP S639307A
- Authority
- JP
- Japan
- Prior art keywords
- current
- transistor
- resistor
- gate
- adjusting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔Ｍ東上の利用分針〕
本発明は電流ミラー回路に関し、特に出力電流を調整可
能な午導体果償（ロ）路化に通した電流ミラー回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Minute hand used by M Tojo] The present invention relates to a current mirror circuit, and more particularly to a current mirror circuit in which the output current is passed through an adjustable meridian conductor compensation circuit.
従来の電流ミラー回路を第３図に示す。入力電流源ＩＩ
Ｎよシ供給される電流はドレイ／−ゲート短絡トランジ
スタＱ１で電圧にに換され、ミラー側トランジスタＱ！
のゲートがバイアスする。このゲートバイアスに応じて
ミラー側トラノンスタＱ２からは出力電流工＠が流れる
。しかし、この回路において入力電流源ＩＩＮからの電
流と出１ａＩｏとの相対″ｆ［Ｉは、トランジスタＱｔ
、（＝ｈの閾値電圧ＶＴやサイズ（Ｗ／Ｌ）のバラツ
キのために、高ｔ５ｋを得ることがむずかしかった。A conventional current mirror circuit is shown in FIG. Input current source II
The current supplied to N is converted into a voltage by the drain/-gate shorted transistor Q1, and the mirror side transistor Q!
gate is biased. According to this gate bias, an output current flows from the mirror-side trannon star Q2. However, in this circuit, the relative value ``f[I'' between the current from the input current source IIN and the output 1aIo is the transistor Qt
, (=h) It was difficult to obtain a high t5k due to variations in the threshold voltage VT and size (W/L).
この欠点を改良した従来例を第４図に示す。この従来例
も、基本的にはＷＪ３図と同様で入力ｌｆＥ課Ｉ Ｉ
ＮとトランジスタＱ、、Ｑ、からなっており。A conventional example in which this drawback has been improved is shown in FIG. This conventional example is also basically the same as the WJ3 diagram, and the input lfE section I
It consists of N and transistors Q,,Q,.
更に２つの調贅可能な憶抗器Ｒ，，Ｒ，４が、％１０
ＳトランジスタＱ１．Ｑ２の各ソースと接地電位との間
に挿入されている。これらの抵抗器ａｉ、ａ４をトリミ
ング等により調整することにより出力電流工・を任意に
設定でき、入力電流源ＩＩＮからの電流と出力電流工０
との相対比を調節できる。Two more adjustable capacitors R,,R,4 are %10
S transistor Q1. It is inserted between each source of Q2 and the ground potential. By adjusting these resistors ai and a4 by trimming etc., the output current can be set arbitrarily, and the current from the input current source IIN and the output current can be set as desired.
The relative ratio can be adjusted.
上述した従来の電流ミラー回路において可変抵よる方法
等で実現できる。しかしながら、前者においては別にレ
ーザートリミング装置が必要になり設備が高額になる。This can be realized by using a variable resistor in the conventional current mirror circuit described above. However, in the former case, a separate laser trimming device is required, making the equipment expensive.
また後者においては抵抗値を広範囲に変化されることや
微小に変化させることがむずかしいという欠点がある。Furthermore, the latter has the disadvantage that it is difficult to vary the resistance value over a wide range or to vary it minutely.
本発明の電流ミラー回路は、入力電流源に出力電極が接
続され、この出力電極と制御電極が磁路された第１のト
ランジスタと、この第１のトランジスタの出力電極と廿
１＃電極との短絡点に制御電極が接＋−ｉされた第２の
トランジスタと、第１および第２のトランジスタの各共
通電極と基準電位間にそれぞれ接続された第１および第
２の抵抗と、第１および第２の抵抗の少くとも一万に調
整用電流を供給する制＃て流源とを備えている。The current mirror circuit of the present invention includes a first transistor in which an output electrode is connected to an input current source and a control electrode is connected to the output electrode in a magnetic path; a second transistor having a control electrode connected to the short-circuit point; first and second resistors respectively connected between the common electrodes of the first and second transistors and a reference potential; and a control current source for supplying a regulating current to at least 10,000 of the second resistor.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示すものである。FIG. 1 shows an embodiment of the present invention.
入力電流ＩＩＮはトランジスタＱ、のドレインとゲート
に従続され、更にトランジスタＱ２のゲートに接続され
ている。トランジスタＱ２のドレイ／から出力電流工０
が取シ出されている。各トランジスタＱ１とＱ２のソー
スと接地電位間には直列に同抵抗値の第１の抵抗比！及
び第２の抵抗Ｒ２が接続されている。これら第１または
第２の抵抗Ｒ１またはＲ２には制御電流源１かも調整用
電流をスイッチ２によりて選択面に供給されている０２
個の抵抗Ｒ，、ＦＬ、の抵抗値は、はぼ同じ１直であれ
ばよく、通常得られる相対精度で充分である。Input current IIN follows the drain and gate of transistor Q, and is further connected to the gate of transistor Q2. The output current from the drain of transistor Q2 is 0.
has been taken out. A first resistance ratio of the same resistance value is connected in series between the sources of each transistor Q1 and Q2 and the ground potential! and a second resistor R2 are connected. To these first or second resistors R1 or R2, a control current source 1 or an adjusting current is supplied to the selected surface by a switch 2.
The resistance values of the resistors R, , FL only need to be approximately the same, and the relative accuracy normally obtained is sufficient.
次に動作を説明する。まず、第１図の回路を７リコン基
根上に作成した結果、トランジスタＱ２の電流がトラン
ジスタＱｌの電流よシ少ない場合について考える。この
場合、トランジスタＱ２の電流を増やすためにトランジ
スタＱ２のゲート電圧を大きくすればよい。そのために
は調聚用電流を第１の抵抗Ｒ１に流し込んで節点Ａの電
位を上げ、トランジスタＱ、のゲートをバイアスする電
圧を上げる。この時、調整用電流の電流頃をＡ聚すれば
トランジスタＱ！の電流を任意に増力０させることがで
き、入／出力電流の相対比を調仝することができる。Next, the operation will be explained. First, let us consider the case where the circuit of FIG. 1 is created on a 7-recon base and the current of transistor Q2 is smaller than the current of transistor Ql. In this case, the gate voltage of the transistor Q2 may be increased in order to increase the current of the transistor Q2. To do this, a tuning current is flowed into the first resistor R1 to raise the potential at node A, thereby increasing the voltage biasing the gate of transistor Q. At this time, if the current of the adjustment current is A, then the transistor Q! The current can be arbitrarily boosted to 0, and the relative ratio of input/output current can be determined.
次に、トランジスタＱ２の電流がトランジスタＱ１の電
流より多い場合について考える。この場合トランジスタ
Ｑ８のゲート・ソース間１王ＶＧＳを小さくすればよい
。そのためには調整用電流を第２の抵抗比２に流し込ん
で節点すの電位を持ち上げることによって、トランジス
タＱ！のゲート・ソース間電圧ＶＧＳを小さくし電流を
減らす。Next, consider the case where the current in transistor Q2 is greater than the current in transistor Q1. In this case, the voltage VGS between the gate and source of the transistor Q8 may be reduced. To do this, by injecting an adjustment current into the second resistance ratio 2 and raising the potential of the node S, the transistor Q! Reduce the current by reducing the gate-source voltage VGS.
このように調整用電流を調をしてトランジスタもの電流
を任意に減少させることによって出力電光をＡＥｋする
ことができる。In this way, by adjusting the adjustment current to arbitrarily reduce the current flowing through the transistor, the output lightning can be reduced to AEk.
ここで文相される制御電流源１は電流出刃形ＤＡＣで構
成すれはよく、そのＤＡＣのフルスケール電流や分解能
を変えることによって広範囲、セして微小にミラー回路
の入／出力電流の相？ｌ比を調毀できる。The control current source 1 discussed here is preferably composed of a current output type DAC, and by changing the full scale current and resolution of the DAC, it is possible to control the phase of the input/output current of the mirror circuit over a wide range or minutely. You can change the l ratio.
〔実施例２つ 第２図は本発明の他の実地例の回路図である。[Two examples FIG. 2 is a circuit diagram of another practical example of the present invention.
トランジスタＱ、とＱ２および入力電流源■ＸＮからな
る構成は第１図の一実施例と同じで、トランジスタＱ１
のソースと接地電位間にのみ直列に第１の抵抗比１が挿
入されておプ、更にこの第］の抵抗Ｒ１に電流を流し込
む制御電流源１を有している。かかる実施例では、トラ
ンジスタＱ２を流れる電流はトランジスタＱ１の１［よ
りわずかに少なくなるように、トランジスタＱ１のトラ
７ジスタサイズ（Ｗ／Ｌ）をトランジスタＱ２より大き
めに設計している。The configuration consisting of transistors Q and Q2 and input current source XN is the same as the embodiment in FIG.
A first resistance ratio 1 is inserted in series only between the source of the resistor R1 and the ground potential, and a controlled current source 1 is further provided to flow current into the first resistor R1. In this embodiment, the transistor size (W/L) of the transistor Q1 is designed to be larger than that of the transistor Q2 so that the current flowing through the transistor Q2 is slightly less than 1 of the transistor Q1.
次に動作を説明する。第２因の回路はンリコノ基板上（
作成した結果、トランジスタＱ、の電流がトランジスタ
Ｑ８の電流より少なくなるよ５に設計されているので、
トランジスタＱ２のゲート電圧を持ち上げて電流を増加
させれぼよい。このために調整用電流を第１の抵抗Ｒ１
に流し込み、節点Ｂの電位を上げ、トランジスタＱ２の
ゲート電圧を大きくする。このようにすることによって
、ｖ４警用電流によって入／出力を流の相対比を調整す
ることができる。Next, the operation will be explained. The circuit of the second cause is on the PCB (
As a result of the creation, the current of transistor Q is designed to be less than the current of transistor Q8, so
The current may be increased by raising the gate voltage of transistor Q2. For this purpose, the adjustment current is connected to the first resistor R1.
, the potential at node B is increased, and the gate voltage of transistor Q2 is increased. By doing so, the relative ratio of input/output flow can be adjusted by the v4 warning current.
以上説明したように、本発明１丁、％、流ミラー回路を
構成する各トランジスタの共通電極と基準電位間に抵抗
を挿入し、その抵抗に調蟹用１！流を流すことによシ、
ミラー回路の入／出力電流の比を広範囲に、かつ精密に
調整できる０以上の説明はｈｉｏｓトランジスタを例に
取ったが、バイポーラトランジスタにおいても同様の効
果が得られるのは明らかである。As explained above, according to the present invention, a resistor is inserted between the common electrode of each transistor constituting the current mirror circuit and the reference potential, and the resistor is connected to the resistor. It is better to let the flow flow,
The explanation of the ability to adjust the input/output current ratio of the mirror circuit over a wide range and with precision takes the HIOS transistor as an example, but it is clear that the same effect can be obtained with a bipolar transistor as well.
第】図は本発明による一実施例を示す回路図、第２図は
本発明による他の実施例を示す回路図である。第３図は
従来例を示す回路図、第４図は池の従来例を示す回路図
である。
Ｑ＋−Ｑ−・・・・・・ＭＯＳトランジスタ、Ｒ１−Ｒ
２・・・・・抵抗器、Ｒ３−Ｒ４・・・・・可変抵抗器
、１・・・・・・制御を流源、２・・・・・・スイッチ
、３・・パ°出力端子０
＼＋１
坪 ／ＩＩ！１
ｙ ２ 図
ＶＤ７）
茅 ３１５
ＤＤ
＄４ＴＭ1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram showing another embodiment of the present invention. FIG. 3 is a circuit diagram showing a conventional example, and FIG. 4 is a circuit diagram showing a conventional example of a pond. Q+-Q-...MOS transistor, R1-R
2...Resistor, R3-R4...Variable resistor, 1...Control current source, 2...Switch, 3...P° output terminal 0 \+1 tsubo /II! 1 y 2 Figure VD7) Kaya 315 DD $4TM
Claims (1)
第１のトランジスタと、前記共通接続された出力電極と
制御電極にその制御電極が接続された第２のトランジス
タと、前記第１および第２のトランジスタの少くとも一
方の共通電極と基準電位点間に接続された抵抗と、該抵
抗の所定のものに調整用電流を供給する制御電流源とを
含み、前記第２のトランジスタの出力電極から出力電流
を得る電流ミラー回路。a first transistor whose control electrode is connected to the commonly connected output electrode and the control electrode; a second transistor whose control electrode is connected to the commonly connected output electrode and the control electrode; a resistor connected between the common electrode of at least one of the transistors and a reference potential point, and a control current source that supplies an adjustment current to a predetermined one of the resistors, the output electrode of the second transistor Current mirror circuit to obtain output current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61154377A JPS639307A (en) | 1986-06-30 | 1986-06-30 | Current mirror circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61154377A JPS639307A (en) | 1986-06-30 | 1986-06-30 | Current mirror circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639307A true JPS639307A (en) | 1988-01-16 |
Family
ID=15582819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61154377A Pending JPS639307A (en) | 1986-06-30 | 1986-06-30 | Current mirror circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639307A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03222470A (en) * | 1990-01-29 | 1991-10-01 | Mitsubishi Electric Corp | Threshold voltage generation circuit |
| JP2013545363A (en) * | 2010-10-15 | 2013-12-19 | エス．シー． ジョンソン アンド サン、インコーポレイテッド | Application specific integrated circuit including motion detection system |
-
1986
- 1986-06-30 JP JP61154377A patent/JPS639307A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03222470A (en) * | 1990-01-29 | 1991-10-01 | Mitsubishi Electric Corp | Threshold voltage generation circuit |
| JP2013545363A (en) * | 2010-10-15 | 2013-12-19 | エス．シー． ジョンソン アンド サン、インコーポレイテッド | Application specific integrated circuit including motion detection system |
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