JPS639125A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS639125A JPS639125A JP15293586A JP15293586A JPS639125A JP S639125 A JPS639125 A JP S639125A JP 15293586 A JP15293586 A JP 15293586A JP 15293586 A JP15293586 A JP 15293586A JP S639125 A JPS639125 A JP S639125A
- Authority
- JP
- Japan
- Prior art keywords
- cover film
- stress
- portions
- wiring pattern
- resin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000013039 cover film Substances 0.000 claims abstract description 28
- 239000010408 film Substances 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 239000011347 resin Substances 0.000 abstract description 19
- 229920005989 resin Polymers 0.000 abstract description 19
- 239000010410 layer Substances 0.000 abstract description 18
- 239000012141 concentrate Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
（ｆｌＡ要）
本発明は特に樹脂封止された半導体装置において、
樹脂と半導体チップとの熱膨張率の違いによって半導体
チップのカバー膜が破壊され易い問題点を解決するため
、
配線パターン裏面に設けられている層間絶縁膜の配線パ
ターンエツジに対向する部分を丸味を帯びた形状にする
ことにより、
カバー膜の局所に応力が集中するのを防止し得、カバー
膜の破壊を未然に防止し得るようにしたものである。[Detailed Description of the Invention] (Requires flA) The present invention solves the problem that, particularly in resin-sealed semiconductor devices, the cover film of the semiconductor chip is easily destroyed due to the difference in thermal expansion coefficient between the resin and the semiconductor chip. Therefore, by rounding the part of the interlayer insulating film provided on the backside of the wiring pattern that faces the wiring pattern edge, it is possible to prevent stress from concentrating locally on the cover film. This is to prevent destruction.
本発明は半導体装置、特に、樹脂封止された半導体装置
に関する。半導体装置は今侵更に種々の方面で多く用い
られる傾向にあるが、この場合、カバー膜の局所に応力
が集中するのを防止してカバー膜の破壊を未然に防止し
得、信頼性の高い強固な半導体装置が必要とされる。The present invention relates to a semiconductor device, and particularly to a resin-sealed semiconductor device. Semiconductor devices are now being used more and more in various fields, and in this case, it is possible to prevent the stress from concentrating locally on the cover film, thereby preventing the cover film from being destroyed, and providing high reliability. Robust semiconductor devices are required.
〔従来の技術〕 。[Conventional technology].
第２図は従来の半導体装置の一例の断面図を示す。同図
中、１はＡ２配線パターンでＰＳＧ等のカバー膜（絶縁
膜）２にてカバーされており、その表面を樹脂層３で封
止されている。４はＰＳＧ等の＠間絶縁枳である。FIG. 2 shows a cross-sectional view of an example of a conventional semiconductor device. In the figure, 1 is an A2 wiring pattern covered with a cover film (insulating film) 2 such as PSG, and its surface is sealed with a resin layer 3. 4 is an @ insulation layer such as PSG.
このように、半導体素子を樹脂封止すると、樹脂と半導
体チップとの熱膨張率の違いによって樹脂層３の応力（
矢印イ）及びカバー膜２の応力（矢印口）を生じ、両者
は常に応力を及ぼし合い、これにより、カバー膜２は矢
印凸方向の応力を受けて破壊される。樹脂層３の応力は
元々その内部に一様かつ等方向に分布しているが、配線
パターン１による半導体チップ表面の凹凸形状によって
応力が局所に集中し、破壊され易くなる。In this way, when a semiconductor element is encapsulated with resin, the stress in the resin layer 3 (
This generates stress in the cover film 2 (arrow a) and stress in the cover film 2 (indicated by the arrow), and the two constantly exert stress on each other. As a result, the cover film 2 receives stress in the convex direction of the arrow and is destroyed. Although the stress in the resin layer 3 is originally distributed uniformly and in the same direction within the resin layer 3, the stress is locally concentrated due to the uneven shape of the semiconductor chip surface due to the wiring pattern 1, making it easy to break.
この場合、第３図（Ａ＞に示すようにＡ８配線パターン
１′の断面形状がいわゆる一般の台形状であれば、カバ
ー膜２の矢印二方向の応力は台形斜面上に渡って分散さ
れるので応力が局所に集中するのが緩和される。然るに
、上記断面形状が艮方形状或いは第３図（Ｂ）に示すよ
うにいわゆる逆台形状であるとカバー膜２の矢印口方向
の応力は互いに逃げる所がなく、局所に集中し易く、Ａ
２配線パターン１“と絶縁膜４とのなす角が鋭角に近い
程この傾向が強い。In this case, if the cross-sectional shape of the A8 wiring pattern 1' is a so-called general trapezoidal shape as shown in FIG. Therefore, local concentration of stress is alleviated. However, if the cross-sectional shape is a rectangular shape or a so-called inverted trapezoid shape as shown in FIG. 3(B), the stress in the direction of the arrow in the cover film 2 is There is no escape from each other and it is easy to concentrate locally, A.
This tendency is stronger as the angle between the two wiring patterns 1'' and the insulating film 4 approaches an acute angle.
上記従来装置は、カバー膜２が破壊される現象に対して
何ら対策を施していないので、更に、下部構造にまで破
壊が及ぶ虞れがあり、信頼性に欠ける問題点があった。Since the above-mentioned conventional device does not take any measures against the phenomenon that the cover film 2 is destroyed, there is also a risk that the lower structure will be destroyed, resulting in a problem of lack of reliability.
第１図中、１はＡ２配線パターン、１ａはＡＩｌ配線パ
ターン１のエツジ、５は層間絶縁膜５ａは層間絶縁膜５
の弧状部、６はカバー膜、６ａはカバー膜６の弧状部、
７は樹脂層である。層間絶縁膜５の配線パターン１のエ
ッジ１ａ対向部分近傍に、エツジ１ａから連続して弧状
をなして層間絶縁膜５の表面に至る弧状部５ａを形成し
てなる。In FIG. 1, 1 is the A2 wiring pattern, 1a is the edge of the AIl wiring pattern 1, 5 is the interlayer insulating film 5a is the interlayer insulating film 5
6 is a cover film, 6a is an arc-shaped part of the cover film 6,
7 is a resin layer. In the vicinity of the portion of the interlayer insulating film 5 that faces the edge 1a of the wiring pattern 1, an arc-shaped portion 5a is formed that extends continuously from the edge 1a to the surface of the interlayer insulating film 5.
層間絶縁膜５に弧状部５ａが設けられているため、カバ
ー膜６の応力は矢印二のように弧状部５ａに沿って逃げ
、この部分に応力が集中することはない。Since the interlayer insulating film 5 is provided with the arcuate portion 5a, stress in the cover film 6 escapes along the arcuate portion 5a as shown by arrow 2, and stress is not concentrated in this portion.
第１図は本発明装置の一実施例の断面図を示し、同図中
、第２図と同一構成部分には同一番号を付す。同図中、
５はＰＳＧ等の層間絶縁膜、６はＰＳＧ等のカバー膜（
絶縁膜）、７は樹脂層である。FIG. 1 shows a sectional view of one embodiment of the apparatus of the present invention, and in the figure, the same components as in FIG. 2 are given the same numbers. In the same figure,
5 is an interlayer insulating film such as PSG, 6 is a cover film such as PSG (
7 is a resin layer.
層間絶縁膜５を形成した後、Ａ２配線パターン１のエツ
チングを過剰に行なうと、層間絶縁ＦＪ５のＡ２配線パ
ターン１のエッジ１ａ対向部分付近に、エツジ１ａから
連続して弧状をなして居間絶縁膜５表面に至る弧状部５
ａが形成されることが確認される。この弧状部５ａに沿
ってカバーＩＩ ６及び樹脂層７が形成されるので、カ
バー膜６の弧状部５ａ対向部分には弧状部６ａが形成さ
れ、これと同様に樹脂層７にも弧状部７ａが形成される
。If the A2 wiring pattern 1 is excessively etched after forming the interlayer insulating film 5, the living room insulating film will form an arc shape continuously from the edge 1a near the portion of the interlayer insulating FJ5 opposite the edge 1a of the A2 wiring pattern 1. 5 Arcuate portion 5 reaching the surface
It is confirmed that a is formed. Since the cover II 6 and the resin layer 7 are formed along this arcuate portion 5a, an arcuate portion 6a is formed in the portion of the cover film 6 that faces the arcuate portion 5a, and similarly, the resin layer 7 also has an arcuate portion 7a. is formed.
このようにカバー膜６に弧状部６ａが形成されるとカバ
ー膜６の応力は矢印二のように弧状部６ａに沿って逃げ
合うことになり、又、樹脂層７に弧状部７ａが形成され
ると樹脂層７の応力は矢印ホのように弧状部７ａに沿っ
て逃げることになり、これらの部分に夫々応力が集中す
ることばなくなる。即ち、第２図において、Ａ２配線パ
ターン１が前述のようにいわゆる一般の台形状に形成さ
れているのと略同じ効果を得ることができる。When the arcuate portion 6a is formed in the cover film 6 in this way, the stress in the cover film 6 escapes along the arcuate portion 6a as shown by arrow 2, and the arcuate portion 7a is formed in the resin layer 7. Then, the stress in the resin layer 7 escapes along the arcuate portion 7a as shown by the arrow E, and the stress is no longer concentrated on these portions. That is, in FIG. 2, substantially the same effect can be obtained as when the A2 wiring pattern 1 is formed in the so-called general trapezoidal shape as described above.
本発明によれば、カバー膜の応力及び樹脂層の応力は局
所に集中することはなくなり、これにより、カバー膜の
破壊を未然に防止し得、信頼性を向上し得る等の特長を
有する。According to the present invention, the stress in the cover film and the stress in the resin layer are no longer locally concentrated, thereby preventing damage to the cover film and improving reliability.
第１図は本発明装置の一実施例の断面図、第２図は従来
装置の一例の断面図、
第３図は応力の方向を説明する図である。
第１図において、
１はＡＩｌ配線パターン、
１ａはＡ２配線パターン１のエツジ、
５は層間絶縁膜、
５ａは居間絶縁膜５の弧状部、
６はカバー膜、
６ａはカバー膜６の弧状部、
７は樹脂層、
７ａは樹脂層７の弧状部である。
本１シ明禮手１≧も慢ピＬ
１ｍ
第２図
応力の方ゴ町【糖り咽する図
第３図FIG. 1 is a sectional view of an embodiment of the device of the present invention, FIG. 2 is a sectional view of an example of a conventional device, and FIG. 3 is a diagram illustrating the direction of stress. In FIG. 1, 1 is the AIl wiring pattern, 1a is the edge of the A2 wiring pattern 1, 5 is the interlayer insulating film, 5a is the arcuate part of the living room insulating film 5, 6 is the cover film, 6a is the arcuate part of the cover film 6, 7 is a resin layer, and 7a is an arc-shaped portion of the resin layer 7. Book 1 Shi Akari Te 1 ≧ Arrogant Pi L 1m Figure 2 Stress Direction [Figure 3
Claims (1)
該配線パターン（１）の表面にカバー膜（６）を施した
半導体装置において、 上記層間絶縁膜（５）の上記配線パターン（１）のエッ
ジ（１ａ）対向部分近傍に、該エッジ（１ａ）から連続
して弧状をなして上記層間絶縁膜（５）の表面に至る弧
状部（５ａ）を形成してなることを特徴とする半導体装
置。[Claims] A wiring pattern (1) is provided on the surface of an interlayer insulating film (5),
In a semiconductor device in which a cover film (6) is provided on the surface of the wiring pattern (1), the edge (1a) is provided near a portion of the interlayer insulating film (5) facing the edge (1a) of the wiring pattern (1). A semiconductor device characterized in that an arc-shaped portion (5a) is formed continuously from the top to the surface of the interlayer insulating film (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15293586A JPS639125A (en) | 1986-06-30 | 1986-06-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15293586A JPS639125A (en) | 1986-06-30 | 1986-06-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639125A true JPS639125A (en) | 1988-01-14 |
Family
ID=15551360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15293586A Pending JPS639125A (en) | 1986-06-30 | 1986-06-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639125A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5959830A (en) * | 1996-07-30 | 1999-09-28 | Nec Corporation | Electric double layer capacitor |
-
1986
- 1986-06-30 JP JP15293586A patent/JPS639125A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5959830A (en) * | 1996-07-30 | 1999-09-28 | Nec Corporation | Electric double layer capacitor |
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