JPS6388835A - Package for flip chip - Google Patents
Package for flip chipInfo
- Publication number
- JPS6388835A JPS6388835A JP23502386A JP23502386A JPS6388835A JP S6388835 A JPS6388835 A JP S6388835A JP 23502386 A JP23502386 A JP 23502386A JP 23502386 A JP23502386 A JP 23502386A JP S6388835 A JPS6388835 A JP S6388835A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor chip
- chip
- bumps
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 238000002844 melting Methods 0.000 claims abstract description 10
- 230000008018 melting Effects 0.000 claims abstract description 10
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 abstract description 10
- 238000003825 pressing Methods 0.000 abstract description 2
- 230000006866 deterioration Effects 0.000 abstract 1
- 229920001721 polyimide Polymers 0.000 description 7
- 239000009719 polyimide resin Substances 0.000 description 7
- 239000010949 copper Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- FGRBYDKOBBBPOI-UHFFFAOYSA-N 10,10-dioxo-2-[4-(N-phenylanilino)phenyl]thioxanthen-9-one Chemical compound O=C1c2ccccc2S(=O)(=O)c2ccc(cc12)-c1ccc(cc1)N(c1ccccc1)c1ccccc1 FGRBYDKOBBBPOI-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
集積回路が形成された半導体チップを、他の回路と組み
合わせてシステム化する工程において、接続のための加
熱により集積回路の特性が劣化する問題を解決するため
に、絶縁層の開口部に形成された低融点、軟金属よりな
る突起を有するフリップチップ用パッケージを提起し、
接続のための加熱過程をなくして、完全な電気的接続を
得るようにした。[Detailed Description of the Invention] [Summary] To solve the problem that the characteristics of the integrated circuit deteriorate due to heating for connection in the process of combining a semiconductor chip on which an integrated circuit is formed with other circuits to form a system. proposed a flip chip package having a protrusion made of a low melting point soft metal formed in an opening of an insulating layer,
A complete electrical connection is obtained by eliminating the heating process for connection.
本発明は半導体チップを接続する際に集積回路の特性を
劣化させないフリップチップ用パッケージの構造に関す
る。The present invention relates to a structure of a flip-chip package that does not deteriorate the characteristics of an integrated circuit when connecting semiconductor chips.
集積回路が形成された半導体チップを、他の回路と組み
合わせるためのパンケージは種々あるが、その内、チッ
プ表面の接続端子とパッケージ上の配線とを向かい合わ
せて接続するフリップチップ用パッケージは電気信号の
伝達性に優れているため、高速集積回路用のパッケージ
として使用されることが多くなってきた。There are various types of pancases for combining a semiconductor chip with an integrated circuit formed thereon with other circuits. Among them, flip-chip packages, which connect the connection terminals on the surface of the chip and the wiring on the package facing each other, are used to connect electrical signals. Because of their excellent transferability, they are increasingly being used as packages for high-speed integrated circuits.
・そのため、多様の機能、および特性をもつ半導体チッ
プの性能を劣化させることなく、確実に接続できるフリ
ップチップ用パッケージの実現が望まれる。-Therefore, it is desired to realize a flip-chip package that can be reliably connected without deteriorating the performance of semiconductor chips with various functions and characteristics.
第３図は従来のフリップチップ用パッケージの断面図で
ある。FIG. 3 is a sectional view of a conventional flip chip package.
図において、アルミナ等よりなるセラミック基板１３の
上に、配線上４を形成する。In the figure, a wiring top 4 is formed on a ceramic substrate 13 made of alumina or the like.
つぎに、チップの接続端子位置に対応した位置の配線１
４上に直接、不定形の半田バンプ１５を形成する。Next, wire 1 at the position corresponding to the connection terminal position of the chip.
4, an irregularly shaped solder bump 15 is formed directly on the solder bump 4.
以上の構造のパッケージと半導体デツプとの接続は、こ
のパッケージの上に大体の位置合わせをして半導体チッ
プを載せて、加熱処理をして行われる。Connection between the package having the above structure and the semiconductor depth is achieved by placing the semiconductor chip on the package with rough alignment, and then subjecting it to heat treatment.
加熱処理により、半田バンプは溶融し、表面張力により
半導体チップ上の接続用金属端子と、パッケージ上の配
線金属とを接近させ、自動的に位置合わせがなされる。The solder bumps are melted by the heat treatment, and the connection metal terminals on the semiconductor chip and the wiring metal on the package are brought closer to each other due to surface tension, and alignment is automatically performed.
従来のフリップチップ用パッケージは、加熱による半田
バンプの溶融を用いた位置合わせ、および接続を行って
いるため、加熱による性能劣化が予想される半導体チッ
プには適用できないという問題があった。Conventional flip-chip packages use melting of solder bumps by heating for alignment and connection, so there is a problem that they cannot be applied to semiconductor chips whose performance is expected to deteriorate due to heating.
〔問題点を解決するための手段〕
上記問題点の解決は、集積回路が形成された半導体チッ
プの接続端子位置に対応して配置された導電性の突起と
、該突起に電気的に接続された配線とを有する基板より
なり、
該突起が、該配線上に被着された絶縁層に形成された開
口部内に半田より低融点で、かつ軟らかい金属で形成さ
れ、
該開口部の容積が該突起の体積より小さいことを特徴と
するフリップチップ用パッケージにより達成される。[Means for solving the problem] The solution to the above problem is to provide conductive protrusions arranged corresponding to the connection terminal positions of a semiconductor chip on which an integrated circuit is formed, and electrically connected to the protrusions. The protrusion is formed of a soft metal with a lower melting point than solder in an opening formed in an insulating layer deposited on the wiring, and the volume of the opening is This is achieved by a flip-chip package that is characterized by being smaller than the volume of the protrusion.
本発明のパンケージは絶縁層に開けられた開口部の寸法
で決められた形状をもつ低融点、軟金属のバンプを有す
るため、半導体チップの端子配列に適応したバンプ形成
が容易であり、また、パッケージと半導体チップの接続
は低融点、軟金属のバンプを介して加圧して行うため、
加熱処理を必要としないで行うことができる。Since the pan cage of the present invention has bumps made of a low melting point, soft metal whose shape is determined by the dimensions of the openings made in the insulating layer, it is easy to form bumps that are compatible with the terminal arrangement of the semiconductor chip. The package and semiconductor chip are connected by applying pressure through low melting point, soft metal bumps.
It can be carried out without the need for heat treatment.
第１図（１）、（２）は本発明のフリップチップ用パッ
ケージの断面図と平面図である。FIGS. 1(1) and 1(2) are a sectional view and a plan view of a flip-chip package of the present invention.
図において、アルミナ等よりなるセラミック基板１の上
に、金（Ａｕ）、または銅（Ｃｏ）よりなる接地用配線
２を形成する。In the figure, a ground wiring 2 made of gold (Au) or copper (Co) is formed on a ceramic substrate 1 made of alumina or the like.
接地用配線２の上に絶縁層としてポリイミド樹脂層３を
被着し、この上に通常のりソグラフィによるパターニン
グを用いて、Ｃｕよりなる信号用の配線４を形成する。A polyimide resin layer 3 is deposited as an insulating layer on the ground wiring 2, and a signal wiring 4 made of Cu is formed thereon by patterning using ordinary lamination lithography.
配線４を覆ってポリイミド樹脂層５を被着し、半導体チ
ップの接続端子位置に対応した位置の配線４上に接続用
の開口部を形成する。A polyimide resin layer 5 is applied to cover the wiring 4, and a connection opening is formed on the wiring 4 at a position corresponding to the connection terminal position of the semiconductor chip.
ポリイミド樹脂層５の厚さが不足の場合はさらに、位置
決め用絶縁層としてポリイミド樹脂層６を開口部の周囲
に堤状に形成する。If the thickness of the polyimide resin layer 5 is insufficient, a polyimide resin layer 6 is further formed in the shape of a bank around the opening as a positioning insulating layer.
開口部内に半田より低融点で、かつ軟らかい金属として
、例えばインジウム（Ｉｎ）バンプ７を挿入し、圧接す
る。An indium (In) bump 7, which is a metal having a lower melting point than solder and is softer than solder, for example, is inserted into the opening and pressure-bonded.
以上の構造のパンケージと半導体チップとの接続方法の
例を第２図により説明する。An example of a method of connecting the pancage with the above structure and a semiconductor chip will be explained with reference to FIG. 2.
第２図は本発明のパンケージと半導体チップとの接続方
法を説明する断面図である。FIG. 2 is a sectional view illustrating a method of connecting a pan cage and a semiconductor chip according to the present invention.
図において、台８」二に本発明のパッケージ９を置き、
位置合わせ治具ｌＯをパッケージ９の上に被せ、半導体
チップ１１と、チップ押さえ治具１２を順次パッケージ
９の上に載せる。。In the figure, the package 9 of the present invention is placed on the stand 8'',
A positioning jig 10 is placed over the package 9, and a semiconductor chip 11 and a chip holding jig 12 are placed on the package 9 one after another. .
位置合わせ治具１０には半導体チップ１１の外形寸法に
合わせた孔が開けてあり、パッケージ９に半導体チップ
１１を対向させて、チップ押さえ治具１２により圧力を
かけてＩｎバンプ７を介して両者を接着する。The positioning jig 10 has a hole that matches the external dimensions of the semiconductor chip 11, and the semiconductor chip 11 is placed facing the package 9, and pressure is applied by the chip holding jig 12 to hold the semiconductor chip 11 between the two via the In bumps 7. Glue.
この際、Ｉｎハンプ７は変形するが、位置決め用絶縁層
６によって、変形する範囲を決められているため、隣接
端子と接触することはない。At this time, the In hump 7 is deformed, but since the range of deformation is determined by the positioning insulating layer 6, it does not come into contact with adjacent terminals.
〔発明の効果〕
以上詳細に説明したように本発明によれば、加熱処理を
することなくパッケージと半導体チップとの接続が可能
となり、このために熱によって性能劣化が予想されるジ
ョセフソン素子の集積回路等の半導体チップに対して高
信頬のパッケージが得られる。[Effects of the Invention] As explained in detail above, according to the present invention, it is possible to connect a package and a semiconductor chip without heat treatment, and this makes it possible to connect a Josephson element whose performance is expected to deteriorate due to heat. A highly reliable package can be obtained for semiconductor chips such as integrated circuits.
第１図（１１、（２）は本発明のフリップチップ用パン
ケージの断面図と平面図、
第２図は本発明のパッケージと半導体チップとの接続方
法を説明する断面図、
第３図は従来のフリップチップ用パンケージの断面図で
ある。
図において、
１はセラミック基板、
２はＡｕ 、またはＣｕよりなる接地用配線、３は絶縁
層でポリイミド樹脂層、
４はＣｕよりなる信号用配線、
５は絶縁層でポリイミド樹脂層、
６は位置決め用絶縁層でポリイミド樹脂層、７は低融点
、軟金属バンプでＩｎバンプ、８は台、
９は本発明のパッケージ、
１０は位置合わせ治具、
１１は半導体チップ、
１２はチップ押さえ治具
Ｖ東伺ｎ断Ｃ
，％３
９図
囲Fig. 1 (11, (2)) is a sectional view and a plan view of a flip chip pan cage of the present invention, Fig. 2 is a sectional view illustrating a method of connecting a package of the present invention and a semiconductor chip, and Fig. 3 is a conventional 1 is a cross-sectional view of a flip-chip pancage. In the figure, 1 is a ceramic substrate, 2 is a ground wiring made of Au or Cu, 3 is an insulating layer made of a polyimide resin layer, 4 is a signal wiring made of Cu, 5 6 is an insulating layer and is a polyimide resin layer; 6 is a positioning insulating layer and is a polyimide resin layer; 7 is a low melting point, soft metal bump that is an In bump; 8 is a stand; 9 is a package of the present invention; 10 is a positioning jig; 11 12 is a semiconductor chip, 12 is a chip holding jig,
Claims (1)
応して配置された導電性の突起と、該突起に電気的に接
続された配線とを有する基板よりなり、 該突起が、該配線上に被着された絶縁層に形成された開
口部内に、半田より低融点で、かつ軟らかい金属で形成
され、 該開口部の容積が該突起の体積より小さい ことを特徴とするフリップチップ用パッケージ。[Scope of Claims] A substrate comprising a conductive protrusion arranged corresponding to the connection terminal position of a semiconductor chip on which an integrated circuit is formed, and wiring electrically connected to the protrusion, the protrusion is formed of a softer metal with a lower melting point than solder in an opening formed in an insulating layer deposited on the wiring, and the volume of the opening is smaller than the volume of the protrusion. Package for flip chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23502386A JPS6388835A (en) | 1986-10-02 | 1986-10-02 | Package for flip chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23502386A JPS6388835A (en) | 1986-10-02 | 1986-10-02 | Package for flip chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6388835A true JPS6388835A (en) | 1988-04-19 |
Family
ID=16979933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23502386A Pending JPS6388835A (en) | 1986-10-02 | 1986-10-02 | Package for flip chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6388835A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03257899A (en) * | 1990-03-07 | 1991-11-18 | Mitsubishi Electric Corp | Positioning of semiconductor device |
-
1986
- 1986-10-02 JP JP23502386A patent/JPS6388835A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03257899A (en) * | 1990-03-07 | 1991-11-18 | Mitsubishi Electric Corp | Positioning of semiconductor device |
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