JPS6384131A - Device for inspecting semiconductor device - Google Patents
Device for inspecting semiconductor deviceInfo
- Publication number
- JPS6384131A JPS6384131A JP61230388A JP23038886A JPS6384131A JP S6384131 A JPS6384131 A JP S6384131A JP 61230388 A JP61230388 A JP 61230388A JP 23038886 A JP23038886 A JP 23038886A JP S6384131 A JPS6384131 A JP S6384131A
- Authority
- JP
- Japan
- Prior art keywords
- probe
- relay
- semiconductor chip
- electrode
- measured
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000523 sample Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims description 10
- 239000012212 insulator Substances 0.000 claims description 5
- 238000005259 measurement Methods 0.000 abstract description 7
- 230000006698 induction Effects 0.000 abstract 1
- 238000012360 testing method Methods 0.000 description 12
- 238000007689 inspection Methods 0.000 description 9
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
- Measuring Leads Or Probes (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置のプローブ検査工程で用いられる
検査装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an inspection device used in a probe inspection process for semiconductor devices.
従来の技術
半導体装置のプローブ検査では、被測定半導体チップ上
の電極と検査装置との間を接続するためのプローブ(探
針)が取り付けられたプローブカードと称される検査装
置が用いられる。第2図は上記プローブカードの一例を
示す構造図である。2. Description of the Related Art In probe testing of semiconductor devices, a testing device called a probe card is used, which is equipped with a probe for connecting an electrode on a semiconductor chip to be measured and the testing device. FIG. 2 is a structural diagram showing an example of the probe card.
第2図において、1は絶縁体製基板(以下プローブカー
ド本体と呼ぶ)、2はプローブカード本体1の裏面に突
出して取り付けられたプローブ、3はプローブカード本
体1の一端に形成された複数の電気的端子、4は上記プ
ローブ2と上記電気的端子3を接続する配線層、5は被
測定半導体チップ、6は被測定半導体チップ5の表面に
設けられた電極、7は電極6とプローブ2が正しく接触
しているか否かを確認するための窓である。In FIG. 2, 1 is an insulator substrate (hereinafter referred to as the probe card body), 2 is a probe attached to the back surface of the probe card body 1, and 3 is a plurality of probes formed at one end of the probe card body 1. An electrical terminal; 4 is a wiring layer connecting the probe 2 and the electrical terminal 3; 5 is a semiconductor chip to be measured; 6 is an electrode provided on the surface of the semiconductor chip 5 to be measured; 7 is an electrode 6 and the probe 2; This window is used to confirm whether or not the contact is correct.
上記プローブカードはその電気的端子3につながる接続
手段を介してプローブ検査用テスターに接続されて測定
システムが構成される。この測定システム全体の構成を
第3図に示す。第3図において、8は上記のように構成
されたプローブカード、9はプローブ検査用テスター、
10はプローブカード8とプローブ検査用テスター9を
接続するための接続手段であるリード線、11はプロー
ブ検査用テスター9の内部にある各種の電源、電圧計、
電流計等のモジュール、12はモジュール11とリード
線10の電気的接続及び開放を行なうリレー等のスイッ
チ手段である。The probe card is connected to a probe testing tester via a connecting means connected to the electrical terminal 3 of the probe card, thereby configuring a measurement system. The overall configuration of this measurement system is shown in FIG. In FIG. 3, 8 is a probe card configured as described above, 9 is a tester for probe inspection,
10 is a lead wire which is a connection means for connecting the probe card 8 and the probe tester 9; 11 is various power supplies and voltmeters inside the probe tester 9;
A module such as an ammeter, and reference numeral 12 are switching means such as a relay for electrically connecting and disconnecting the module 11 and the lead wire 10.
以上のように構成されたプローブ検査測定システムに、
検査時の動作について以下に説明する。In the probe inspection measurement system configured as above,
The operation during inspection will be explained below.
例えば、被測定半導体チップ5上の電極6aと6bの間
に一定の電圧を印加した際に流れる電流を測定しようと
するとその動作は以下のようになる。For example, when trying to measure the current flowing when a constant voltage is applied between the electrodes 6a and 6b on the semiconductor chip 5 to be measured, the operation is as follows.
上記モジュール11の構成要素である電圧源111と電
流計112が第3図に示すように直列に接続される。次
にリレー12の接点12aと12bが閉じられ電圧源1
11の電圧はこれらの接点につながるリード線10aと
10b、さらにリード線10aと10bが各々接続され
たプローブカード8の電気的端子3aと3bを介してプ
ローブカード8に入力される。このようにして入力され
た電圧は、さらに、第2図で示しだプローブカードの配
線層4aと4bおよびプローブ2aと2bを通じて被測
定半導体チップの電極6とと6bに印加される。このよ
うにして形成された回路に電流が流れ、この電流が電流
計112により測定される。A voltage source 111 and an ammeter 112, which are components of the module 11, are connected in series as shown in FIG. Contacts 12a and 12b of relay 12 are then closed and voltage source 1
11 is input to the probe card 8 through lead wires 10a and 10b connected to these contacts, and electrical terminals 3a and 3b of the probe card 8 to which the lead wires 10a and 10b are connected, respectively. The voltage thus input is further applied to the electrodes 6 and 6b of the semiconductor chip to be measured through the wiring layers 4a and 4b of the probe card and the probes 2a and 2b shown in FIG. A current flows through the circuit thus formed, and this current is measured by an ammeter 112.
発明が解決しようとする問題点
上記のようなプローブ検査測定システムの構成では、半
導体被測定チップ6とプローブ検査用テスター9の電気
的接続及び開放はテスター内部のリレー12によシ行な
われる。このだめ、リレー12が開放の場合でも、長い
リード線10が被測定半導体チップ5に接続されたまま
となり、リード線10が接続されている被測定半導体チ
ップ上の電極6に誘導ノイズが印加されやすくなる。さ
らに、リード線1oの分布容量も電極6に付加されると
ころとなる。したがって、被測定半導体チップ5の電気
特性の正確な測定が困難となる問題点があった。Problems to be Solved by the Invention In the configuration of the probe inspection and measurement system as described above, the electrical connection and disconnection between the semiconductor chip 6 to be measured and the probe inspection tester 9 is performed by a relay 12 inside the tester. In this case, even if the relay 12 is open, the long lead wire 10 remains connected to the semiconductor chip under test 5, and inductive noise is applied to the electrode 6 on the semiconductor chip under test to which the lead wire 10 is connected. It becomes easier. Furthermore, the distributed capacitance of the lead wire 1o is also added to the electrode 6. Therefore, there is a problem in that it is difficult to accurately measure the electrical characteristics of the semiconductor chip 5 to be measured.
問題点を解決するための手段
本発明は上記の問題点を解決するためになされたもので
、プローブ検査用の複数のプローブと、これらのプロー
ブが取り付けられた絶縁体製の基板と、この基板上に設
けられた複数の電気的端子と、前記基板上に形成され、
前記複数のプローブと複数の電気的端子を接続する配線
層とを備えるとともに、前記基板上に被測定半導体チッ
プとプローブ検査用テスターの電気的接続及び開放を行
なうだめのスイッチ手段を配置したものである。Means for Solving the Problems The present invention has been made to solve the above problems, and includes a plurality of probes for probe testing, a substrate made of an insulator to which these probes are attached, and this substrate. a plurality of electrical terminals provided on the substrate;
It comprises a wiring layer for connecting the plurality of probes and a plurality of electrical terminals, and a switch means for electrically connecting and disconnecting the semiconductor chip to be measured and the probe testing tester on the substrate. be.
作 用
この構成によればスイッチ手段が開放の場合、被測定半
導体チップ上の電極にはこのスイッチ手段とプローブと
の間の配線層部分とプローブのみが繋るところとなり、
電極に繋る導体の長さは従来に比べてかなシ短かくなる
。According to this configuration, when the switch means is open, only the wiring layer portion between the switch means and the probe and the probe are connected to the electrode on the semiconductor chip to be measured.
The length of the conductor connected to the electrode is much shorter than before.
実施例
第1図は、本発明にかかる半導体装置用検査装置の一実
施例を示す構造図である。第1図において、13はプロ
ーブカード本体1の上に配置されたリレー、14.15
はリレー13の制御用電気的端子、16はリレー13と
電気的端子14および16との間を接続するだめの配線
層である。なお、番号1〜7を付与して示した要素は第
2図で同一番号を付与した要素と同じものである。Embodiment FIG. 1 is a structural diagram showing an embodiment of a semiconductor device inspection apparatus according to the present invention. In FIG. 1, 13 is a relay placed on the probe card body 1, 14.15
1 is an electrical terminal for controlling the relay 13, and 16 is a wiring layer for connecting the relay 13 and the electrical terminals 14 and 16. Note that the elements numbered 1 to 7 are the same as the elements numbered the same in FIG.
以上のように構成された本発明の半導体装置用検査装置
について以下に説明する。例えば、被測定半導体チップ
5の電極の中で、電極6cが高い電圧利得を持つ増幅器
の入力端子となっており、従って、誘導ノイズの影響を
できるだけ低減するために電極6cに付加するリード線
等の導体の長さを極力短かくする必要があるときには、
図示すルヨうに電極6cに接触しているプローブ2cと
電気的端子3cの間にリレー13を設置し、このリレー
13を制御用電気的端子14と15の間に一定の電圧を
印加して開放状態にすることで目的が達成される。すな
わち、リレー13の開放で電気的端子3cとプローブ検
査用テスターとの間に接続されている通常数メートルの
長さを持つリード線が電極6cから切シ離される。した
がって、誘導ノイズによる悪影響を除くことが可能とな
る。The semiconductor device inspection apparatus of the present invention configured as described above will be described below. For example, among the electrodes of the semiconductor chip 5 to be measured, the electrode 6c is the input terminal of an amplifier with a high voltage gain, and therefore a lead wire etc. is added to the electrode 6c in order to reduce the influence of induced noise as much as possible. When it is necessary to make the length of the conductor as short as possible,
As shown in the figure, a relay 13 is installed between the probe 2c in contact with the electrode 6c and the electrical terminal 3c, and the relay 13 is opened by applying a constant voltage between the control electrical terminals 14 and 15. The purpose is achieved by achieving the state. That is, when the relay 13 is opened, the lead wire, which is usually several meters long and is connected between the electrical terminal 3c and the probe tester, is separated from the electrode 6c. Therefore, it is possible to eliminate the adverse effects of induced noise.
なお、被測定半導体チップ5の品種が異なれば、それに
応じて、付加されるリード線等の導体の長さを極力短く
しなければならない電極も変化するが、被測定半導体チ
ップ5の品種に対応させて、リレー16の取付位置を設
定したプローブ力−ド本体1を準備すればよい。Note that if the type of semiconductor chip 5 to be measured differs, the electrodes to which the length of conductors such as lead wires to be added must be kept as short as possible will also change, but the length of the conductor such as an attached lead wire must be kept as short as possible. Then, the probe power cord body 1 in which the mounting position of the relay 16 is set is prepared.
また、上記の実施例ではスイッチ手段としてリレーを用
いだが、リレー以外のものを用いてもよいことはいうま
でもない。Further, although a relay is used as the switch means in the above embodiment, it goes without saying that something other than a relay may be used.
発明の効果
以上述べてきたように、本発明によれば、プローブカー
ド上に設置したスイッチ手段によシ、所定の導体を被測
定半導体チップから電気的に切シ離すことができ、誘導
ノイズの印加あるいは分布等
容量の付加勤;排除され、これらによる測定への悪影響
が排除される。したがって、被測定半導体チップの安定
な測定が実現できる。Effects of the Invention As described above, according to the present invention, a predetermined conductor can be electrically disconnected from a semiconductor chip under test by means of a switch installed on a probe card, thereby reducing induced noise. Addition of applied or distributed isocapacitance is eliminated; their negative influence on the measurement is eliminated. Therefore, stable measurement of the semiconductor chip to be measured can be achieved.
第1図は本発明の一実施例にかかる半導体装置用検査装
置を示す構造図、第2図は従来の半導体装置用検査装置
の一例を示す構造図、第3図はプローブ検査システムの
構成図である。
1・・・・・・絶縁体製基板、2・・・・・・プローブ
、3・・・・・・電気的端子、4・−・−・・導線、5
・・・・・被測定半導体チップ、6・・・・電極、7・
・・・・・窓、13・・・・・・リレー(スイッチ手段
)、14.15・・・・・リレーの制御用電気的端子、
16・・・・・・導線。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名7−
−−絶縁体製基板
2− ブローク(裸炉)
3− 電気的端子
4−配線層
5−被測定半導体チヅプ
−1Ja
7− 剋
第 1 図 13− リレー(ス
チナ7千手欺)ta、ts−−リレーの制御用端子
tb−−配線層
@2図FIG. 1 is a structural diagram showing a semiconductor device testing device according to an embodiment of the present invention, FIG. 2 is a structural diagram showing an example of a conventional semiconductor device testing device, and FIG. 3 is a configuration diagram of a probe testing system. It is. DESCRIPTION OF SYMBOLS 1...Insulator substrate, 2...Probe, 3...Electrical terminal, 4--Conductor wire, 5
... Semiconductor chip to be measured, 6... Electrode, 7.
... window, 13 ... relay (switch means), 14.15 ... electrical terminal for controlling relay,
16... Conductor. Name of agent: Patent attorney Toshio Nakao and 1 other person7-
--Insulator substrate 2- Broke (bare furnace) 3-Electrical terminal 4-Wiring layer 5-Semiconductor chip to be measured-1Ja 7-Relay 1 Figure 13-Relay (Stina 7,000-handed deception) ta, ts- -Relay control terminal tb--Wiring layer @2 diagram
Claims (1)
ブと、同複数のプローブが取り付けられた絶縁体製の基
板と、同基板上に設けられた複数の電気的端子を備える
とともに、前記複数のプローブと複数の電気的端子のそ
れぞれから選定した所定のプローブと電気的端子とを前
記基板上に配設した配線層とスイッチ手段を介して接続
したことを特徴とする半導体装置用検査装置。A plurality of probes to be brought into contact with electrodes on a semiconductor chip to be measured, a substrate made of an insulator to which the plurality of probes are attached, and a plurality of electrical terminals provided on the substrate, and the plurality of probes. and a predetermined probe selected from each of the plurality of electrical terminals and the electrical terminal are connected to a wiring layer provided on the substrate via a switch means.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61230388A JPH0827298B2 (en) | 1986-09-29 | 1986-09-29 | Inspection device for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61230388A JPH0827298B2 (en) | 1986-09-29 | 1986-09-29 | Inspection device for semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6384131A true JPS6384131A (en) | 1988-04-14 |
JPH0827298B2 JPH0827298B2 (en) | 1996-03-21 |
Family
ID=16907092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61230388A Expired - Lifetime JPH0827298B2 (en) | 1986-09-29 | 1986-09-29 | Inspection device for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0827298B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6148380U (en) * | 1984-09-04 | 1986-04-01 |
-
1986
- 1986-09-29 JP JP61230388A patent/JPH0827298B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6148380U (en) * | 1984-09-04 | 1986-04-01 |
Also Published As
Publication number | Publication date |
---|---|
JPH0827298B2 (en) | 1996-03-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |