JPS6384127A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6384127A
JPS6384127A JP61228211A JP22821186A JPS6384127A JP S6384127 A JPS6384127 A JP S6384127A JP 61228211 A JP61228211 A JP 61228211A JP 22821186 A JP22821186 A JP 22821186A JP S6384127 A JPS6384127 A JP S6384127A
Authority
JP
Japan
Prior art keywords
bump
alloy
electrode
bonded
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61228211A
Other languages
Japanese (ja)
Other versions
JPH0732170B2 (en
Inventor
Michihiko Inaba
道彦 稲葉
Isao Suzuki
功 鈴木
Nobuo Iwase
岩瀬 暢男
Kazuyoshi Saito
和敬 斎藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61228211A priority Critical patent/JPH0732170B2/en
Publication of JPS6384127A publication Critical patent/JPS6384127A/en
Publication of JPH0732170B2 publication Critical patent/JPH0732170B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a bump directly on an aluminum electrode without base metal with a whole bump or a surface layer formed of a metal which mainly contains at least two types of Zn, Cu, Sn or one type of them and at least one type of In, Bi and Cd. CONSTITUTION:Component elements for forming an eutectic crystal with aluminum or intermetallic compound by diffusing Zn, Sn or Cu in aluminum to form a reaction layer, and an alloy including In, Bi, Cd for reducing a hardness and easily plastically deforming by the mixture are used. This alloy film 2 is formed on the bump 11 of a taper 3, and bonded through the reaction layer 1 on an aluminum electrode 4 on a semiconductor chip 5. Or, the alloy 2 is bonded to the heat of the bump 11 provided with leads 20 adhered with an insulating tape, or the bump 7 is covered with the alloy 2, or the bump itself is formed of the alloy 2. According to this configuration, the bump of Zn, Sn, Cu which is impossible to be bonded due to high hardness can be softened to be easily bonded, and a device having high bonding reliability is obtained in response to a miniaturization.

Description

【発明の詳細な説明】 〔発明の目的1 (産業上の利用分野) へ 本発明はTAB(TepeAutomated Bon
ding)方式の半導体装置のパンダの改良に関する。
[Detailed Description of the Invention] [Objective of the Invention 1 (Industrial Application Field) The present invention is directed to a TAB (Tepe Automated Bonn).
ding) type semiconductor device.

(従来の技術) 半導体装置のボンディング技術はワイヤボンディング技
術と、ワイヤレスボンディング技術との2つに大別され
る。前者はワイヤで半導体チップの電極とリードフレー
ムのリード端子と21妾続す電極の寸法が100μm口
以下となり、かつ高密度となるにつれ、待に信頼性の点
で間頂が多くなる。
(Prior Art) Bonding technology for semiconductor devices is roughly divided into two types: wire bonding technology and wireless bonding technology. In the former case, the dimensions of the electrodes connected by wires to the electrodes of the semiconductor chip and the lead terminals of the lead frame are 100 μm or less, and as the density becomes higher, the number of gaps increases in terms of reliability.

これに対して、後者の方法は半導体チップの電極と、リ
ードフレームのリード端子又はガラス、セラミック基板
上の/lflとを一括してボンディングするものであり
、E子の高集積化に対応して信頼性を確保する之めに実
用化がなされている。
On the other hand, the latter method involves bonding the electrodes of the semiconductor chip and the lead terminals of the lead frame or /lfl on the glass or ceramic substrate all at once, and is compatible with the high integration of E elements. It has been put into practical use to ensure reliability.

このワイヤレスボンディング41.1’JTとしては1
例えばテープオートメイティッドボンディング方式(T
AB方式)、フリップテップ方式あるいはCCB方式な
どが知られており、これらの方式では通常半導体チップ
の電極上にパンダを形成する。
This wireless bonding 41.1'JT is 1
For example, tape automated bonding method (T
AB method), flip-step method, and CCB method are known, and in these methods, pandas are usually formed on the electrodes of the semiconductor chip.

このパンダとしては、従来から高価な金が検討されてい
る。
For this panda, expensive gold has been considered.

従来、半4体チップの!極上に形成される金からなるバ
ンプは%第6閣に示Tようなものである。
Conventionally, half 4 body chips! The bump made of gold formed on the top is like that shown in the 6th cabinet.

第5図に訃いて、シリコン基板31上には酸化シリコン
嗅等の絶縁膜322介してAI又はAj合金専からなる
電極33がパターニングされて形成され、全面に窒化シ
リコン’I11 %のパッジベージ藁ン膜34を被1し
た後、゛電極33上0パッシベーシッン膜34を選択的
にエツチングして電極33を露出させている。−茸出し
之電極33上にはCr。
As shown in FIG. 5, an electrode 33 made of AI or Aj alloy is formed by patterning on a silicon substrate 31 through an insulating film 322 such as silicon oxide, and a padding layer of 11% silicon nitride is formed on the entire surface. After covering the film 34, the passive basis film 34 on the electrode 33 is selectively etched to expose the electrode 33. - Cr on the mushroom removal electrode 33;

Ni、Mo*UusAu+Ag  等からなる下地金属
35が形成されている。更に、下地金属35上にに金バ
ンプ36が形成されている。
A base metal 35 made of Ni, Mo*UusAu+Ag, etc. is formed. Furthermore, gold bumps 36 are formed on the base metal 35.

前記′F地金@35ははんだとの接合性を改讐するため
に設けられる%、Oである。この自回・Oために下地金
@35としては1層〜3層の金@層が設けられ1種々の
組合せが@村されている。
The 'F base metal@35 is %O provided to improve bondability with solder. For this purpose, one to three gold layers are provided as the base metal layer 35, and various combinations are formed.

ところで、金バンプ36は通常めっき又は蒸着により形
成され、種々の方法が促案されているが、これらの方法
は臥下に述べるようにいずれも欠点がある。
Incidentally, the gold bumps 36 are usually formed by plating or vapor deposition, and various methods have been proposed, but all of these methods have drawbacks as described below.

めっきによる方法では1例えば電礪孔あけ工程が終了し
た後、v1極上の自然収化模を反応性イオンエツチング
により除去し、全面に1〜3.10下地金rA?蒸曙し
、電砥部が開孔しためっきレジストを被覆し、電極上の
下地金属上vC17)+はんだめっき2豆ない、めりき
レジスト及び下地金属の不要部分?エツチングするとい
り工程がとられる。
In the plating method, for example, after the electric drilling step is completed, the natural grains on the V1 layer are removed by reactive ion etching, and a base metal rA? After steaming, the abrasive part covers the plating resist with holes, and there is no need for vC17) + solder plating on the base metal on the electrode, unnecessary parts of the plated resist and base metal? Etching involves a drilling process.

この丸め工程が複雑になるという欠点がある。The drawback is that this rounding process is complicated.

また蒸着による方法では時間がかがり不都合である。Further, the method using vapor deposition is disadvantageous in that it is time consuming.

いずれにしても従来の方法では、下地金@2用い、しか
も′電極部以外り部分に今がめつきあるいはfA′yi
tされないようにマスク?形成しなければならない等、
工程の煩雑化につながる基本的な問題点がある。
In any case, in the conventional method, the base metal @2 is used, and the part other than the electrode part is not coated or fA'yi.
Mask so you don't get hit? must be formed, etc.
There are fundamental problems that lead to complicated processes.

これを鱗決丁ぺ(Zn会被被覆たバンプつきテープが考
案(′!#開昭55−103734 )があるが。
A tape with bumps coated with Zn was devised ('!#103734, 1972).

Zn被覆層が硬く塑性変形しにくいなめ妾合が元分行れ
ない。
The Zn coating layer is hard and difficult to plastically deform, so licking cannot be performed.

(発明が解決しよりとする問題点) 本発明は上記問題点?解消するためになされ九もつであ
ジ、’KIIL上に下地金属なしで直接パンブタ形成す
る%Dである。
(Problems to be solved by the invention) Does the invention solve the above problems? In order to solve this problem, there are nine methods that can be used to form a mold directly on the KIIL without an underlying metal.

【発明の構成コ (問題tf4決するための手段と作用)本発明はバンプ
全tJI−あるいは表面層がZn、Cu。
Structure of the Invention (Means and Actions for Solving Problem TF4) The present invention is characterized in that the entire bump or surface layer is made of Zn or Cu.

Snの中から選ばれた少なくとも2櫨の金1を主Ii!
、分とする金属体で構成されるかあ6いはZn。
Lord Ii with at least 2 gold 1 selected from Sn!
, or Zn.

Sn、Cuの第1成分群から選ばれた少なくとも一種と
In、BL、Cdの第2取分鮮から選ばれt少くとも一
種から構成された金属体であることを特徴とT6もので
ある。
The T6 material is characterized by being a metal body composed of at least one member selected from the first component group of Sn and Cu and at least one member selected from the second group of In, BL, and Cd.

本発明を原理的に説明すると吠態因に示される、謙に、
Zn、Sn 、Cut)様にAlと共晶あるいは金属間
化合′JjlJ?つくる成分元素がAI中に拡孜し反応
層2形成下る成分と、金属体の硬度e下げ容易に型性変
形する事3助えるIn、BI、Cdの喀2成分から金@
体が構成される事により、ZnだけあるいはCu、Sn
だけでできたバンプに比べ、Al¥!を極との反も層が
できやすくなる。次にバンプ接合部の断面を第1図2も
ちいて説明する。
To explain the present invention in principle, it is humbly explained by the barking cause.
Zn, Sn, Cut), eutectic or intermetallic combination with Al 'JjlJ? The constituent elements to be formed expand into AI to form a reaction layer 2, and the 2 constituents of In, BI, and Cd help to lower the hardness of the metal body and easily deform the mold.
Depending on the composition of the body, only Zn or Cu, Sn
Compared to the bump made only by Al¥! The pole and the opposite also make it easier to form a layer. Next, a cross section of the bump joint will be explained using FIG. 1 and FIG.

このバンプの構成は箒1図(a) K示す様にバンプつ
きテープ3のバンプ部110表面に本発明の合金被覆部
2がもうけられ半導本テップ5の上0Alシ!8M4v
c反芯層1に;り接合されてhるものである。
The configuration of this bump is as shown in Figure 1 (a) K, the alloy coating part 2 of the present invention is formed on the surface of the bump part 110 of the tape 3 with bumps, and the 0Al film is formed on the top of the semiconductor tape 5. 8M4v
It is bonded to the anti-core layer 1.

さらに第1図(b)では絶縁テープ6vC付着されたり
−ド20vCエツチングした穴31出しバンプ11を形
成して本発明の今萬本2を被覆したものである。また号
1図tc)はバンプ7表面に合金体23%。
Further, in FIG. 1(b), a bump 11 with holes 31 formed by adhering 6vC of insulating tape and etching 20vC of insulating tape is used to cover the present invention 2. In addition, Figure 1 tc) has 23% alloy on the bump 7 surface.

うけ九もので、第1図(d)はバンプ8全体が本発明の
合金t$になっている事を示している。
As a matter of fact, FIG. 1(d) shows that the entire bump 8 is made of the alloy of the present invention.

核金属本?もつける方法はめっき、蒸着、スパッタ、m
虫金嘴へのディップ専のいずれかの方法をとってもよい
。ま九Al電翫側にバンプ2形成する場合は、溶融金属
中あるいは電極側基板に超貨波をかけてバンプ3tてて
もよい。さらにはんだで通常を本成分となってhるpb
を含んでもよい。
Nuclear metal book? Methods of attaching include plating, vapor deposition, sputtering, m
You can also use one of the methods that exclusively involves dipping into the beak of insects. When the bumps 2 are formed on the Al electrode side, the bumps 3t may be formed by applying a superfrequency wave to the molten metal or to the electrode side substrate. Furthermore, with soldering, the normal component becomes HPB.
May include.

リードとの接続は通常リード表面がAg、Sn。For connections with leads, the lead surface is usually Ag or Sn.

Au、Niはんだのいずれかのめっきがしであるか゛。Is it plated with either Au or Ni solder?

これとバンプの接続は通常の熱圧着で行れ、@1図(a
)〜(d)に示される様な構成をもつ半導体装置となる
The connection between this and the bump can be done by normal thermocompression bonding.
A semiconductor device having the configuration shown in ) to (d) is obtained.

(実施例) 以下1本発明の実施例を図面を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to the drawings.

実施例1 第2図は本発明の実施例で、Cuのインナーリード3V
cバンプ11ε形成させその表面にZn−In合金めっ
′a2をほどこしてから、このめっきをAノミ極4に直
接接続し、Zn−Al共晶反応層1vcよって接合され
た半導体装置である。この半導体装置の製造法は以下の
様になる。
Example 1 FIG. 2 shows an example of the present invention, in which the inner lead of Cu is 3V.
This is a semiconductor device in which a C bump 11ε is formed, a Zn-In alloy plating 'a2 is applied to the surface thereof, and this plating is directly connected to the A chisel pole 4, which is bonded by a Zn-Al eutectic reaction layer 1vc. The method for manufacturing this semiconductor device is as follows.

まず1通常のウニ八プロセスにより配線・電極の形成2
行なった後、全面にパッシベーション膜を堆積し、更に
コンタクトバット用の開孔V15を形り 成したシリコンウェハ珂?用意し友。前記配線パ電極は
スパッタリング製置により形成された嘆厚約1μm0A
l−2SS i −21Cuからなり。
First, 1. Formation of wiring and electrodes using the normal Unihachi process. 2.
After this, a passivation film was deposited on the entire surface of the silicon wafer, and an opening V15 for a contact butt was formed. Prepared friend. The wiring pad electrode is formed by sputtering and has a thickness of about 1 μm0A.
Consisting of l-2SS i-21Cu.

またパッジベージリン膜としては窒化シリコン膜が用い
られている。そして、このシリコンウニ八杷に形成され
た各チップには80μm口の電極(コンパクトパッド)
がそれぞれ64個形成されている0次に、このシリコン
ウニ11Aについてはプ゛レードダイシングを行なっ之
のち1個々の半導体チップにわけている。
Furthermore, a silicon nitride film is used as the padding film. Each chip formed on this silicon sea urchin Yawata has an 80 μm electrode (compact pad).
The silicon urchins 11A each having 64 pieces formed thereon are subjected to blade dicing and then divided into individual semiconductor chips.

次vc第2図にも示される様にパングー10ついたイン
ナーリード2もつテープを用意し、そV表面にZn−I
nめっきを行った。このめりき条件は以下の様な酒1石
散塩−アンモ;≦p浴からの11で行っている。尚めつ
き膜厚は5μmである。
Next, as shown in Figure 2, prepare a tape with 2 inner leads and 10 Pangu tapes, and coat the V surface with Zn-I.
n plating was performed. This grinding condition is carried out under the following conditions: 11 from the Sake 1 stone powdered salt-ammonium; ≦p bath. The plating film thickness was 5 μm.

亜鉛・−3011/l  インジウム−511711硫
酸ナトリウム−559/l  塩化ナトリウム−651
1/l  [lJ!アンモニ1フムー4 (11/に酒
石酸ナトリウム−2011/l  アンモニア−250
mJ/j  I)H−11アソード電流−1,IA/d
m意 浴温−27℃ このインナーリード!p200℃に加熱したインナーリ
ードボンダーのステージ・D上におきボンダーのツール
へ度を390℃とし2gの圧力で2秒間図芯2おこさせ
8274772行った。その麦Slデッグ部分樹脂封止
し、インナーリード■他端をデバイスのアウターリード
にはんだづけをし半導体装置としで完成させた。
Zinc - 3011/l Indium - 511711 Sodium sulfate - 559/l Sodium chloride - 651
1/l [lJ! Ammonia 1 humu 4 (11/sodium tartrate-2011/l ammonia-250
mJ/j I) H-11 anode current -1, IA/d
My intention Bath temperature -27℃ This inner reed! It was placed on the stage D of an inner lead bonder heated to 200°C, and the bonder tool was heated to 390°C and the drawing core 2 was raised for 2 seconds with a pressure of 2g. The SL deck was partially sealed with resin, and the other end of the inner lead was soldered to the outer lead of the device to complete the semiconductor device.

実IAガ2 まず、実施例1と同様なシリコンウニへ蛇3用意し九〇
この鴨合、配線・電極としてはAl−1俤SMが用いら
れ、シリコンウニへ祠に形成された各チップには60μ
m口の電極(コンタクトバット)がそれぞれ128個形
成されている。なお、このシリコンウェハーは素子形成
袋、かなりの期間2経てお9.4極表面が固い酸化膜で
、′J!われでいることが予けされtので、オゾン洗浄
2行なった。
Actual IA Ga2 First, prepare the same silicone wire as in Example 1, use Al-1 SM as the wiring and electrodes, and attach each chip formed in the silicone wire to the silicone wire. is 60μ
128 m-hole electrodes (contact butts) are each formed. In addition, this silicon wafer is an element forming bag, and after a considerable period of time, the surface of the 9.4 pole is a hard oxide film, and 'J! I didn't want to be alone, so I did two rounds of ozone cleaning.

あらかじめ半導体チップのAj電極の配列に対応し九バ
ンプ122別の基板に設けておいた。このバンプはめっ
きでつくっておりcu−Inp主成分とする。めっきの
成分としては以下の通りである。
Nine bumps 122 were previously provided on separate substrates corresponding to the arrangement of the Aj electrodes of the semiconductor chip. This bump is made by plating and has cu-Inp as its main component. The components of the plating are as follows.

シアン化tlii−3511/l  −J/アン化イン
ジウム−511/l  シアン化ナトリウム−1011
/l  カソード電流密2− I A / dm”温度
−25℃ さらにインナーリードとこの別居仮にもうけられたバン
プを当接させ熱処理してCu−InのバンプとSnめっ
きしたリードにIn−Snの共晶14を利用し転写した
のちバンプOついたリードを半導体チップの電極に対応
させてインナーリードボンディングをした。この際Cu
の酸化2ふせぐtめにNz+)It混合ガスどふきつけ
300℃で5秒間、551の荷重で接続し九。その仮エ
ポキシ樹脂13で、インナーリードD接涜された半導体
チップをモールドし外部にでたり−ド15をベンディン
グして半導体装置として完成させた。
Cyanide tlii-3511/l -J/Indium annide-511/l Sodium cyanide-1011
/l Cathode current density 2- I A / dm"Temperature -25℃Furthermore, the inner lead is brought into contact with the bump that was temporarily created in this separate house, and heat treated to form an In-Sn joint between the Cu-In bump and the Sn-plated lead. After transferring using Cu 14, inner lead bonding was performed by matching the leads with bumps O to the electrodes of the semiconductor chip.
After the second oxidation test, apply Nz+)It mixed gas at 300°C for 5 seconds and connect with a load of 551. The semiconductor chip with the inner leads D attached was molded using the temporary epoxy resin 13, and the leads 15 were bent to the outside to complete the semiconductor device.

実施例3 まず、 実t@例1と同様なシリコンウニへに)を用意
した。この喘合、配線・電極としてはAl−1=184
が用いられ、シリコンウェハ綱に形成されt各チップに
は200μm口の11侃(コンタクトパッド)がそれぞ
れ12個形成されでいる。
Example 3 First, a silicone sea urchin similar to that in Example 1 was prepared. For this mesh, wiring and electrodes, Al-1 = 184
The contact pads are formed on a silicon wafer and each chip has 11 contacts (contact pads) each having a diameter of 200 μm.

このウニへ−の′vt極に相当する部分にあらかじめ電
極と同一径の穴をあけ之メタルマスク(Ttで作製)を
この穴と電極があうように位置あわせをしt6その?麦
150μm径のAIボールの表面にあらかじめ、40C
u−40Sn−20Bi O被II rU ’E−3μ
mはどこしておき、このボール2メタルマスクの穴にお
いt、その後ウニへ−基板1C20KHzの超鐙彼憑勧
を加えながら230℃で5秒間区持し。
A hole with the same diameter as the electrode is pre-drilled in the part corresponding to the 'vt pole of this sea urchin, and a metal mask (made in Tt) is positioned so that this hole matches the electrode. 40C was applied in advance to the surface of an AI ball with a diameter of 150 μm.
u-40Sn-20Bi O II rU 'E-3μ
Place m somewhere, put the ball into the hole of the metal mask, and then heat the sea urchin at 230°C for 5 seconds while applying a 20KHz super stirrup signal to the board.

ボール?バンブとしvL甑上に形成した。この際損動に
よりメタルマスクの穴からAjボールがとびだ丁事もあ
っ九のでポリイミドDテープとすでに穴にボール導入っ
たメタルマスクの上に全面にはっ九。さらに一部接者が
不充分々ボールもあっ九ツ ので300℃に加熱し之ボンディング歩#−ルに2gの
荷重分かけボール分おし、つけ、固着?充分なものとし
た。
ball? It was made into a bamboo and formed on a vL koshiki. At this time, due to the damage, the AJ ball jumped out of the hole in the metal mask, so it completely covered the polyimide D tape and the metal mask that had already introduced the ball into the hole. Furthermore, some of the balls were not in good contact, so I heated them to 300℃, applied a load of 2g to the bonding step, and pushed the balls in place to make them stick. It was considered sufficient.

この様にしてできたバンプつきウニ八−をダイジングし
たのち1個々のチップにし、AIめっきとしたCuリー
ドのインナーリード部6バングに直接接続し、第1図(
C)の様なバンプ淡合部の構成?もつ半導体装置2製造
させた。
After dicing the bumped sea urchin eight produced in this way, it was made into one individual chip, which was directly connected to the inner lead part 6 bang of the AI-plated Cu lead, as shown in Figure 1.
Is the configuration of the bump blending part like C)? Manufactured two semiconductor devices.

実施例4 まず、泉施し1」1と同様なりリコンウェハセ叶2用意
し九〇この1隨合、配線・電極としてはAl−11st
が用いられ、シリコンウェハ掴に形成され比容チップに
(1500μm口の′成極(コンタクトパッド)がそれ
ぞれ211N形成されでいる。
Example 4 First, prepare a silicone wafer sheet 2 as in 1, and use Al-11st for wiring and electrodes.
was used, and 211N contact pads (1500 μm in diameter) were formed on the silicon wafer grip and on the specific capacitance chip.

次にAuめっきし2Cuインナーリード2具備したキャ
リアチーブ3用意し、インナーリードの先端16に財4
図で示す様にめっき18の上に酸化を防ぐ之めvCN 
2ガスをふきつけながら行りた。その後、ダイシングさ
れた半導体θテップ上に電極と立喧合わせ?してバンプ
2層合させた。
Next, prepare a carrier chip 3 equipped with 2 Au-plated 2Cu inner leads, and attach a material 4 to the tip 16 of the inner lead.
As shown in the figure, vCN is applied on top of plating 18 to prevent oxidation.
I went there while blowing gas. After that, the electrodes are placed on the diced semiconductor θ tip? Then, the two bump layers were combined.

この時の温度は230℃で、リードと電極間の距離を2
0μm#/c深ちながら行った。この際圧力(まかけて
いないが、4QKHzの超i彼?インナーリードと通し
、浴融したバンプに付加し、電極上のAIの原化膜2と
りOぞいで接合さtている。そつ1及ポツテイング麟e
テツプ浸jに滴Fし固化させて基板上に装着しto 実施例5 実施例1と同様な半導体チップを用意し、さらに実施列
1と同様な形犬2しtインナーリード分もつキャリアテ
ープビ容易した。このインナーリードのパンダ部に80
Cd−20Zn7)めっきを膜厚3μmで成長させ九〇
その後実施例1と同様な半導体装置?作製した。
The temperature at this time was 230℃, and the distance between the lead and the electrode was 2
The depth was 0 μm #/c. At this time, pressure (although not applied) was passed through the inner lead of 4QKHz, applied to the bump melted in the bath, and bonded to the AI original film 2 on the electrode. and potting ring
Example 5 A semiconductor chip similar to that in Example 1 was prepared, and a carrier tape with a shape similar to that in Example 1 and a carrier tape with an inner lead portion was added. It was easy. 80 in the panda part of this inner lead
Cd-20Zn7) plating was grown to a film thickness of 3 μm, and then a semiconductor device similar to that of Example 1 was produced. Created.

〔発明の効果〕〔Effect of the invention〕

本@明によれば従来バンプ硬度が高く接合不可能であっ
た。Zn、Sn、Uu等のパンダも軟化させ改良する蔓
ができる。また金バンプに比べ隠めでがん便々工程でバ
ンプを形FRfる”iZができワイヤレスボンディング
技術の導入2琴易にし、素子の微細化に対[F]してボ
ンディングの信頼性の高い半導体装置2製造できる等産
梁上極めて顕著な効果?うむものである。
According to Akira Hon@Mei, the hardness of conventional bumps was so high that it was impossible to bond them. Pandas such as Zn, Sn, and Uu also have vines that soften and improve them. In addition, compared to gold bumps, it is possible to form bumps in a hidden process in a more convenient process.Introduction of wireless bonding technology2. This has a very significant effect on the production efficiency of the device 2.

【図面の簡単な説明】[Brief explanation of the drawing]

Claims (2)

【特許請求の範囲】[Claims] (1)Alを主成分とする電極を有する半導体ペレツト
と、この電極に直接形成されたバンプと、このバンプに
接続されたリードを備えた半導体装置において、少なく
ともバンプの電極との接合表面が、Zn、Sn及びCu
の少なくとも2種を主成分とする合金もしくはZn、S
n及びCuの少なくとも一種とIn、Bi及びCdの少
なくとも1種とを主成分とする合金で形成されており、
バンプと電極との接合がAl−Zn及びAl−Snの共
晶又はAl−Cuの金属間化合物の少なくとも一種の反
応により直接接合されていることを特徴とする半導体装
置。
(1) In a semiconductor device including a semiconductor pellet having an electrode mainly composed of Al, a bump formed directly on the electrode, and a lead connected to the bump, at least the bonding surface of the bump with the electrode is Zn, Sn and Cu
An alloy containing at least two of the following as main components or Zn, S
It is formed of an alloy whose main components are at least one of n and Cu and at least one of In, Bi and Cd,
1. A semiconductor device characterized in that a bump and an electrode are directly bonded by a reaction of at least one type of eutectic of Al-Zn and Al-Sn or an intermetallic compound of Al-Cu.
(2)前記バンプを有するリード又はテープキャリアボ
ンディング用テープを有することを特徴とする特許請求
の範囲第1項記載の半導体装置。
(2) The semiconductor device according to claim 1, further comprising a lead or tape carrier bonding tape having the bumps.
JP61228211A 1986-09-29 1986-09-29 Semiconductor device Expired - Lifetime JPH0732170B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61228211A JPH0732170B2 (en) 1986-09-29 1986-09-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61228211A JPH0732170B2 (en) 1986-09-29 1986-09-29 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6384127A true JPS6384127A (en) 1988-04-14
JPH0732170B2 JPH0732170B2 (en) 1995-04-10

Family

ID=16872929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61228211A Expired - Lifetime JPH0732170B2 (en) 1986-09-29 1986-09-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0732170B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6002287A (en) * 1997-05-08 1999-12-14 Canon Kabushiki Kaisha Signal outputting apparatus
US7709947B2 (en) 2006-06-15 2010-05-04 Kabushiki Kaisha Toyota Jidoshokki Semiconductor device having semiconductor element with back electrode on insulating substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6002287A (en) * 1997-05-08 1999-12-14 Canon Kabushiki Kaisha Signal outputting apparatus
US7709947B2 (en) 2006-06-15 2010-05-04 Kabushiki Kaisha Toyota Jidoshokki Semiconductor device having semiconductor element with back electrode on insulating substrate

Also Published As

Publication number Publication date
JPH0732170B2 (en) 1995-04-10

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