JP2003017531A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2003017531A
JP2003017531A JP2001201012A JP2001201012A JP2003017531A JP 2003017531 A JP2003017531 A JP 2003017531A JP 2001201012 A JP2001201012 A JP 2001201012A JP 2001201012 A JP2001201012 A JP 2001201012A JP 2003017531 A JP2003017531 A JP 2003017531A
Authority
JP
Japan
Prior art keywords
solder
semiconductor device
layer
joining
melting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001201012A
Other languages
Japanese (ja)
Other versions
JP3868766B2 (en
Inventor
Soichi Honma
荘一 本間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2001201012A priority Critical patent/JP3868766B2/en
Publication of JP2003017531A publication Critical patent/JP2003017531A/en
Application granted granted Critical
Publication of JP3868766B2 publication Critical patent/JP3868766B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a connection part in a semiconductor device where a semiconductor element is connected to a wiring substrate by flip chip. SOLUTION: In the semiconductor device of the present invention, an electrode terminal of the semiconductor element and the wiring layer of the wiring substrate are connected to each other via a bump by two or more kinds of connection forms. As the connection forms via the bump, two or more kinds of connection forms that are selected from the connection by melting solders each other, the connection by melting the solder and metal getting wet thereto, the connection by mutually diffusing or pressing the same kind or different kinds of metals, and the connection by contacting conductive particles can be applied.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に係わ
り、さらに詳しくは、半導体素子が配線基板にフリップ
チップ接続された半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor element is flip-chip connected to a wiring board.

【０００２】[0002]

【従来の技術】従来から、半導体チップを配線基板に搭
載し接続する実装技術の一つとして、フリップチップ接
続がある。フリップチップ接続部の構造の一例を、以下
に示す。2. Description of the Related Art Conventionally, flip chip connection is one of the mounting techniques for mounting and connecting a semiconductor chip on a wiring board. An example of the structure of the flip chip connection part is shown below.

【０００３】フリップチップ接続部では、図２２に示す
ように、配線基板５１の配線パッド５２形成面上に、半
導体チップ５３がフェースダウンで搭載され、この半導
体チップ５３の電極端子５４と基板側の配線パッド５２
とが、金（Ａｕ）バンプ５５などを介してはんだ５６に
より電気的・機械的に接続されている。なお、この図に
おいて、符号５７および５８は、配線パッド５２上に積
層されて形成されたＮｉ層およびＡｕ層をそれぞれ示
し、５９はソルダーレジスト層、６０はパッシベーショ
ン膜をそれぞれ示す。また、図示を省略したが、このよ
うなフリップチップ接続部の外側には、エポキシ樹脂の
ような絶縁樹脂の封止層がポッティングなどにより形成
される。In the flip chip connection portion, as shown in FIG. 22, a semiconductor chip 53 is mounted face down on the surface of the wiring board 51 on which the wiring pads 52 are formed, and the electrode terminals 54 of this semiconductor chip 53 and the board side. Wiring pad 52
Are electrically and mechanically connected by solder 56 via gold (Au) bumps 55 and the like. In this figure, reference numerals 57 and 58 denote a Ni layer and an Au layer formed on the wiring pad 52, 59 denotes a solder resist layer, and 60 denotes a passivation film. Although not shown, a sealing layer of an insulating resin such as an epoxy resin is formed by potting or the like on the outside of the flip chip connection portion.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、このよ
うな従来のフリップチップ接続部においては、以下に示
す問題があった。すなわち、Ａｕバンプ５５とはんだ５
６（例えば、Ｓｎ−Ｐｂはんだ）層との界面にＡｕ−Ｓ
ｎ金属間化合物が生成するが、このＡｕ−Ｓｎ金属間化
合物の接合が過度に進行すると、接合強度が低下して、
接合部に歪みが加わったとき接続信頼性が低下するとい
う問題があった。However, such a conventional flip-chip connection section has the following problems. That is, the Au bump 55 and the solder 5
6 (for example, Sn-Pb solder) layer at the interface with Au-S
Although an n intermetallic compound is generated, if the bonding of the Au-Sn intermetallic compound progresses excessively, the bonding strength decreases,
There is a problem that the connection reliability is deteriorated when strain is applied to the joint.

【０００５】この問題を解決するため、はんだ量を少な
くしてＡｕ−Ｓｎ金属間化合物の生成を抑える方法が考
えられるが、その方法でははんだの融着による接続が良
好に行われないという問題があった。In order to solve this problem, a method of suppressing the formation of Au--Sn intermetallic compound by reducing the amount of solder can be considered. However, this method has a problem that the connection by the fusion of the solder is not performed well. there were.

【０００６】さらに、Ａｕバンプ５５に代えて、はんだ
のボール状バンプを用いて接合を行ったフリップチップ
接続部も用いられている。しかし、そのようなフリップ
チップ接続部では、はんだバンプのスタンドオフ効果が
十分でないため、電極端子間の短絡防止や半導体チップ
と基板との間隔維持効果が十分に得られないという問題
があった。Further, in place of the Au bump 55, a flip chip connection portion in which a solder ball-shaped bump is used for bonding is also used. However, in such a flip-chip connection part, the stand-off effect of the solder bump is not sufficient, so that there is a problem in that the effect of preventing a short circuit between the electrode terminals and the effect of maintaining the distance between the semiconductor chip and the substrate cannot be sufficiently obtained.

【０００７】本発明は、これらの問題を解決するために
なされたもので、半導体素子が配線基板にフリップチッ
プ接続された半導体装置において、接続部の信頼性を高
めることを目的とする。The present invention has been made to solve these problems, and it is an object of the present invention to improve the reliability of a connecting portion in a semiconductor device in which a semiconductor element is flip-chip connected to a wiring board.

【０００８】[0008]

【課題を解決するための手段】本発明の半導体装置は、
請求項１に記載するように、絶縁基板の少なくとも一方
の主面に配線層が形成された配線基板と、前記配線基板
の配線層形成面上にフェースダウンに搭載された半導体
素子と、前記半導体素子の電極端子と前記配線基板の配
線層の少なくとも一方の上に形成されたバンプを備え、
前記半導体素子の電極端子と前記配線基板の配線層と
が、前記バンプを介する２種類以上の接合形態により接
続されていることを特徴とする。The semiconductor device of the present invention comprises:
A wiring board having a wiring layer formed on at least one main surface of an insulating substrate, a semiconductor element mounted facedown on a wiring layer formation surface of the wiring board, and the semiconductor according to claim 1. An electrode terminal of the element and a bump formed on at least one of the wiring layers of the wiring board,
It is characterized in that the electrode terminals of the semiconductor element and the wiring layer of the wiring board are connected by two or more kinds of bonding forms via the bumps.

【０００９】本発明の半導体装置においては、請求項２
に記載するように、バンプを介する接合形態が、はんだ
同士の溶融による接合、はんだとそれに濡れる金属との
溶融による接合、同種または異種の金属相互の拡散また
は圧接による接合、導電性粒子同士の接触による接合か
ら選ばれる２種類以上の接合形態であることができる。According to another aspect of the semiconductor device of the present invention,
As described in, the joining form via bumps is joining by melting of solders, joining by melting of solder and a metal wettable to it, joining by diffusion or pressure welding of the same kind or different kinds of metals, contact between conductive particles It is possible to have two or more types of joining forms selected from joining by

【００１０】そして、請求項３に記載するように、はん
だ同士の溶融による接合として、Ｓｎ、Ｐｂ、Ａｇ、Ｂ
ｉ、Ｚｎ、Ｉｎ、Ｓｂ、Ｃｕ、Ｇｅの金属単独、これら
の金属の混合物または化合物から選ばれるはんだの１種
または２種以上の溶融による接合形態を用いることがで
きる。Further, as described in claim 3, as the joining by melting the solders, Sn, Pb, Ag, B
It is possible to use a joint mode by melting one or more solders selected from the metals i, Zn, In, Sb, Cu and Ge alone, or a mixture or compound of these metals.

【００１１】また、請求項４に記載するように、はんだ
とそれに濡れる金属との溶融による接合として、Ｓｎ、
Ｐｂ、Ａｇ、Ｂｉ、Ｚｎ、Ｉｎ、Ｓｂ、Ｃｕ、Ｇｅの金
属単独、これらの金属の混合物または化合物から選ばれ
るはんだと、Ｃｕ、Ｎｉ、Ａｕ、Ｐｄ、Ａｇから選ばれ
るはんだに濡れる金属との間の、前記はんだの溶融によ
る接合形態を用いることができる。Further, as described in claim 4, as a joint by melting the solder and a metal wettable with the solder, Sn,
Pb, Ag, Bi, Zn, In, Sb, Cu, Ge metal alone, a solder selected from a mixture or compound of these metals, and a metal wettable by a solder selected from Cu, Ni, Au, Pd, Ag In the meantime, a joining mode by melting the solder can be used.

【００１２】また、請求項５に記載するように、同種ま
たは異種の金属相互の拡散または圧接による接合とし
て、Ｃｕ，Ｎｉ、Ａｕ、Ｐｄ、Ｗ、Ｔｉ、Ｃｒ、ＴｉＮ
（窒化チタン）、Ｔａ、ＴａＮ（窒化タンタル）、Ｎ
ｂ、Ｆｅ、Ａｇの単独、これらの混合物または化合物か
ら選ばれる金属の１種または２種以上の間の拡散または
接触による接合形態を用いることができる。Further, as described in claim 5, Cu, Ni, Au, Pd, W, Ti, Cr, TiN are used as the bonding by diffusion or pressure welding of the same or different metals.
(Titanium nitride), Ta, TaN (tantalum nitride), N
It is possible to use a bonding mode by diffusion or contact between one or more metals selected from b, Fe and Ag alone, or a mixture or compound thereof.

【００１３】さらに、請求項６に記載するように、導電
性粒子同士の接触による接合として、異方性導電材料中
のＡｕ、Ｎｉ、Ｐｄ、Ｃｕ、Ａｇから選ばれる１種また
は２種以上の金属を含む粒子相互の接触による接合形態
を用いることができる。Further, as described in claim 6, as the joining by the contact of the conductive particles, one or more kinds selected from Au, Ni, Pd, Cu and Ag in the anisotropic conductive material are used. It is possible to use a joining mode in which particles containing a metal are brought into contact with each other.

【００１４】本発明に使用する絶縁基板としては、ガラ
ス基板、セラミック基板、樹脂含浸ガラスクロス基板、
あるいはポリイミド樹脂テープのような樹脂基板などが
挙げられる。The insulating substrate used in the present invention includes a glass substrate, a ceramic substrate, a resin-impregnated glass cloth substrate,
Alternatively, a resin substrate such as a polyimide resin tape may be used.

【００１５】本発明においては、このような絶縁基板の
少なくとも一方の主面に、銅、銅系合金、金等から成る
配線層が形成されている。配線層の形成は、樹脂含浸ガ
ラスクロス基板や樹脂基板では、銅箔のエッチングなど
により行なわれ、ガラス基板やセラミック基板のような
無機材料系の絶縁基板においては、真空蒸着やスパッタ
リングなどの物理的蒸着（ＰＶＤ）法や化学的蒸着（Ｃ
ＶＤ）法により薄膜を形成した後、パターニングする方
法、あるいは導電ペーストを所定のパターンで印刷した
後焼成する方法などで行うことができる。In the present invention, a wiring layer made of copper, a copper alloy, gold or the like is formed on at least one main surface of such an insulating substrate. The wiring layer is formed by etching copper foil on a resin-impregnated glass cloth substrate or a resin substrate, and by using an inorganic material-based insulating substrate such as a glass substrate or a ceramic substrate, a physical layer such as vacuum deposition or sputtering is used. Vapor deposition (PVD) method and chemical vapor deposition (C
The method can be performed by forming a thin film by the VD method and then patterning it, or by printing a conductive paste in a predetermined pattern and then firing it.

【００１６】また、銅配線層の上には、銅の酸化を防
ぎ、金バンプ等との接合を強固にするために、Ｎｉ層を
介してＡｕ層を積層し、Ｎｉ−Ａｕ層を形成することが
好ましい。なお、配線層全体に亘ってＮｉ−Ａｕ層を形
成しても良いが、接続用のパッド部のみに形成しても十
分な効果を上げることができる。Further, on the copper wiring layer, an Au layer is laminated via a Ni layer to form a Ni-Au layer in order to prevent the oxidation of copper and strengthen the bonding with a gold bump or the like. It is preferable. Although the Ni-Au layer may be formed over the entire wiring layer, it is possible to sufficiently enhance the effect by forming it only on the pad portion for connection.

【００１７】本発明において、バンプは、半導体素子の
電極端子上または配線基板の配線パッド上あるいはその
両方に設けられる。バンプとしては、例えば金のボール
状バンプが挙げられる。金バンプの形成は、ワイヤボン
ダのキャピラリー先端に金ボールを形成し、この金ボー
ルを半導体素子の電極端子上等に接合し、キャピラリー
でボールのネック部を切断する方法により行なうことが
できる。In the present invention, the bump is provided on the electrode terminal of the semiconductor element, the wiring pad of the wiring board, or both. Examples of bumps include gold ball-shaped bumps. The gold bumps can be formed by forming a gold ball on the tip of the capillary of the wire bonder, bonding the gold ball to an electrode terminal of a semiconductor element or the like, and cutting the neck portion of the ball with the capillary.

【００１８】本発明の半導体装置では、配線基板の配線
層と半導体素子の電極端子とが、前記した金バンプのよ
うなバンプを介した２種類以上の接合形態により接続さ
れているので、接合部の接続信頼性が向上する。また、
金バンプを用いることで、バンプのスタンドオフ効果に
より、電極端子間の短絡の防止や半導体素子と基板との
間隔維持が達成され、安定した信頼性の高いフリップチ
ップ接続が実現される。In the semiconductor device of the present invention, since the wiring layer of the wiring board and the electrode terminals of the semiconductor element are connected by two or more kinds of bonding modes via bumps such as the gold bumps described above, the bonding portion Connection reliability is improved. Also,
By using the gold bumps, the stand-off effect of the bumps can prevent a short circuit between the electrode terminals and maintain the distance between the semiconductor element and the substrate, thereby realizing stable and highly reliable flip chip connection.

【００１９】[0019]

【発明の実施の形態】以下、本発明の実施例を図面に基
づいて説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

【００２０】図１は、本発明の半導体装置の第１の実施
例を示す断面図である。図において、符号１は、ポリイ
ミド樹脂テープ、樹脂基板、セラミック基板のような絶
縁基板を示す。この絶縁基板１の片面（図では上面）に
Ｃｕからなる配線層が設けられ、その配線パッド（Ｃｕ
パッド）２上に、Ｎｉ層３とＡｕ層４が積層されて形成
されている。そして、このような配線基板の配線層形成
面において、配線パッド２以外の領域には、エポキシ樹
脂等のソルダーレジスト層５が設けられている。また、
配線パッド２上に形成されたＡｕ層４の上には、はんだ
（Ｓｎ−Ｐｂはんだ）層６が中央部を除いてドーナツ状
に形成されている。FIG. 1 is a sectional view showing a first embodiment of the semiconductor device of the present invention. In the figure, reference numeral 1 indicates an insulating substrate such as a polyimide resin tape, a resin substrate, or a ceramic substrate. A wiring layer made of Cu is provided on one surface (upper surface in the figure) of the insulating substrate 1, and the wiring pad (Cu
The Ni layer 3 and the Au layer 4 are laminated on the pad 2 to be formed. Then, on the wiring layer forming surface of such a wiring board, a solder resist layer 5 such as an epoxy resin is provided in a region other than the wiring pad 2. Also,
On the Au layer 4 formed on the wiring pad 2, a solder (Sn—Pb solder) layer 6 is formed in a donut shape except for the central portion.

【００２１】一方、符号７はシリコン等の半導体チップ
を示し、そのＡｌからなる電極パッド８上には、先端に
小突起を有するボール状の金バンプ９が形成されてい
る。なお、符号１０は、パッシベーション膜を示す。On the other hand, reference numeral 7 indicates a semiconductor chip made of silicon or the like, and ball-shaped gold bumps 9 having small protrusions at the tips are formed on the electrode pads 8 made of Al. Reference numeral 10 indicates a passivation film.

【００２２】このような半導体チップ７が、フェースダ
ウンに配置され、配線基板上に搭載されている。そし
て、金バンプ９の先端部が基板側の配線パッド２のＡｕ
層４に圧接され、界面にＡｕとＡｕの相互拡散による接
合（Ａｕ−Ａｕ拡散接合）が形成されている。また、金
バンプ９の側周部は、基板側にドーナツ状に形成された
はんだ層６と接合されている。すなわち、金バンプ９の
側周部とはんだ層６との間には、はんだの溶融（融着）
による接合部が形成されている。Such a semiconductor chip 7 is arranged face down and mounted on a wiring board. The tip of the gold bump 9 is Au of the wiring pad 2 on the substrate side.
The layer 4 is pressure-welded to form a bond (Au-Au diffusion bond) by mutual diffusion of Au and Au at the interface. Further, the side portion of the gold bump 9 is joined to the solder layer 6 formed in a donut shape on the substrate side. That is, between the side peripheral portion of the gold bump 9 and the solder layer 6, the solder is melted (fused).
To form a joint.

【００２３】さらに、半導体チップ７と配線基板との間
には、図示を省略したが、エポキシ樹脂、アクリル樹
脂、シリコーン樹脂等の絶縁樹脂が充填され、これらの
絶縁樹脂によりフリップチップ接続部が封止されてい
る。Although not shown in the drawing, an insulating resin such as an epoxy resin, an acrylic resin or a silicone resin is filled between the semiconductor chip 7 and the wiring board, and the flip chip connection portion is sealed by these insulating resins. It has been stopped.

【００２４】このような第１の実施例の半導体装置は、
以下に示すように製造される。The semiconductor device of the first embodiment as described above is
It is manufactured as shown below.

【００２５】まず、図２に示すように、シリコン等の半
導体ウェハ１１（例えば、直径６インチ、厚さ６２５μ
ｍ）の全面に、Ａｌ電極パッド８を形成した後、その上
に、電極パッド８の中心部を開口部とするパッシベーシ
ョン膜１０を形成する。なお、Ａｌ電極パッド８の大き
さは例えば８０μｍ角とし、これらの電極パッド８は、
後工程で形成される個々の半導体チップ（３ｍｍ×３ｍ
ｍ）の周辺部に相当する領域に、１２０μｍのピッチで
形成されている。First, as shown in FIG. 2, a semiconductor wafer 11 made of silicon or the like (for example, a diameter of 6 inches and a thickness of 625 μm is used).
After the Al electrode pad 8 is formed on the entire surface of m), the passivation film 10 having the central portion of the electrode pad 8 as an opening is formed thereon. The size of the Al electrode pads 8 is, for example, 80 μm square, and these electrode pads 8 are
Individual semiconductor chips (3mm x 3m)
m) is formed in a region corresponding to the peripheral portion at a pitch of 120 μm.

【００２６】この半導体ウェハ１１のＡｌ電極パッド８
上に、先端に小突起を有するボール状の金バンプ９を、
ワイヤボンダにより１個ずつ形成する。金バンプ９の径
は６０μｍ、高さは７０μｍとする。Al electrode pad 8 of this semiconductor wafer 11
Above the ball-shaped gold bump 9 having a small protrusion at the tip,
Form one by one with a wire bonder. The gold bump 9 has a diameter of 60 μm and a height of 70 μm.

【００２７】また、図３に示すように、ポリイミド樹脂
テープ、樹脂基板、セラミック基板などの絶縁基板１の
片面にＣｕの配線パッド２が設けられ、配線パッド２以
外の領域にエポキシ樹脂等のソルダーレジスト層５が形
成された配線基板を用意し、その配線パッド２上に、無
電解めっきなどによりＮｉ層３とＡｕ層４を積層して形
成する。そして、図４に示すように、このＡｕ層４の中
央部にレジスト層１２を形成する。Further, as shown in FIG. 3, a Cu wiring pad 2 is provided on one surface of an insulating substrate 1 such as a polyimide resin tape, a resin substrate or a ceramic substrate, and a solder such as an epoxy resin is provided in a region other than the wiring pad 2. A wiring board on which a resist layer 5 is formed is prepared, and a Ni layer 3 and an Au layer 4 are formed on the wiring pad 2 by electroless plating. Then, as shown in FIG. 4, a resist layer 12 is formed in the center of the Au layer 4.

【００２８】次いで、Ａｕ層４の上にＳｎ−Ｐｂはんだ
層６をめっきにより形成した後、レジスト層１２を剥離
・除去する。めっき法以外に、はんだを含むペーストを
メタルマスクを用いて印刷する方法を採ることもでき
る。こうして、図５（ａ）に示すように、Ａｕ層４の上
にドーナツ状のはんだ層６が形成される。このはんだ層
６の上面図を、図５（ｂ）に示す。Next, the Sn-Pb solder layer 6 is formed on the Au layer 4 by plating, and then the resist layer 12 is peeled and removed. In addition to the plating method, a method of printing a paste containing solder using a metal mask can be adopted. Thus, as shown in FIG. 5A, a donut-shaped solder layer 6 is formed on the Au layer 4. A top view of the solder layer 6 is shown in FIG.

【００２９】次に、半導体ウェハをダイシングして個々
の半導体チップとした後、半導体チップを以下に示すよ
うにフリップチップ接続して、半導体装置とする。Next, after dicing the semiconductor wafer into individual semiconductor chips, the semiconductor chips are flip-chip connected as shown below to obtain a semiconductor device.

【００３０】すなわち、図６に示すように、チップ側に
形成された金バンプ９の先端部が基板側のＡｕ層４の中
央部（ドーナツ状のはんだ層６の穴部より露出した部
分）に当接するように、半導体チップ７と配線基板との
位置合わせを行い、熱圧着法、超音波併用熱圧着法など
により接合を行う。図７は、超音波を併用した熱圧着に
より接合する工程を模式的に示す図である。この図にお
いて、符号１３は、超音波印加ツールを示し、符号１４
は真空穴を示す。That is, as shown in FIG. 6, the tip of the gold bump 9 formed on the chip side is located at the central portion of the Au layer 4 on the substrate side (the portion exposed from the hole of the donut-shaped solder layer 6). The semiconductor chip 7 and the wiring board are aligned so that they come into contact with each other, and they are joined by a thermocompression bonding method, an ultrasonic combined thermocompression bonding method or the like. FIG. 7: is a figure which shows typically the process of joining by thermocompression bonding which used ultrasonic waves together. In this figure, reference numeral 13 indicates an ultrasonic wave application tool, and reference numeral 14
Indicates a vacuum hole.

【００３１】熱圧着法では、例えば３５０度の温度で２
０秒間加熱して接合する。超音波併用熱圧着法では、２
００度の温度に加熱し、かつ超音波強度５Ｗで１秒間超
音波を印加し、バンプ１個当たり１００ｇの荷重をかけ
て接合を行う。In the thermocompression bonding method, for example, at a temperature of 350.degree.
Heat for 0 seconds to bond. In the ultrasonic thermocompression bonding method, 2
Heating is performed at a temperature of 00 degrees, ultrasonic waves are applied at an ultrasonic wave intensity of 5 W for 1 second, and a load of 100 g per bump is applied to perform bonding.

【００３２】こうして、金バンプ９の先端部と基板側の
Ａｕ層４との圧接部に、Ａｕ−Ａｕ拡散接合部が形成さ
れる。また、金バンプ９の側周部と基板側のはんだ層６
との間に、はんだの溶融（融着）による接合部が形成さ
れる。Thus, an Au-Au diffusion bonding portion is formed at the pressure contact portion between the tip of the gold bump 9 and the Au layer 4 on the substrate side. In addition, the peripheral portion of the gold bump 9 and the solder layer 6 on the substrate side
A joint part is formed by melting (fusing) the solder between and.

【００３３】その後、エポキシ樹脂、アクリル樹脂、シ
リコーン樹脂などの絶縁樹脂を、半導体チップ７と配線
基板との間のギャップに、毛細管現象を利用して、ある
いは真空印刷樹脂封止法、真空モールド法などにより充
填し、接続部を封止する。Thereafter, an insulating resin such as an epoxy resin, an acrylic resin, or a silicone resin is used in the gap between the semiconductor chip 7 and the wiring board by utilizing a capillary phenomenon, or by a vacuum printing resin sealing method or a vacuum molding method. And the like, and the connection part is sealed.

【００３４】なお、封止用樹脂は、フリップチップ接続
を行う前に半導体チップ側に形成してもよいし、配線基
板側に形成して、接続と樹脂封止を一括して行ってもよ
い。一括して封止する樹脂は、ペースト状でもよいし、
固体状（例えば、予め成形されたシート）でもよい。The sealing resin may be formed on the semiconductor chip side before the flip-chip connection, or may be formed on the wiring board side so that the connection and the resin sealing are performed at once. . The resin to be sealed at once may be a paste,
It may be in solid form (eg preformed sheet).

【００３５】こうして製造される第１の実施例の半導体
装置においては、半導体チップ７のフリップチップ接続
部が、Ａｕ−Ａｕの拡散による接合とはんだの溶融によ
る接合という２種類の接合形態を有する。そして、はん
だの融着部に生成するＡｕ−Ｓｎ金属間化合物による接
続信頼性の低下を、Ａｕ−Ａｕの拡散接合部が補ってい
るので、安定した信頼性の高いフリップチップ接続が実
現される。また、金のスタッドバンプが使用されている
ため、十分なスタンドオフ効果が得られ、高い接続信頼
性が得られる。In the semiconductor device of the first embodiment manufactured in this way, the flip chip connection portion of the semiconductor chip 7 has two types of bonding modes: bonding by diffusion of Au-Au and bonding by melting of solder. Then, since the Au-Au diffusion bonding portion compensates for the decrease in the connection reliability due to the Au-Sn intermetallic compound generated in the fused portion of the solder, a stable and highly reliable flip chip connection is realized. . Further, since gold stud bumps are used, a sufficient standoff effect can be obtained and high connection reliability can be obtained.

【００３６】前述の工程にしたがって製造された第１の
実施例の半導体装置を、実際に温度サイクル試験に供し
て、接続信頼性を調べた。なお、半導体チップとして
は、５０個の金バンプが形成された３ｍｍ角のシリコン
チップを使用し、これをポリイミド樹脂基板上に実装し
て試験サンプルとした。温度サイクル試験は、（−６５
℃×３０分）〜（２５℃×５分）〜（１５０℃×３０
分）を１サイクルとして行った。The semiconductor device of the first embodiment manufactured according to the above-mentioned steps was actually subjected to a temperature cycle test to examine the connection reliability. As the semiconductor chip, a 3 mm square silicon chip on which 50 gold bumps were formed was used and mounted on a polyimide resin substrate to give a test sample. The temperature cycle test is (-65
℃ × 30 minutes) ~ (25 ℃ × 5 minutes) ~ (150 ℃ × 30
Min) as one cycle.

【００３７】温度サイクル試験の結果、３０００サイク
ル後でも接続箇所（フリップチップ接続部）に破断の発
生が全く認められなかった。また、金バンプの接合強度
（シェア強度）は、バンプ１個当たり４０ｇｆ／個で、
従来のフリップチップ接続部における２０ｇｆ／個に比
べて大幅に向上しており、バンプの剥離および強度の劣
化は全く起こらなかった。さらに、バンプ間でのショー
トも発生しなかった。As a result of the temperature cycle test, no breakage was observed at the connection portion (flip chip connection portion) even after 3000 cycles. Further, the bonding strength (share strength) of the gold bump is 40 gf / piece per bump,
This is a significant improvement over the conventional flip chip connection of 20 gf / piece, and peeling of bumps and deterioration of strength did not occur at all. Furthermore, no short circuit occurred between the bumps.

【００３８】次に、第２の実施例について説明する。Next, the second embodiment will be described.

【００３９】第２の実施例の半導体装置は、以下に示す
ようにして製造される。まず、図８に示すように、シリ
コン等の半導体ウェハ１１（例えば、直径６インチ、厚
さ６２５μｍ）の全面に、Ａｌ電極パッド８を形成した
後、その上に電極パッド８の中心部を開口部とするパッ
シベーション膜１０を形成する。なお、電極パッド８の
大きさは例えば１００μｍ角とし、これらの電極パッド
８は、後工程で形成される個々の半導体チップ（１５ｍ
ｍ×１５ｍｍ）の全面に、２５０μｍのピッチでエリア
状に形成されている。The semiconductor device of the second embodiment is manufactured as follows. First, as shown in FIG. 8, after forming an Al electrode pad 8 on the entire surface of a semiconductor wafer 11 made of silicon or the like (for example, a diameter of 6 inches and a thickness of 625 μm), a central portion of the electrode pad 8 is opened on the Al electrode pad 8. A passivation film 10 to be a part is formed. The size of the electrode pads 8 is, for example, 100 μm square, and these electrode pads 8 are formed on individual semiconductor chips (15 m) formed in a later process.
m × 15 mm) over the entire surface, and formed in an area shape with a pitch of 250 μm.

【００４０】次に、図９に示すように、この半導体ウェ
ハ１１の全面に、Ｔｉ膜１５、Ｎｉ膜１６およびＰｄ膜
１７を、スパッタリング、電子ビーム蒸着などの方法に
より順に積層して形成し、バリアメタル層とする。Next, as shown in FIG. 9, a Ti film 15, a Ni film 16 and a Pd film 17 are sequentially laminated on the entire surface of the semiconductor wafer 11 by a method such as sputtering and electron beam evaporation. As a barrier metal layer.

【００４１】次いで、図１０に示すように、このバリア
メタル層上に、フォトレジストを塗布し、５０μｍ程度
の厚さのレジスト層１８を形成した後、このレジスト層
１８を露光・現像し、Ａｌ電極パッド８に重なるように
１００μｍ角の開口部を形成する。そして、このレジス
ト層１８の開口部内にはんだめっきを行い、５０μｍ厚
のバンプ形成用のはんだ層１９を形成する。Then, as shown in FIG. 10, a photoresist is applied on the barrier metal layer to form a resist layer 18 having a thickness of about 50 μm, and then the resist layer 18 is exposed and developed to form Al. An opening of 100 μm square is formed so as to overlap with the electrode pad 8. Then, solder plating is performed in the openings of the resist layer 18 to form bump-forming solder layers 19 having a thickness of 50 μm.

【００４２】なお、はんだめっきは、以下に示すように
行われる。例えばＳｎ−Ｐｂ共晶はんだをめっきするに
は、スズ１２ｇ／Ｌ、鉛８ｇ／Ｌ、アルキルスルホン酸
１００ｇ／Ｌ、および界面活性剤を主成分とする添加剤
を含有する溶液中に、レジスト層１８のパターンが形成
された半導体ウェハ１１を浸漬し、浴温度２０℃でバリ
アメタル層を陰極、はんだ板（スズ６３重量％、鉛３７
重量％）を陽極として、電流密度１Ａ／ｄｍ２の条件で
緩やかに撹拌しながら電解めっきを行う。The solder plating is performed as shown below. For example, in order to plate Sn-Pb eutectic solder, a resist layer is added to a solution containing tin 12 g / L, lead 8 g / L, alkylsulfonic acid 100 g / L, and a surfactant-based additive. The semiconductor wafer 11 on which 18 patterns were formed was dipped, and the barrier metal layer was used as a cathode and a solder plate (63 wt% tin, 37 wt% lead) at a bath temperature of 20 ° C.
(% By weight) as an anode, and electrolytic plating is performed under conditions of a current density of 1 A / dm 2 with gentle stirring.

【００４３】その後、図１１に示すように、アセトンや
公知のレジスト剥離液を用いてレジストパターンを剥離
した後、下地電極として残ったＰｄ膜１７およびＮｉ膜
１６を、王水系のエッチング液を用いてエッチング除去
する。さらに、Ｔｉ膜１５を、エチレンジアミン四酢酸
系溶液を用いてエッチングする。After that, as shown in FIG. 11, after removing the resist pattern using acetone or a known resist stripping solution, the Pd film 17 and the Ni film 16 remaining as the underlying electrodes are replaced with an aqua regia etching solution. To remove by etching. Further, the Ti film 15 is etched using an ethylenediaminetetraacetic acid-based solution.

【００４４】次いで、この半導体ウェハ１１にロジン系
フラックスを塗布した後、窒素雰囲気中で２２０℃の温
度に３０秒間加熱してはんだをリフローし、図１２に示
すように、突起状のはんだ電極（はんだバンプ）２０を
形成する。その後、電気的なテストを行った後、半導体
ウェハをダイシングして個々の半導体チップとする。Then, after applying a rosin-based flux to the semiconductor wafer 11, the solder is reflowed by heating it to a temperature of 220 ° C. for 30 seconds in a nitrogen atmosphere, and as shown in FIG. Solder bumps) 20 are formed. Then, after conducting an electrical test, the semiconductor wafer is diced into individual semiconductor chips.

【００４５】一方、図１３に示すように、ポリイミド樹
脂テープ、樹脂基板、セラミック基板などの絶縁基板１
の片面にＣｕ配線パッド２が設けられ、かつ配線パッド
２以外の領域にエポキシ樹脂等のソルダーレジスト層５
が形成された配線基板を用意し、その配線パッド２上
に、無電解めっきなどによりＮｉ層３とＡｕ層４を積層
して形成する。そして、このＡｕ層４の中央部にレジス
ト層を形成した後、Ａｕ層４上に、Ｓｎ−Ｐｂはんだな
どのはんだ層６をめっき法や印刷法などによりドーナツ
状に形成する。On the other hand, as shown in FIG. 13, an insulating substrate 1 such as a polyimide resin tape, a resin substrate, or a ceramic substrate.
Is provided with a Cu wiring pad 2 on one surface thereof, and a solder resist layer 5 of epoxy resin or the like is provided in a region other than the wiring pad 2.
A wiring board on which is formed is prepared, and the Ni layer 3 and the Au layer 4 are laminated on the wiring pad 2 by electroless plating or the like. Then, after forming a resist layer at the center of the Au layer 4, a solder layer 6 such as Sn—Pb solder is formed in a donut shape on the Au layer 4 by a plating method or a printing method.

【００４６】次に、このドーナツ形状のはんだ層６の中
央穴部に、先端に小突起を有するボール状の金バンプ
（スタッドバンプ）９を、ワイヤボンダにより１個ずつ
形成する。Next, ball-shaped gold bumps (stud bumps) 9 having small protrusions at their tips are formed in the center hole of the doughnut-shaped solder layer 6 one by one using a wire bonder.

【００４７】次いで、図１４に示すように、このように
金バンプ９が形成された配線基板と前記したはんだバン
プ２０を有する半導体チップ７とを、金バンプ９がチッ
プ側のはんだバンプ２０に圧入するように位置合わせし
て仮止めし、加熱してはんだをリフローさせる。Next, as shown in FIG. 14, the wiring board having the gold bumps 9 thus formed and the semiconductor chip 7 having the solder bumps 20 are pressed into the solder bumps 20 on the chip side. Position, temporarily fix, and heat to reflow the solder.

【００４８】こうして、チップ側のはんだバンプ２０と
基板側のＡｕ層４上に形成されたはんだ層６とが溶融一
体化し、図１５に示すように、はんだ融着層２１が形成
されるとともに、基板側に形成された金バンプ９とチッ
プ側のはんだバンプ２０とが、はんだの溶融により接合
される。In this way, the solder bumps 20 on the chip side and the solder layer 6 formed on the Au layer 4 on the substrate side are melt-integrated to form the solder fusion layer 21 as shown in FIG. The gold bumps 9 formed on the substrate side and the solder bumps 20 on the chip side are joined by melting the solder.

【００４９】次いで、半導体チップ７と配線基板との間
のギャップにシリコーン樹脂を、毛細管現象を利用して
あるいは真空印刷樹脂封止法、真空モールド法などによ
り充填した後硬化させ、接続部を封止する。Then, a silicone resin is filled in the gap between the semiconductor chip 7 and the wiring board by using a capillary phenomenon or by a vacuum printing resin sealing method, a vacuum molding method or the like, and then cured to seal the connection portion. Stop.

【００５０】こうして製造される第２の実施例の半導体
装置においては、半導体チップ７のフリップチップ接続
部に、はんだ同士の溶融による接合とはんだの溶融（融
着）による接合という２種類の接合形態が含まれてい
る。そして、はんだの融着部に生成するＡｕ−Ｓｎ金属
間化合物による接続信頼性の低下を、はんだ同士の溶融
による接合が補っているので、安定した信頼性の高いフ
リップチップ接続が実現される。In the semiconductor device of the second embodiment manufactured as described above, two types of joining modes are used, that is, the flip chip connection portion of the semiconductor chip 7 is joined by melting the solders and joining by melting (fusion) the solders. It is included. Further, since the decrease in the connection reliability due to the Au-Sn intermetallic compound generated in the fused portion of the solder is compensated for by the joining due to the melting of the solders, a stable and highly reliable flip chip connection is realized.

【００５１】また、少量のフラックスでの接合が可能と
なるうえに、リフロー雰囲気によっては、フラックスな
しでの接合も可能になる。さらに、金のスタッドバンプ
が使用されているため、十分なスタンドオフ効果が得ら
れ、高い接続信頼性が得られる。Further, it is possible to perform joining with a small amount of flux and also possible to join without flux depending on the reflow atmosphere. Further, since gold stud bumps are used, a sufficient standoff effect can be obtained and high connection reliability can be obtained.

【００５２】前述の工程にしたがって製造された第２の
実施例の半導体装置を、実際に温度サイクル試験に供し
て接続信頼性を調べた。なお、半導体チップとしては、
２５００個のはんだバンプが形成された１０ｍｍ角のシ
リコンチップを使用し、これをポリイミド樹脂基板上に
実装してサンプルとした。温度サイクル試験は、（−６
５℃×３０分）〜（２５℃×５分）〜（１５０℃×３０
分）を１サイクルとして行った。The semiconductor device of the second embodiment manufactured according to the above process was actually subjected to a temperature cycle test to examine the connection reliability. As a semiconductor chip,
A 10 mm square silicon chip on which 2500 solder bumps were formed was used and mounted on a polyimide resin substrate to prepare a sample. The temperature cycle test is (-6
5 ° C x 30 minutes) ~ (25 ° C x 5 minutes) ~ (150 ° C x 30 minutes)
Min) as one cycle.

【００５３】温度サイクル試験の結果、３０００サイク
ル後でも接続箇所に破断の発生が全く認められなかっ
た。また、はんだバンプの接合強度（シェア強度）は、
バンプ１個当たり４０ｇｆ／個で、従来のフリップチッ
プ接続部における２０ｇｆ／個に比べて大幅に向上して
おり、バンプの剥離および強度の劣化は起こらなかっ
た。さらに、バンプ間でのショートも発生しなかった。As a result of the temperature cycle test, even after 3000 cycles, no breakage was observed at the connection portion. Also, the bonding strength (share strength) of the solder bump is
The number of bumps per bump was 40 gf / piece, which was significantly improved compared to 20 gf / piece in the conventional flip-chip connection part, and peeling of bumps and deterioration of strength did not occur. Furthermore, no short circuit occurred between the bumps.

【００５４】次に、第３の実施例について説明する。Next, the third embodiment will be described.

【００５５】第３の実施例の半導体装置を製造するに
は、まず図１６に示すように、シリコン等の半導体ウェ
ハ１１（例えば、直径６インチ、厚さ６２５μｍ）の全
面に、Ａｌ電極パッド８を形成した後、その上にパッド
の中心部を開口部とするパッシベーション膜１０を形成
する。なお、電極パッド８の大きさは例えば８０μｍ角
とし、これらの電極パッド８は、後工程で形成される個
々の半導体チップ（３ｍｍ×３ｍｍ）の周辺部に相当す
る領域に、１２０μｍのピッチで形成されている。In order to manufacture the semiconductor device of the third embodiment, first, as shown in FIG. 16, Al electrode pads 8 are formed on the entire surface of a semiconductor wafer 11 made of silicon (for example, diameter 6 inches, thickness 625 μm). After forming, the passivation film 10 having an opening at the center of the pad is formed thereon. The size of the electrode pads 8 is, for example, 80 μm square, and these electrode pads 8 are formed at a pitch of 120 μm in a region corresponding to the peripheral portion of each semiconductor chip (3 mm × 3 mm) formed in a later step. Has been done.

【００５６】そして、半導体ウェハ１１のＡｌ電極パッ
ド８上に、先端に小突起を有するボール状の金バンプ
（スタッドバンプ）９を、ワイヤボンダにより１個ずつ
形成する。金バンプ９の径は６０μｍ、高さは７０μｍ
とする。Then, on the Al electrode pad 8 of the semiconductor wafer 11, ball-shaped gold bumps (stud bumps) 9 having small protrusions at the tip are formed one by one by a wire bonder. Gold bump 9 has a diameter of 60 μm and a height of 70 μm
And

【００５７】また、図１７に示すように、ポリイミド樹
脂テープ、樹脂基板、セラミック基板などの絶縁基板１
の片面にＣｕの配線パッド２が設けられ、かつ配線パッ
ド２以外の領域にエポキシ樹脂等のソルダーレジスト層
５が形成された配線基板を用意し、その配線パッド２上
に、無電解めっきなどによりＮｉ層３とＡｕ層４を積層
して形成する。In addition, as shown in FIG. 17, an insulating substrate 1 such as a polyimide resin tape, a resin substrate, or a ceramic substrate is used.
A wiring board having a Cu wiring pad 2 provided on one side thereof and a solder resist layer 5 made of epoxy resin or the like formed on a region other than the wiring pad 2 is prepared, and the wiring pad 2 is electroless plated or the like. It is formed by stacking the Ni layer 3 and the Au layer 4.

【００５８】次いで、図１８に示すように、このＡｕ層
４の上に、異方性導電層２２を形成する。異方性導電層
２２は、絶縁性樹脂２３中に導電性粒子２４が混入され
た構造を有する。導電性粒子２４は、図１９に拡大して
示すように、フィラーからなるコア２５の周りに金属め
っき層２６が被覆された構造を有する。ここで、金属め
っき層２６としては、Ｃｕ、Ｎｉ、Ａｕ、Ｐｄ、Ａｇか
ら選ばれる金属のめっき層が挙げられる。これらの金属
層は単層としてもよいが、２層以上を積層することもで
きる。また、導電性粒子２４としては、フィラーを使用
せず、前記金属の粒子（５〜１０μｍ径）をそのまま混
入することもできる。Then, as shown in FIG. 18, an anisotropic conductive layer 22 is formed on the Au layer 4. The anisotropic conductive layer 22 has a structure in which conductive particles 24 are mixed in the insulating resin 23. As shown in an enlarged view in FIG. 19, the conductive particles 24 have a structure in which a metal plating layer 26 is coated around a core 25 made of a filler. Here, examples of the metal plating layer 26 include a metal plating layer selected from Cu, Ni, Au, Pd, and Ag. These metal layers may be a single layer, but two or more layers may be laminated. Further, as the conductive particles 24, it is also possible to mix the particles of the metal (5 to 10 μm diameter) as they are without using a filler.

【００５９】異方性導電層２２の形成は、異方性導電シ
ートを貼着する方法で、あるいは異方性導電ペーストを
塗布する方法で行われる。異方性導電シートは、シート
状に成形された絶縁性樹脂シート中に前記した導電性粒
子が混入された構造を有する。異方性導電ペーストは、
ペースト状の絶縁性樹脂中に前記した導電性粒子を混入
したものである。The anisotropic conductive layer 22 is formed by a method of attaching an anisotropic conductive sheet or a method of applying an anisotropic conductive paste. The anisotropic conductive sheet has a structure in which the above-mentioned conductive particles are mixed in a sheet-shaped insulating resin sheet. The anisotropic conductive paste is
It is a mixture of the above-mentioned conductive particles in a paste-like insulating resin.

【００６０】異方性導電シートを使用して異方性導電層
２２を形成する場合には、配線パッド２に相当する部分
に開口を設けるようにする。このとき、開口の径は、配
線パッドの径（８０μｍ）よりも小さくし、例えば５０
μｍとする。また、異方性導電ペーストを使用する場合
は、印刷マスク等を用いて、５０μｍ径の開口が得られ
るようにペーストを塗布する。When the anisotropic conductive layer 22 is formed by using the anisotropic conductive sheet, an opening is provided at a portion corresponding to the wiring pad 2. At this time, the diameter of the opening is made smaller than the diameter (80 μm) of the wiring pad, for example, 50
μm. When an anisotropic conductive paste is used, the paste is applied using a printing mask or the like so that an opening with a diameter of 50 μm can be obtained.

【００６１】次に、図２０に示すように、チップ側に形
成された金バンプ９の先端部が基板側のＡｕ層４の中央
部に当接するように、半導体チップ７と配線基板との位
置合わせを行い、熱圧着法、超音波併用熱圧着法などに
より接合を行う。Next, as shown in FIG. 20, the positions of the semiconductor chip 7 and the wiring board are set so that the tip portions of the gold bumps 9 formed on the chip side come into contact with the central portion of the Au layer 4 on the board side. They are joined together and joined by a thermocompression bonding method, a thermocompression bonding method using ultrasonic waves, or the like.

【００６２】熱圧着法では、例えば、２００度の温度で
１分間加熱して接合する。超音波併用熱圧着法では、２
００度の温度に加熱し、かつ超音波強度５Ｗで１秒間超
音波を印加し、バンプ１個当たり１００ｇの荷重をかけ
て接合を行う。In the thermocompression bonding method, for example, heating is carried out at a temperature of 200 ° C. for 1 minute to bond them. In the ultrasonic thermocompression bonding method, 2
Heating is performed at a temperature of 00 degrees, ultrasonic waves are applied at an ultrasonic wave intensity of 5 W for 1 second, and a load of 100 g per bump is applied to perform bonding.

【００６３】こうして、図２１に示すように、金バンプ
９の先端部と基板側のＡｕ層４との圧接部にＡｕ−Ａｕ
拡散接合部が形成される。また、金バンプ９の側周部
は、異方性導電層２２中の導電性粒子２４同士の接触に
より、基板側のＡｕ層４と接続される。Thus, as shown in FIG. 21, Au—Au is formed at the pressure contact portion between the tip of the gold bump 9 and the Au layer 4 on the substrate side.
A diffusion bond is formed. Further, the side peripheral portion of the gold bump 9 is connected to the Au layer 4 on the substrate side by the contact between the conductive particles 24 in the anisotropic conductive layer 22.

【００６４】こうして製造される第３の実施例の半導体
装置においては、パッドの中央部に金属同士の拡散によ
る接合（Ａｕ−Ａｕ拡散接合）が形成され、抵抗が低く
かつ強固な接続がなされる。また、パッドの周辺部に
は、異方性導電層２２中の導電性粒子２４同士の接触に
よる接合がなされ、かつ異方性導電層２２中の樹脂によ
る機械的接合もなされるので、前記したＡｕ−Ａｕ拡散
接合が補強され、より信頼性の高い接続部が得られる。In the semiconductor device of the third embodiment thus manufactured, a bond by diffusion of metals (Au-Au diffusion bond) is formed in the central part of the pad, so that the resistance is low and the connection is strong. . Further, in the peripheral portion of the pad, the conductive particles 24 in the anisotropic conductive layer 22 are bonded to each other by contact, and the resin in the anisotropic conductive layer 22 is also mechanically bonded. The Au-Au diffusion bonding is reinforced and a more reliable connection is obtained.

【００６５】実際に、前述の工程にしたがって製造され
た第３の実施例の半導体装置を、温度サイクル試験に供
して接続信頼性を調べた。なお、半導体チップ７として
５０個の金バンプが形成された３ｍｍ角のシリコンチッ
プを使用し、これをポリイミド樹脂基板上に実装して試
験サンプルとした。温度サイクル試験は、（−６５℃×
３０分）〜（２５℃×５分）〜（１５０℃×３０分）を
１サイクルとして行った。Actually, the semiconductor device of the third embodiment manufactured according to the above process was subjected to a temperature cycle test to examine the connection reliability. As the semiconductor chip 7, a 3 mm square silicon chip having 50 gold bumps formed thereon was used and mounted on a polyimide resin substrate to obtain a test sample. The temperature cycle test is (-65 ° C x
30 minutes) to (25 ° C x 5 minutes) to (150 ° C x 30 minutes) were performed as one cycle.

【００６６】温度サイクル試験の結果、３０００サイク
ル後でも接続箇所に破断の発生が認められなかった。さ
らに、バンプ間でのショートも発生しなかった。As a result of the temperature cycle test, no breakage was observed at the connection portion even after 3000 cycles. Furthermore, no short circuit occurred between the bumps.

【００６７】以上、本発明の実施例について説明した
が、本発明はこれらの実施例に限定されるものではな
く、例えば、金バンプとして、金ボール以外に金めっき
バンプや金ペーストの印刷によるバンプを用いることが
できる。またこれらのバンプにおいて、金（Ａｕ）に代
えて、Ｃｕ、Ｎｉ、Ｐｄ、Ａｇなどを用いてもよく、一
方はんだとしては、Ｓｎ−Ｐｂ以外のはんだであっても
よい。Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example, as gold bumps, bumps formed by printing gold plating bumps or gold paste in addition to gold balls. Can be used. In these bumps, Cu, Ni, Pd, Ag, or the like may be used instead of gold (Au), and the solder may be a solder other than Sn-Pb.

【００６８】さらに、このような接合部材中には、微量
のＯやＮが含有されていても差し支えなく、その他本発
明の主旨を逸脱しない範囲内で種々変更して実施するこ
とができる。Furthermore, a small amount of O or N may be contained in such a joining member, and various modifications may be made without departing from the scope of the present invention.

【００６９】[0069]

【発明の効果】以上の説明から明らかなように、本発明
の半導体装置では、半導体素子の電極端子と配線基板の
配線層とが、バンプを介した２種類以上の接合形態によ
り接続されているので、接合部の信頼性が向上する。ま
た、バンプのスタンドオフ効果により、電極端子間の短
絡防止や半導体素子と基板との間隔維持を実現すること
ができ、安定した信頼性の高いフリップチップ接続部が
得られる。As is apparent from the above description, in the semiconductor device of the present invention, the electrode terminals of the semiconductor element and the wiring layer of the wiring substrate are connected by two or more kinds of bonding forms via bumps. Therefore, the reliability of the joint is improved. Further, due to the standoff effect of the bumps, prevention of short circuit between the electrode terminals and maintenance of the distance between the semiconductor element and the substrate can be realized, and a stable and highly reliable flip chip connection portion can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図１】第１の実施例の半導体装置を示す断面図。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment.

【図２】第１の実施例の半導体装置の製造方法を説明す
るための断面図。FIG. 2 is a sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.

【図３】第１の実施例の半導体装置の製造方法を説明す
るための断面図。FIG. 3 is a sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.

【図４】第１の実施例の半導体装置の製造方法を説明す
るための断面図。FIG. 4 is a sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment.

【図５】第１の実施例の半導体装置の製造方法を示し、
（ａ）は断面図、（ｂ）ははんだ層の上面図。FIG. 5 shows a method of manufacturing the semiconductor device of the first embodiment,
(A) is sectional drawing, (b) is a top view of a solder layer.

【図６】第１の実施例の半導体装置の製造方法を説明す
るための断面図。FIG. 6 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

【図７】第１の実施例の半導体装置の製造方法を説明す
るための断面図。FIG. 7 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

【図８】第２の実施例の半導体装置の製造方法を説明す
るための断面図。FIG. 8 is a sectional view for explaining the method for manufacturing the semiconductor device of the second embodiment.

【図９】第２の実施例の半導体装置の製造方法を説明す
るための断面図。FIG. 9 is a cross-sectional view for explaining the method for manufacturing the semiconductor device of the second embodiment.

【図１０】第２の実施例の半導体装置の製造方法を説明
するための断面図。FIG. 10 is a sectional view for explaining the manufacturing method for the semiconductor device according to the second embodiment.

【図１１】第２の実施例の半導体装置の製造方法を説明
するための断面図。FIG. 11 is a sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment.

【図１２】第２の実施例の半導体装置の製造方法を説明
するための断面図。FIG. 12 is a sectional view for explaining the manufacturing method for the semiconductor device according to the second embodiment.

【図１３】第２の実施例の半導体装置の製造方法を説明
するための断面図。FIG. 13 is a sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment.

【図１４】第２の実施例の半導体装置の製造方法を説明
するための断面図。FIG. 14 is a sectional view for explaining the manufacturing method for the semiconductor device according to the second embodiment.

【図１５】第２の実施例の半導体装置を示す断面図。FIG. 15 is a sectional view showing a semiconductor device according to a second embodiment.

【図１６】第３の実施例の半導体装置の製造方法を説明
するための断面図。FIG. 16 is a sectional view for explaining the method for manufacturing the semiconductor device of the third embodiment.

【図１７】第３の実施例の半導体装置の製造方法を説明
するための断面図。FIG. 17 is a sectional view for explaining the manufacturing method for the semiconductor device according to the third embodiment.

【図１８】第３の実施例の半導体装置の製造方法を説明
するための断面図。FIG. 18 is a sectional view for explaining the manufacturing method for the semiconductor device according to the third embodiment.

【図１９】第３の実施例の半導体装置の製造方法を説明
するための断面図。FIG. 19 is a sectional view for explaining the manufacturing method for the semiconductor device according to the third embodiment.

【図２０】第３の実施例の半導体装置の製造方法を説明
するための断面図。FIG. 20 is a sectional view for explaining the manufacturing method for the semiconductor device according to the third embodiment.

【図２１】第３の実施例の半導体装置を示す断面図。FIG. 21 is a sectional view showing a semiconductor device according to a third embodiment.

【図２２】従来のフリップチップ接続部の構造を示す断
面図。FIG. 22 is a cross-sectional view showing the structure of a conventional flip chip connection part.

【符号の説明】[Explanation of symbols]

１………絶縁基板、２………配線パッド、４………Ａｕ
層、６………はんだ層、７………半導体チップ、８……
…Ａｌ電極パッド、９………金バンプ、１２、１８……
…レジスト層、２０………はんだバンプ、２１………は
んだ融着層、２２………異方性導電層、２３………導電
性粒子1 ... Insulation substrate, 2 ... Wiring pad, 4 ... Au
Layer, 6 ... Solder layer, 7 Semiconductor chip, 8
... Al electrode pads, 9 ... Gold bumps, 12, 18 ...
... resist layer, 20 ... solder bump, 21 ... solder fusion layer, 22 ... anisotropic conductive layer, 23 ... conductive particles

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 3/34 ５０１ Ｈ０１Ｌ 21/92 ６０２Ｃ Ｆターム(参考） 5E319 AA03 AB06 AC02 AC03 AC04 AC17 BB04 BB16 BB20 CC12 CC33 CC61 CD04 CD26 CD29 GG03 5E336 AA04 BB12 BB15 BB18 BC28 CC31 CC58 EE03 EE05 EE08 GG06 5F044 KK01 LL04 LL07 LL09 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H05K 3/34 501 H01L 21/92 602C F term (reference) 5E319 AA03 AB06 AC02 AC03 AC04 AC17 BB04 BB16 BB20 CC12 CC33 CC61 CD04 CD26 CD29 GG03 5E336 AA04 BB12 BB15 BB18 BC28 CC31 CC58 EE03 EE05 EE08 GG06 5F044 KK01 LL04 LL07 LL09

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 絶縁基板の少なくとも一方の主面に配線
層が形成された配線基板と、 前記配線基板の配線層形成面上にフェースダウンに搭載
された半導体素子と、 前記半導体素子の電極端子と前記配線基板の配線層の少
なくとも一方の上に形成されたバンプを備え、 前記半導体素子の電極端子と前記配線基板の配線層と
が、前記バンプを介する２種類以上の接合形態により接
続されていることを特徴とする半導体装置。1. A wiring board having a wiring layer formed on at least one main surface of an insulating substrate, a semiconductor element mounted facedown on the wiring layer formation surface of the wiring board, and electrode terminals of the semiconductor element. And a bump formed on at least one of the wiring layers of the wiring board, wherein the electrode terminals of the semiconductor element and the wiring layer of the wiring board are connected by two or more kinds of bonding forms via the bumps. A semiconductor device characterized in that 【請求項２】 前記バンプを介する接合形態が、はんだ
同士の溶融による接合、はんだとそれに濡れる金属との
溶融による接合、同種または異種の金属相互の拡散また
は圧接による接合、導電性粒子同士の接触による接合か
ら選ばれる２種類以上の接合形態であることを特徴とす
る請求項１記載の半導体装置。2. The form of joining via the bumps includes joining by melting of solders, joining by melting of solder and a metal wettable thereto, joining by diffusion or pressure welding of the same or different kinds of metal, and contact between conductive particles. 2. The semiconductor device according to claim 1, wherein the semiconductor device has two or more kinds of bonding forms selected from the bonding according to. 【請求項３】 前記はんだ同士の溶融による接合が、Ｓ
ｎ、Ｐｂ、Ａｇ、Ｂｉ、Ｚｎ、Ｉｎ、Ｓｂ、Ｃｕ、Ｇｅ
の金属単独、これらの金属の混合物または化合物から選
ばれるはんだの１種または２種以上の溶融による接合で
あることを特徴とする請求項２記載の半導体装置。3. The joining by melting of the solders is S
n, Pb, Ag, Bi, Zn, In, Sb, Cu, Ge
3. The semiconductor device according to claim 2, wherein the joining is performed by melting one type or two or more types of solder selected from the above metals alone or a mixture or compound of these metals. 【請求項４】 前記はんだとそれに濡れる金属との溶融
による接合が、Ｓｎ、Ｐｂ、Ａｇ、Ｂｉ、Ｚｎ、Ｉｎ、
Ｓｂ、Ｃｕ、Ｇｅの金属単独、これらの金属の混合物ま
たは化合物から選ばれるはんだと、Ｃｕ、Ｎｉ、Ａｕ、
Ｐｄ、Ａｇから選ばれるはんだに濡れる金属との間の、
前記はんだの溶融による接合であることを特徴とする請
求項２記載の半導体装置。4. The joining of the solder and the metal that wets it by melting is Sn, Pb, Ag, Bi, Zn, In,
Sb, Cu, Ge metal alone, a solder selected from a mixture or compound of these metals, and Cu, Ni, Au,
Between a metal wettable with solder selected from Pd and Ag,
The semiconductor device according to claim 2, wherein the connection is made by melting the solder. 【請求項５】 前記同種または異種の金属相互の拡散ま
たは圧接による接合が、Ｃｕ，Ｎｉ、Ａｕ、Ｐｄ、Ｗ、
Ｔｉ、Ｃｒ、ＴｉＮ、Ｔａ、ＴａＮ、Ｎｂ、Ｆｅ、Ａｇ
の単独、これらの混合物または化合物から選ばれる金属
の１種または２種以上の間の拡散または接触による接合
であることを特徴とする請求項２記載の半導体装置。5. The bonding by diffusion or pressure welding of the same or different metals is performed by Cu, Ni, Au, Pd, W,
Ti, Cr, TiN, Ta, TaN, Nb, Fe, Ag
3. The semiconductor device according to claim 2, which is a junction by diffusion or contact between one or two or more kinds of metals selected from the group consisting of the above, a mixture or a compound thereof. 【請求項６】 前記導電性粒子同士の接触による接合
が、異方性導電材料中のＡｕ、Ｎｉ、Ｐｄ、Ｃｕ、Ａｇ
から選ばれる１種または２種以上の金属を含む粒子相互
の接触による接合であることを特徴とする請求項２記載
の半導体装置。6. The bonding of the conductive particles to each other is carried out by Au, Ni, Pd, Cu, Ag in the anisotropic conductive material.
The semiconductor device according to claim 2, wherein the bonding is performed by mutual contact between particles containing one or more metals selected from the group consisting of:
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