JPS6380553A - Ic package - Google Patents

Ic package

Info

Publication number
JPS6380553A
JPS6380553A JP61226783A JP22678386A JPS6380553A JP S6380553 A JPS6380553 A JP S6380553A JP 61226783 A JP61226783 A JP 61226783A JP 22678386 A JP22678386 A JP 22678386A JP S6380553 A JPS6380553 A JP S6380553A
Authority
JP
Japan
Prior art keywords
cap
chip
grid array
pin grid
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61226783A
Other languages
Japanese (ja)
Inventor
Toshio Maeda
前田　利夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61226783A priority Critical patent/JPS6380553A/en
Publication of JPS6380553A publication Critical patent/JPS6380553A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To associate an IC chip of large area by inserting a pin grid array to a cap part, and providing a structure that the inserted pin grid array terminal and a body on which an IC chip is mounted are easily electrically connected. CONSTITUTION:An IC chip 5 is secured to a heat sink 1 in the state that a cap 2 is removed, the chip 5 is bonded to a body 6, and the body 6 is sealed to the cap 2 by a sealing material 3. Gold-plated printed wirings are formed on the contacting surfaces of the body 6 with the cap 2, the body 6 and the cap 2 are associated, sealed by the sealing material to easily electrically connect both, and the signal of the terminal of the chip 5 can be produced to the pin grid array terminal. Thus, the size of the IC to be mounted is not limited by the cap having a limited size by a terminal position.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＩＣチップを封入するＩＣパッケージに関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC package that encapsulates an IC chip.

〔従来の技術〕[Conventional technology]

従来ヒートシンク付ピングリッドアレイＩＣパッケージ
は第２図に断面図で示すようにキャップ１１をはずした
状態でＩＣチップ１０をヒートシンク７に固定し、その
後キャップ１１で封止する構造となっていた。A conventional pin grid array IC package with a heat sink has a structure in which the IC chip 10 is fixed to the heat sink 7 with the cap 11 removed, and then sealed with the cap 11, as shown in a cross-sectional view in FIG.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のヒートシンク付ピングリッドアレイＩＣ
パッケージはその実装可能なＩＣの大きさが、端子位置
によって制限された大きさをもつキャップにより制限さ
れるという欠点があった。The above-mentioned conventional pin grid array IC with heat sink
The package has the disadvantage that the size of the IC that can be mounted is limited by the cap, which has a size limited by the terminal position.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のピングリッドアレイＩＣパッケージはａ、ヒー
トシンク部を持ったＩＣパッケージ本体と、ｂピングリ
ッドアレイの実装されたキャップとＣ１ＩＣパッケージ
本体上に実装されたＩＣナツプの端子とキャップに実装
されたピングリッドアレイ端子間を容易に電気的に接続
出来る構造とを有している。The pin grid array IC package of the present invention consists of (a) an IC package body having a heat sink part, (b) a cap on which the pin grid array is mounted, and (C) terminals of an IC nap mounted on the IC package body and pins mounted on the cap. It has a structure that allows easy electrical connection between grid array terminals.

〔実施例〕〔Example〕

次に本発明について図閘を参照して説明する。 Next, the present invention will be explained with reference to the drawing board.

第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.

ＩＣチップ５はキャップ２を取り外した状態でヒ−トシ
ンク１に固定され、ＩＣチップ５が本体６とボンディン
グされた後、本体６とキャップ２が封止材３によって封
止される。又、本体６及びキャップ２の接触面には各々
金メッキされた印刷配線がされておシ、本体６とキャッ
プ２とを組合わせ、封止材ｐｃよシ封止することによシ
両者間の電気的接続が容易に実現でき、ＩＣチップ５の
端子の信号をピングリッドアレイ端子に取シ出すことが
出来る。The IC chip 5 is fixed to the heat sink 1 with the cap 2 removed, and after the IC chip 5 is bonded to the main body 6, the main body 6 and the cap 2 are sealed with the sealant 3. In addition, the contact surfaces of the main body 6 and the cap 2 are each provided with gold-plated printed wiring, and by combining the main body 6 and the cap 2 and sealing them with the sealing material PC, there is no connection between the two. Electrical connection can be easily realized, and signals from the terminals of the IC chip 5 can be taken out to the pin grid array terminals.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、キャップにピングリッド
アレイ端子を植込む事によシ、キャップの大きさて制限
を受けず大面積のＩＣチップをヒートシンク付ピングリ
ッドアレイＩＣパッケージに組込むことができる効果が
ある。As explained above, the present invention has the effect that by implanting pin grid array terminals in the cap, a large-area IC chip can be incorporated into a pin grid array IC package with a heat sink without being limited by the size of the cap. There is.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明のヒートシンク付ピングリッドアレイＩ
Ｃパッケージの縦断面図、第２図は従来のヒートシンク
付ピングリッドアレイＩＣパッケージの縦断面図である
。 １・・・・・・ヒートシンク、２・・・・・・キャップ
、３・・・・・・封止材、４・・・・・・ピングリッド
アレイ端子、５・・・・・・ＩＣチップ、６・・・・・
・本体、７・・・・・・ヒートシンク、８・・・・・・
本体、９・・・・・・ピングリッドアレイ端子、１０・
・・・・・ＩＣチップ、１１・・・・・・キャップ。 −ゝ＼Figure 1 shows a pin grid array I with a heat sink of the present invention.
FIG. 2 is a vertical cross-sectional view of a conventional pin grid array IC package with a heat sink. 1... heat sink, 2... cap, 3... sealing material, 4... pin grid array terminal, 5... IC chip , 6...
・Main body, 7...Heat sink, 8...
Main body, 9...Pin grid array terminal, 10.
...IC chip, 11...cap. −ゝ＼

Claims (1)

【特許請求の範囲】[Claims] １、キャップ部分にピングリッドアレイ端子を植込み、
この植込まれたピングリッドアレイ端子と、ＩＣチップ
の装着された本体との間を容易に電気的に接続できる構
造を有することを特徴とするヒートシンク付のピングリ
ッドアレイＩＣパッケージ。1. Insert the pin grid array terminal into the cap part,
A pin grid array IC package with a heat sink, characterized in that it has a structure that allows easy electrical connection between the implanted pin grid array terminal and a main body on which an IC chip is mounted.
JP61226783A 1986-09-24 1986-09-24 Ic package Pending JPS6380553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61226783A JPS6380553A (en) 1986-09-24 1986-09-24 Ic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61226783A JPS6380553A (en) 1986-09-24 1986-09-24 Ic package

Publications (1)

Publication Number Publication Date
JPS6380553A true JPS6380553A (en) 1988-04-11

Family

ID=16850543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61226783A Pending JPS6380553A (en) 1986-09-24 1986-09-24 Ic package

Country Status (1)

Country Link
JP (1) JPS6380553A (en)

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