JPS6379422A - Digital-analog converter - Google Patents
Digital-analog converterInfo
- Publication number
- JPS6379422A JPS6379422A JP22537186A JP22537186A JPS6379422A JP S6379422 A JPS6379422 A JP S6379422A JP 22537186 A JP22537186 A JP 22537186A JP 22537186 A JP22537186 A JP 22537186A JP S6379422 A JPS6379422 A JP S6379422A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- terminal
- output
- current
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000004044 response Effects 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 8
- 230000003321 amplification Effects 0.000 abstract 2
- 238000003199 nucleic acid amplification method Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 5
- 230000032683 aging Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 102220067365 rs143592561 Human genes 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
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- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＤ／Ａ変換器の改良に関するもので、さらに詳
しくはＭＯＳ ＦＥＴを使用した電流出力型Ｄ／Ａ変換
器の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in D/A converters, and more particularly to improvements in current output type D/A converters using MOS FETs.
第３図は、従来良く知られたＤ／Ａ変換器の一例である
。第３図において、１は第１のアナログ端子工０，２は
第２のアナログ出力端子Ｉｏ、 ３は基準電圧ＶＲＥｒ
が印加される基準電圧端子、４は電源ＶＤＤが印加され
る電源端子、５は抵抗性素子Ｒ１〜Ｒ４より成り、電源
端子４ニジ流れ込んでくる電流よシ複数の重み付け電流
を発生する抵抗網、Ｍｌｌ〜Ｍ１４は、抵抗網５の重み
付け電流の出力端子を一定電圧に安定化する為のＦＥＴ
、Ｍ２１〜Ｍ２３．Ｍ３１〜Ｍ３３はＭｌｌ〜Ｍ１３よ
り流れ込んでくる重み付け電流を工０又は工０のいずれ
かに導びく、スイッチ用ＦＥＴ、Ｄｉ〜Ｄ３はデジタル
入力端子、６はＤ１〜Ｄ３に印加されるデジタル入力信
号に応じてＦＥＴ、Ｍ２１〜Ｍ２３．Ｍ３１〜Ｍ３３を
制御する信号１ａ〜３ａ、１ｂ〜３ｂを発生する回路で
ある。FIG. 3 shows an example of a conventionally well-known D/A converter. In FIG. 3, 1 is the first analog terminal 0, 2 is the second analog output terminal Io, and 3 is the reference voltage VRer.
4 is a power supply terminal to which the power supply VDD is applied; 5 is a resistor network consisting of resistive elements R1 to R4 and generating a plurality of weighted currents according to the current flowing into the power supply terminal 4; Mll to M14 are FETs for stabilizing the output terminal of the weighted current of the resistance network 5 to a constant voltage.
, M21-M23. M31 to M33 are switch FETs that guide the weighted current flowing in from Mll to M13 to either 0 or 0, Di to D3 are digital input terminals, and 6 is a digital input signal applied to D1 to D3. Depending on the FET, M21 to M23. This circuit generates signals 1a to 3a and 1b to 3b that control M31 to M33.
同図において、Ｒ１−Ｒ４は
Ｍｌｌ〜Ｍ１４は、Ｒ１−Ｒ４の両端にかかる電圧が、
一定値
Ｖｎ＝Ｖｎｎ−ＶＲＢＦ−Ｖａｓｔ（ｉ＝ｌ〜４）
−−・（１）但しＶａｓｔはＭｌｉのゲートソース間電
圧となるように大きさが決定されている。従って同Ｒ
図中ではＩ＝Ｔとすると、Ｒ１には４Ｉ、 ＲｚＶｃ
は２Ｉ。In the same figure, R1-R4 is Mll to M14, and the voltage applied across R1-R4 is
Constant value Vn=Vnn-VRBF-Vast (i=l~4)
--(1) However, the magnitude of Vast is determined so that it becomes the gate-source voltage of Mli. Therefore, if I=T in the same R diagram, R1 has 4I, RzVc
is 2I.
Ｒ３とＲ４には工の大きさの電流が流れることになる。A current of a magnitude of 1.5 mm will flow through R3 and R4.
第４図は制御回路６の論理例である。第４図中コントロ
ール出力の１は、その出力がゲートに接続され九ＦＥＴ
が導通する事を表わし、０は遮断する事を表わし、０は
遮断する事を表わす。例えばデジタル入力信号がＤ１＝
Ｏ，Ｄ２＝Ｄ３＝１の場合、第４図からＭ２１．Ｍ３２
．Ｍ３３が導通し、ＭＢ２゜Ｍ２２．Ｍ２３が遮断する
ことがわかる。この結果、ＩｏＫは３ｘＩの電流が流れ
、ＩＯには４ｘＩの大きさの電流が流れて、デジタル入
力信号がアナログの電流に変換される。デジタル入力信
号が異なった条件の場合にも、第４図の論理に従って各
ＦＥＴが導通、遮断を行い、同様にしてデジタルアナロ
グ変換が行表われる。以上述べたように第３図の条例に
おいて、デジタルアナログ変換が達成されることが理解
された。又、第３図の回路は、その構成要素が抵抗、Ｆ
ＥＴ、デジタル回路よ構成っていることと、 ＶＤｇｐ
電圧さえ外部で調節すれば、それらの素子の相対精度に
のみ、出力の精度が左右されるという２つの理由によシ
、極めて集積回路化に達している。FIG. 4 is a logic example of the control circuit 6. Control output 1 in Fig. 4 has its output connected to the gate of 9 FETs.
represents conduction, 0 represents disconnection, and 0 represents disconnection. For example, if the digital input signal is D1=
If O, D2=D3=1, from FIG. 4 M21. M32
．． M33 conducts, MB2°M22. It can be seen that M23 is blocked. As a result, a current of 3xI flows through IoK, a current of 4xI flows through IO, and the digital input signal is converted into an analog current. Even when the digital input signal is under different conditions, each FET conducts conduction or disconnection according to the logic shown in FIG. 4, and digital-to-analog conversion is performed in the same manner. As described above, it was understood that digital-to-analog conversion is achieved in the regulations shown in Figure 3. In addition, the circuit shown in Fig. 3 has a resistor, F
ET is composed of a digital circuit, and VDgp
Even if the voltage is adjusted externally, the accuracy of the output depends only on the relative accuracy of those elements, for two reasons: highly integrated circuits have been reached.
ところで、上述したように、従来のＤ／Ａ変換器におい
ては、その重み付け電流をＲ１−Ｒ４より成る抵抗網の
出力端をＭｌｌ〜Ｍ１４よ構成るＦＥＴによって定電圧
化して得る。従って（１）式中のＶａｓｔ（？ｖ！ｐ＋
のゲートソース間１！圧）はＭｌｌ〜Ｍ１４において一
致することが必要であるが、前述したとおシ各ＦＥＴを
流れる電流は４：２：１：１の比になりている。ＦＥＴ
が流すことが可能な電流値はゲートソース間電圧が一定
の場合、その物理的形状で決まってしまうので、この場
合ＭｌｌにはＭ１４の４倍の形状のものが、Ｍ１２には
Ｍ１４の２倍の形状のものが使用される。実際には、こ
れらのＦＥＴの相対性を良好とする為、ＭｌｌはＭ１４
と同一のものを４つ並列に、Ｍ１２はＭ１４と同一のも
のを２つ並列に使用することが多い。第３図の従来例は
３ｂｉｔのＤ／Ａ変換器の例であるが、この型のＤ／Ａ
変換器はｂｉｔ数が上昇するにつれて、抵抗網の重み付
け電流の比は２のべき乗で変化するので、このＦ Ｅ
’Ｉｔ”の回路全体に対して占める割合も蓄しく大きく
なってゆくという欠点を持っている。又Ｖｏｓ＋の差を
産む他の要因としてＭｌｉのＩ” Ｅ Ｔの閾値Ｖｒの
変動が存在する。通常ＦＥＴにおいてはこの変動は数ｍ
Ｖである。By the way, as described above, in the conventional D/A converter, the weighting current is obtained by making the output terminal of the resistor network composed of R1-R4 a constant voltage by the FETs composed of Mll-M14. Therefore, Vast(?v!p+
Between the gate sources 1! It is necessary that the voltages (voltages) are the same in Mll to M14, but as described above, the currents flowing through each FET are in a ratio of 4:2:1:1. FET
The current value that can flow is determined by its physical shape when the gate-source voltage is constant, so in this case, Mll has a shape four times that of M14, and M12 has a shape twice that of M14. A shape of is used. Actually, in order to make the relativity of these FETs good, Mll is M14.
Four pieces identical to M12 are often used in parallel, and two pieces identical to M14 are used in parallel for M12. The conventional example in Fig. 3 is an example of a 3-bit D/A converter;
In the converter, as the bit number increases, the weighting current ratio of the resistor network changes by a power of 2, so this F E
It has the disadvantage that the ratio of 'It' to the entire circuit increases rapidly.Furthermore, another factor that causes a difference in Vos+ is the fluctuation of the threshold value Vr of I'ET of Mli. In normal FETs, this fluctuation is several meters
It is V.
もし仮に■＝ＩＶとすると、１３ ｂｉｔのＤ／Ａを第
３図の従来例と同じ方法で実現するとし、最上位のＰＥ
ＴのＶｒの変動が１０ｍｖ存在した場合、最下位の重み
付け電流Ｉ＝青に対して、最上位の重み付け電流は
となシ、ｖｒの変動による最上位の重み付け電流の変動
が最下位の重み付け電流を越えてしまうととがわかる。If ■ = IV, 13-bit D/A is realized using the same method as the conventional example shown in Fig. 3, and the top PE
If there is a variation of Vr of T by 10 mV, the lowest weighted current I = blue, the highest weighted current will be the same, and the fluctuation of the highest weighted current due to the fluctuation of vr will be the lowest weighted current. If you exceed this, you will understand.
このような変動はデジタル、アナログ変換の誤差となっ
て表われ好ましくない。又、ＦＥＴ、Ｍｌｉの単位大き
さあたりの電流駆動能力幻も変動し、この変動もやはり
Ｖａｓｔの変動を生じ、同様にデジタル、アナログ変換
の結果に誤差となって表われる。そのため、一般にはこ
のような変動は抵抗網を構成する抵抗をトリミングする
事により取り除かれているが、’Ｖ’ｒ＋には温度特性
や経時変化も持つ為、完全には調節できないという欠点
も持っていた。Such fluctuations appear as errors in digital/analog conversion and are undesirable. Furthermore, the current drive capability per unit size of the FET and Mli also varies, and this variation also causes a variation in Vast, which similarly appears as an error in the results of digital and analog conversion. Therefore, such fluctuations are generally removed by trimming the resistors that make up the resistor network, but 'V'r+ also has temperature characteristics and changes over time, so it has the disadvantage that it cannot be completely adjusted. was.
上述した従来のＤ／Ａ変換器のＦＥＴのゲートソース間
電圧による定電圧化の方法に対し、本発明のＤ／Ａ変換
器は、抵抗網の一端の電圧と基準電圧とを差動増幅器に
よシ比較し、その結果で抵抗網の重み付け電流の出力端
につながれたＦＥＴのゲート電圧を制御することで定電
圧化をはかるもので、従来例Ｃ（おいて問題となったＦ
ＥＴの占有面積の増大や温度変化や経時変化によるＦＥ
Ｔの閾値変動、駆動能力の変動を問題としない、優れた
Ｄ／Ａ変換器が提供できるという独創的内容を有する。In contrast to the conventional D/A converter described above, in which the voltage is made constant by the gate-source voltage of the FET, the D/A converter of the present invention uses a differential amplifier to connect the voltage at one end of the resistor network and the reference voltage. By comparing the results, the gate voltage of the FET connected to the output terminal of the weighted current of the resistor network is controlled to achieve a constant voltage.
FE caused by an increase in the area occupied by ET, temperature changes, and changes over time.
The invention has an original content in that it can provide an excellent D/A converter that does not have problems with T threshold fluctuations and driving capability fluctuations.
かかる独創的内容を有する本発明のＤ／Ａ変換器とは、
デジタル入力端子と、第１のアナログ出力端子と第２の
アナログ出力端子と基準電圧端子と、複数の重み付け電
流を発生する抵抗網と、前記抵抗網の重み付け電流の出
力端子におのおのソースを接続した第１のＦＥＴ群中の
おのおののＦＥＴのソースに第１の入力端子を接続し、
第２の入力端子を前記基準電圧端子に接続し、出力端子
をおのおののＦＥＴのゲートに接続した差動増幅器群と
前記第１のＦＥＴ群中のおのおののＦＥＴのドレインに
おのおののソースを接続し、ドレインを前記第１のアナ
ログ出力端子に接続した第２のＦＥＴ群と、前記第１の
ＦＥＴ群中のおのおののＦＥＴのドレインにおのおのの
ソースを接続し、ドレインを前記第２のアナログ出力端
子に接続した第３のＦＥＴ群と、前記デジタル入力端子
に印加されたデジタル入力信号に対応して前記第２のＦ
ＥＴ群及び第３のＦＥＴ群のＦＥＴのゲート電圧を制御
する回路とから成ることを特徴とするＤ／Ａ変換器であ
る。The D/A converter of the present invention having such original content is as follows:
A digital input terminal, a first analog output terminal, a second analog output terminal, a reference voltage terminal, a resistor network that generates a plurality of weighted currents, and a source connected to each of the weighted current output terminals of the resistor network. connecting a first input terminal to the source of each FET in the first FET group;
A differential amplifier group having a second input terminal connected to the reference voltage terminal and an output terminal connected to the gate of each FET, and each source connected to the drain of each FET in the first FET group. , a second group of FETs whose drains are connected to the first analog output terminal, and a source of which is connected to the drain of each FET in the first group of FETs, whose drains are connected to the second analog output terminal. and a third FET group connected to the second FET group in response to a digital input signal applied to the digital input terminal.
This is a D/A converter characterized by comprising an ET group and a circuit for controlling gate voltages of FETs of a third FET group.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明のＤ／Ａ変換器の一実施例である。第１
図において１はアナログ出力端子ＩＯ２２は第２のアナ
ログ出力端子工０，３は基準電圧ＶＤＫＦが印加される
基準電圧端子、４は電源ＶＤＤが印加される電源端子、
５は抵抗性素子Ｒ１〜Ｒ４よ構成シ、電源端子４よシ流
れ込んでくる電流から複数の重み付け電流を発生する抵
抗網、ＡｉとＭｌｉ（ｉ＝１〜４）は、抵抗網５の重み
付け電流の出力端子をＶＲＢＦに定電圧化する為の差動
増幅器とＦＥＴ、Ｍ２１〜Ｍ２３．Ｍ３１〜Ｎ■３３は
Ｍｌｌ〜Ｍ１３より流れ込む重み付け電流を工０又はＩ
ｏのいずれかに導びくスイッチ用ＦＥＴ、ＤＩ〜Ｄ３は
デジタル入力端子、６はＤ１〜Ｄ３に印加されるデジタ
ル入力信号に応じてＦＥＴ、Ｍ２１〜Ｍ２３．Ｍ３１〜
Ｍ３３を制御する信号、１ａ〜３ａ、 １ｂ〜３ｂを発
生する回路である。同図においてＲ１−Ｒ４は
几４＝Ｒ３＝几、Ｒ２＝旦、Ｒ１＝旦に設定されており
、前述のとおりＲ１−Ｒ４の一端にはＶＤＤが残る一端
にＢ ＶＲＥＦ 力印加すｈテイル。従ッテ￥１＝Ｖｎ
ｎ−ＶｎｇＰ。FIG. 1 shows an embodiment of the D/A converter of the present invention. 1st
In the figure, 1 is an analog output terminal IO22 is a second analog output terminal; 0 and 3 are reference voltage terminals to which a reference voltage VDKF is applied; 4 is a power supply terminal to which a power supply VDD is applied;
5 is a resistance network composed of resistive elements R1 to R4 and generates a plurality of weighted currents from the current flowing into the power supply terminal 4; Ai and Mli (i=1 to 4) are weighted currents of the resistance network 5; A differential amplifier and FET, M21 to M23. M31 to N33 are the weighting currents flowing from Mll to M13.
o, DI to D3 are digital input terminals, and 6 is a FET that leads to one of the FETs M21 to M23 . M31~
This circuit generates signals 1a to 3a and 1b to 3b that control M33. In the figure, R1-R4 are set to 4=R3=3, R2=1, and R1=1, and as mentioned above, VDD is applied to one end of R1-R4, and the B VREF force is applied to the other end. Jutte ¥1=Vn
n-VngP.
ＶＲ’
工′二ＴとするとＲ１には４Ｉ／、 Ｒ２には２Ｉ’、
Ｒ，とＲ４には工′の大きさの電流が流れることにな
る。制御回路６の論理は従来例と同様に第４図で表わさ
れる。この結果第１図の実施例の回路でも従来例と同様
に、デジタル、アナログ変換が達成されることが容易に
理解できる。VR' Engineering '2 T, then 4I/ for R1, 2I' for R2,
A current with a magnitude of 100 Ω will flow through R and R4. The logic of the control circuit 6 is shown in FIG. 4 as in the conventional example. As a result, it can be easily understood that digital-to-analog conversion can be achieved in the circuit of the embodiment shown in FIG. 1 as well as in the conventional example.
ところで、本実施例のＤ／Ａ変換器においては、抵抗網
の重み付け電流出力端は、出力端電圧と基準電圧を入力
とし、出力をその重み付け電流出力端に直列に接続した
ＦＥＴのゲートに接続した差動増幅器により定電圧化さ
れているので、従来例のようにＦＥＴに流れる電流の密
度が異っても差動増幅器によシ帰還がかかる為、抵抗網
の出力端子の電圧が変化することはないため、ＦＥＴの
大きさを調節する必要がなくＤ／Ａ変換のｂｉｔ数が上
がっても、従来例のようにＦＥＴに変換器の大半を占有
されるという事は生じない。又、温度特性や経時変化に
よｆｉＦＥＴのＶＴ−？Ｋが変化してもやはり差動増幅
器によυ帰還がかかつて補正される為、非常に安定なり
／Ａ変換器を構成できる。By the way, in the D/A converter of this embodiment, the weighted current output terminal of the resistor network is connected to the gate of the FET which receives the output terminal voltage and the reference voltage and whose output is connected in series to the weighted current output terminal. Since the voltage is regulated by a differential amplifier, even if the density of the current flowing through the FET differs as in the conventional example, feedback is applied to the differential amplifier, so the voltage at the output terminal of the resistor network changes. Therefore, there is no need to adjust the size of the FET, and even if the number of D/A conversion bits increases, the FET will not occupy most of the converter as in the conventional example. Also, depending on temperature characteristics and changes over time, the fiFET's VT-? Even if K changes, the υ feedback is once again corrected by the differential amplifier, so a very stable /A converter can be constructed.
本実施例において、唯一精度や経時変化が問題となるの
は差動増幅器であるが、この差動増幅器は前述の説明か
らその目的が各電流出力端の電位の安定化であるため、
直流的な利得さえ有れば良く、その応答速度は遅いもの
で十分であるとわかる。このような差動増幅器としては
、例えばチョッパー型増幅器が周知である。（例えば、
ＩＥＥＥＪＯＵＲＮＡＬ ＯＦ ８０ＬＩＤ−８ＴＡＴ
Ｅ ＣＩＲＣＵＩＴＳＶＯＬ、５Ｃ−１４，Ｎｏ、６．
ＤＥＣＥＭＢＥＲ１９７９゜Ｐ９１２〜９２０中にその
ような増幅器を比較回路に適応した例があるＱ一般Ｋ、
チョッパ型増幅器は、自己校正機能を有するので、素子
に対する精度の要求が緩く、又経時変化にも強い。さら
に集積回路化した場合、デバイスプロセスの進歩による
微細化の恩恵も受けやすい。チョッパ型増幅器は比較的
少数の素子（約１０素子）で構成することも可能なため
、例えば８ｂｉｔの場合、８０素子程度となるが、従来
例では２５６個ものＦＥＴが必要である事と比較すると
大幅な素子数の低減もはかられたことがわかる。In this embodiment, the only problem is the accuracy and aging of the differential amplifier, but as explained above, the purpose of this differential amplifier is to stabilize the potential at each current output terminal.
It turns out that it is sufficient to have a direct current gain, and a slow response speed is sufficient. As such a differential amplifier, for example, a chopper type amplifier is well known. (for example,
IEEEJOURNAL OF 80LID-8TAT
E CIRCUITS VOL, 5C-14, No, 6.
There is an example of applying such an amplifier to a comparator circuit in DECEMBER 1979゜P912-920.
Since the chopper type amplifier has a self-calibration function, the accuracy requirements for the elements are relaxed and it is resistant to changes over time. Furthermore, when integrated circuits are implemented, they are likely to benefit from miniaturization due to advances in device processes. Chopper type amplifiers can be constructed with a relatively small number of elements (approximately 10 elements), so for example, in the case of 8 bits, it is about 80 elements, but compared to the conventional example, which requires as many as 256 FETs. It can be seen that a significant reduction in the number of elements was achieved.
第２図は本発明の第１図とは異なった実施例である。第
２図において１は第１のアナログ出力端子工０，２は第
２のアナログ出力端子■０，３は基準電圧ＶＲＥＦが印
加される基準電圧端子、４は電源ＶＤＤが印加される電
源端子、５は抵抗性素子Ｒ５〜ＲＩＯよ構成υ、電源端
子４よシ流れ込んでくる電流よシ複数の重み付け電流を
発生する抵抗網、 Ａｉ 、！： Ｍｌｉ（ｉ＝１〜４
）は抵抗網５の重み付け電流の出力端子をＶＲＥＦに定
電圧化する為の差動増幅器とＦＥＴ。FIG. 2 shows a different embodiment of the invention from FIG. 1. In FIG. 2, 1 is the first analog output terminal; 2 is the second analog output terminal; 0, 3 is the reference voltage terminal to which the reference voltage VREF is applied; 4 is the power supply terminal to which the power supply VDD is applied; 5 is a resistive network composed of resistive elements R5 to RIO, υ, which generates multiple weighted currents from the current flowing into the power supply terminal 4, Ai,! : Mli (i=1~4
) is a differential amplifier and FET for making the weighted current output terminal of the resistor network 5 a constant voltage VREF.
Ｍ２１〜Ｍ２３．Ｍ３１〜Ｍ３３はＭｌｌ〜Ｍ１３よシ
流れ込む重み付け電流をＩｏ又はＩＯのいずれかに導び
くスイッチ用ＦＥＴ、ＤＩ〜Ｄ３はデジタル入力端子、
６はＤ１〜Ｄ３に印加されるデジタル入力信号に応じて
ＦＥＴ、Ｍ２１〜Ｍ２３．Ｍ３１〜Ｍ３３を制御する信
号。M21-M23. M31 to M33 are switch FETs that guide the weighted current flowing from Mll to M13 to either Io or IO, DI to D3 are digital input terminals,
6 are FETs, M21 to M23 . A signal that controls M31 to M33.
１ａ〜３ａ、ｌｂ〜３ｂを発生する回路である。同図に
おいてＲ５〜ＲＩＯは
Ｒ６＝Ｒ８＝Ｒ’、Ｒ５＝Ｒ７＝Ｒ９＝Ｒ１０＝２Ｒ’
に設定されている。This is a circuit that generates signals 1a to 3a and lb to 3b. In the same figure, R5 to RIO are R6=R8=R', R5=R7=R9=R10=2R'
is set to .
ここで各重み付け電流値がどのようになるかを見てみる
。Let's take a look at what each weighted current value looks like.
前述のとおシ、重み付け電流出力端は全てＶＲＥＦＫ定
電圧化されているので、抵抗網５を流れている電流を検
討する場合、重み付け電流出力端を短絡して考えること
が可能である。As mentioned above, all the weighted current output terminals are set to VREFK constant voltage, so when considering the current flowing through the resistor network 5, it is possible to short-circuit the weighted current output terminals.
まず、Ｒｇ、Ｒ９，ＲＩＯの接続ノード８に注目すると
、ノード８よりＲ９側を見た場合のインピーダンスはＲ
９の抵抗値２ Ｒ／であ、９、Ｒ１０側を見た場合のイ
ンピーダンスはＲＩＯの抵抗値２Ｒ′である。従ってノ
ード８にＲ８側から流れ込んで来た電流はＲ９とＲＩＯ
に２分されて流れる。次ＫＲ６，Ｒ７，Ｒｓの接続ノー
ド７に注目すると、ノード７よシＲ７側を見た場合のイ
ンピーダンスはＲ７の抵抗値２ Ｒ／であシＲ８側を見
た場合のインピーダンスはＲ８，几９．ＲＩＯの合成抵
抗値でやはシ２ｆｉ、／となる。従ってノード７１ＣＲ
６側から流れ込んで来た電流はＲ７とＲ８に２分されて
流れる。First, if we pay attention to the connection node 8 of Rg, R9, and RIO, the impedance when looking from the node 8 to the R9 side is R
The resistance value of 9 is 2R/, and the impedance when looking at the 9 and R10 sides is the resistance value of RIO 2R'. Therefore, the current flowing into node 8 from the R8 side is connected to R9 and RIO.
It flows in two parts. Next, paying attention to the connection node 7 of KR6, R7, and Rs, when looking from the node 7 to the R7 side, the impedance is the resistance value of R7 2 R / When looking from the R8 side, the impedance is R8, 几9 ．． The combined resistance value of RIO is 2fi,/. Therefore node 71CR
The current flowing from the 6 side is divided into two and flows through R7 and R8.
さらに電源端子４に注目すると端子４よシＲ５側を見た
場合のインピーダンスはＲ５の抵抗値２Ｒ′であシＲ６
側を見た場合のインピーダンスはＲ６〜ＲＩＯの合成抵
抗値でやはＤ ２Ｒ’となる。従りてＲ５とＲ６には同
じ大きさの電流が流れることがわかる。Furthermore, looking at power supply terminal 4, the impedance when looking from terminal 4 to the R5 side is the resistance value 2R' of R5 and R6
The impedance when looking at the side is the combined resistance value of R6 to RIO, which is D2R'. Therefore, it can be seen that the same magnitude of current flows through R5 and R6.
と（７）！果、Ｖｕ ’ ＝ ＶＤＤ −ＶＲＥＰとす
ルトＲ９とＲＩＯには１ 、 ’ＩＪｎ／−の大き
さの電流が４ ２Ｒ’
流れることになる。And (7)! As a result, when Vu'=VDD-VREP, a current of 42R' with a magnitude of 1,'IJn/- will flow through the route R9 and RIO.
Ｒ５には４・Ｉ’、Ｒ７には２・Ｉ’、Ｒ９とＲＩＯに
は工“の大きさの電流が流れることがわかる。本実施例
と前述の第１の実施例を比較すると、第１の実施例でＩ
′に相当するのが、本実施例のＩ″であることに気が付
く。従って、本実施例の回路でも第１の実施例と同様に
デジタル、アナログ変換が達成される事が理解される。It can be seen that a current of 4·I' flows through R5, 2·I' flows through R7, and a current of the magnitude of In the example of 1, I
Note that I'' in this embodiment corresponds to I'' in this embodiment. Therefore, it is understood that digital-to-analog conversion can be achieved in the circuit of this embodiment as well as in the first embodiment.
第１の実施例と第２の実施例の間の大きな差はその抵抗
網の構成方法である。ｎ ｂｉｔのＤ／Ａ変換器を構成
する場合、前者では（ｎ十ｉ）本の大きさが最大２（ｎ
−１）倍、異なる抵抗素子が必要なの ′に対して後
者では（ｎ＋ｘ）本の２凡の抵抗と（ｎ−１）本の凡の
抵抗が必要となる。一般に前者はｂｉｔｉ７の少ない場
合に有利であシ、後者はｂｉｔ数の多い場合に有利とな
る。The major difference between the first and second embodiments is the way the resistor network is constructed. When configuring an n-bit D/A converter, in the former case, the size of (n + i) is at most 2 (n
-1) times, different resistance elements are required, whereas in the latter case, (n+x) two resistance elements and (n-1) resistance elements are required. Generally, the former is advantageous when the number of bits 7 is small, and the latter is advantageous when the number of bits is large.
以上説明したようＫ、本発明によればｂｉｔ数が増すに
つれ、ＦＥＴの占有面積が増大する問題や、ＦＥＴの閾
値や駆動能力の温度や経時による変化の問題を解決した
、優れたＤ／Ａ変換器を提供できることがわかる。As explained above, the present invention is an excellent D/A that solves the problem of the area occupied by the FET increasing as the number of bits increases, as well as the problem of changes in the threshold value and driving capacity of the FET due to temperature and aging. It can be seen that a converter can be provided.
なお、前述したように本発明の場合、従来例及び新規に
取り入れたチョッパー型増幅器がいずれも集積回路化に
適している事から、本発明自身も極めて集積回路化に適
しているという特徴も持っておシ、その利用分野は広く
、それにより得られる利益は多大なものである。As mentioned above, in the case of the present invention, both the conventional example and the newly introduced chopper type amplifier are suitable for integration into integrated circuits, so the present invention itself also has the characteristic that it is extremely suitable for integration into integrated circuits. However, its application fields are wide, and the benefits obtained from it are enormous.
第１図は本発明の一実施例の回路図、第２図は本発明の
異なる実施例の回路図、第３図は従来のＤ／Ａ変換器の
一例の回路図、第４図は各回路の論理例である。
１・・・・・・第１のアナログ出力端子、２・・・・・
・第２のアナログ出力端子、３・・・・・・基準電圧端
子、４・・・・・・電源端子、訃・・・・・抵抗網、６
・・・・・・制御回路、Ｍ１１〜Ｍ１４．Ｍ２１〜Ｍ２
３．Ｍ３１〜Ｍ３３・・・・・・ＦＥＴ。
Ａ１−Ａ４・・・・・・差動増幅器、几１〜ＲＩＯ・・
・・・−抵抗性素子、Ｄ１〜Ｄ３・・・・・・デジタル
入力端子。FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of a different embodiment of the present invention, FIG. 3 is a circuit diagram of an example of a conventional D/A converter, and FIG. 4 is a circuit diagram of an example of a conventional D/A converter. This is an example of circuit logic. 1...First analog output terminal, 2...
・Second analog output terminal, 3...Reference voltage terminal, 4...Power supply terminal, Death...Resistance network, 6
...Control circuit, M11 to M14. M21~M2
3. M31-M33...FET. A1-A4...Differential amplifier, 几1~RIO...
...-Resistive element, D1-D3...Digital input terminal.
Claims (1)
ナログ端子と、基準電圧端子と、複数の重み付け電流を
発生する抵抗網と、前記抵抗網の重み付け電流の出力端
子におのおのソースを接続した第１のＦＥＴ群と、前記
第１のＦＥＴ群中のおのおののＦＥＴのソースに第１の
入力端子を接続し、第２の入力端子を前記基準電圧端子
に接続し、出力端子をおのおののＦＥＴのゲートに接続
した差動増幅器群と、前記第１のＦＥＴ群中のおのおの
のＦＥＴのドレインにおのおののソースを接続しドレイ
ンを前記第１のアナログ出力端子に接続した第２のＦＥ
Ｔ群と、前記第１のＦＥＴ群中のおのおののＦＥＴのド
レインにおのおののソースを接続し、ドレインを前記第
２のアナログ出力端子に接続した第３のＦＥＴ群と、前
記デジタル入力端子に印加されたデジタル入力信号に対
応して、前記第２のＦＥＴ群及び前記第３のＦＥＴ群の
ＦＥＴのゲート電圧を制御する回路とから成ることを特
徴とするＤ／Ａ変換器。A digital input terminal, a first analog output terminal, a second analog terminal, a reference voltage terminal, a resistor network that generates a plurality of weighted currents, and a resistor network that has a source connected to each weighted current output terminal of the resistor network. A first input terminal is connected to the source of one FET group and each FET in the first FET group, a second input terminal is connected to the reference voltage terminal, and an output terminal is connected to the source of each FET in the first FET group. a differential amplifier group connected to the gate; and a second FE, the source of which is connected to the drain of each FET in the first FET group, and the drain of which is connected to the first analog output terminal.
T group, a third FET group in which each source is connected to the drain of each FET in the first FET group, and the drain is connected to the second analog output terminal, and a third FET group in which the voltage is applied to the digital input terminal. A D/A converter comprising a circuit for controlling gate voltages of FETs of the second FET group and the third FET group in response to a digital input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22537186A JPS6379422A (en) | 1986-09-22 | 1986-09-22 | Digital-analog converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22537186A JPS6379422A (en) | 1986-09-22 | 1986-09-22 | Digital-analog converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6379422A true JPS6379422A (en) | 1988-04-09 |
Family
ID=16828301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22537186A Pending JPS6379422A (en) | 1986-09-22 | 1986-09-22 | Digital-analog converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6379422A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02179124A (en) * | 1988-12-29 | 1990-07-12 | Nec Corp | Digital/analog conversion circuit |
| JP2011157878A (en) * | 2010-02-01 | 2011-08-18 | Toyota Motor Corp | Water-cooling adapter |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54136261A (en) * | 1978-04-14 | 1979-10-23 | Nec Corp | Current inversion circuit |
-
1986
- 1986-09-22 JP JP22537186A patent/JPS6379422A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54136261A (en) * | 1978-04-14 | 1979-10-23 | Nec Corp | Current inversion circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02179124A (en) * | 1988-12-29 | 1990-07-12 | Nec Corp | Digital/analog conversion circuit |
| JP2011157878A (en) * | 2010-02-01 | 2011-08-18 | Toyota Motor Corp | Water-cooling adapter |
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