JPS6376451A - Manufacture of compound semiconductor crystal substrate - Google Patents
Manufacture of compound semiconductor crystal substrateInfo
- Publication number
- JPS6376451A JPS6376451A JP21960786A JP21960786A JPS6376451A JP S6376451 A JPS6376451 A JP S6376451A JP 21960786 A JP21960786 A JP 21960786A JP 21960786 A JP21960786 A JP 21960786A JP S6376451 A JPS6376451 A JP S6376451A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- lattice
- groove
- epitaxially grown
- warpage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 45
- 239000013078 crystal Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 150000001875 compounds Chemical class 0.000 title claims description 4
- 238000000034 method Methods 0.000 claims abstract description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 15
- 238000005530 etching Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000005259 measurement Methods 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はシリコン基板上に化合物半導体をヘテロエピタ
キシャル成長させた結晶基板の製造方法に係り、特にシ
リコン単結晶上にＧＩＡｓの単結晶を成長させるのに好
適な化合物半導体結晶基板の製造方法に関するものであ
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a crystal substrate in which a compound semiconductor is heteroepitaxially grown on a silicon substrate, and particularly relates to a method for growing a single crystal of GIAs on a silicon single crystal. The present invention relates to a method for manufacturing a compound semiconductor crystal substrate suitable for.
従来、８ｉ基板の上にＧａＡｓの単結晶をエピタキシャ
ル成長させる場合は８にとＧａＡｓの格子定数差が４チ
あり、熱膨張係数も２．２倍異なるため結晶に応力歪が
発生して良好な単結晶を得ることが困難でありた。そこ
でこれ等応力歪を緩和するためには、例えば特開昭５９
−１７１１１５号公報に示されたように８ｉとＧａＡｓ
の中間的物性値を有するＧｅのようなバッファ層を導入
する方法が用いられていた。しかし、格子定数の異なる
結晶を大面積にエピタキシャル成長させると一方の結晶
の引張り応力により基板全体が反るという問題が生じる
。この問題に対して従来の方法は伺の考慮もされていな
かった。Conventionally, when epitaxially growing a single crystal of GaAs on an 8i substrate, the difference in lattice constant between 8i and GaAs is 4 degrees, and the coefficient of thermal expansion is also 2.2 times different, so stress strain occurs in the crystal, making it difficult to obtain a good single crystal. It was difficult to obtain crystals. Therefore, in order to alleviate these stress strains, for example,
-8i and GaAs as shown in Publication No. 171115
A method of introducing a buffer layer such as Ge having intermediate physical property values has been used. However, when crystals with different lattice constants are epitaxially grown over a large area, a problem arises in that the entire substrate warps due to the tensile stress of one crystal. Conventional methods have not even considered this problem.
上記の従来技術では大面積に格子定数の異なる結晶ヲヘ
テロエビタキシャル成長する場合に生じる基板の反りに
ついて何等の考慮もされておらず、この基板上に微細加
工を必要とするデバイスを作製する場合、ホトリソグラ
フィ一工程においてマスクと基板の密着性が悪くなり露
光パターンの解像度が低下する等の問題があった。The above conventional technology does not take into account the warpage of the substrate that occurs when crystals with different lattice constants are grown heteroepitaxially over a large area, and when manufacturing devices that require microfabrication on this substrate. In one step of photolithography, there were problems such as poor adhesion between the mask and the substrate, resulting in a decrease in the resolution of the exposed pattern.
そこで本発明の目的は大面積基板に格子定数や熱膨張係
数の異なる結晶をヘテロエビタキシャル成長する場合に
、エピタキシャル層の引張り応力を緩和して基板の反り
を少くすることにある。Therefore, an object of the present invention is to alleviate the tensile stress of the epitaxial layer and reduce the warpage of the substrate when crystals having different lattice constants and coefficients of thermal expansion are grown heteroepitaxially on a large-area substrate.
上記目的は大面積基板の表面に格子状の溝を設け、この
上に格子定数の異なる結晶をエピタキシャル成長させる
ことにより、エピタキシャル成長層の歪応力を溝部分の
段差で横方向の比較的小さな部分に分散し、基板全体に
加わる引張り応力を小さくすることにより基板の反り量
を小さくして達成できる。The above purpose is to provide lattice-like grooves on the surface of a large-area substrate and epitaxially grow crystals with different lattice constants on the grooves, thereby dispersing the strain stress in the epitaxially grown layer to a relatively small portion in the lateral direction using the steps in the grooves. However, by reducing the tensile stress applied to the entire substrate, the amount of warpage of the substrate can be reduced.
エピタキシャル成長の基板となる結晶表面に格子状の溝
を設けると、この溝によってエピタキシャル成長された
結晶は横方向の比較的小さな面積に分散されて成長する
ため、応力歪はその面積内にのみ働いて、基板全体の反
りは小さな値に抑制することができる。このため結晶成
長後に行うフォトリソグラフィーの工程においてマスク
と基板の密着性が良くなりパターン％偉度の低下を防止
できる等の利点がある。When lattice-like grooves are provided on the surface of a crystal that serves as a substrate for epitaxial growth, the epitaxially grown crystals grow by being distributed over a relatively small area in the lateral direction, so stress and strain act only within that area. The warpage of the entire substrate can be suppressed to a small value. Therefore, in the photolithography process performed after crystal growth, the adhesion between the mask and the substrate is improved, and there are advantages such as preventing a decrease in pattern % quality.
以下、本発明の一実施例を説明する。第１図は８ｉ基板
上に（ｈＡｓの単結晶をＭＢＢ（分子線エピタキシー）
成長させた場合の基板の大きさと反り量の関係をＧａＡ
ｓ層の厚さをパラメータとして示したものである。アラ
イナの解像度が次式で表わせるとすると１μｍの解像度
を出すために許容される基板の反り量は１０＃ｒ１以下
でなければならない。An embodiment of the present invention will be described below. Figure 1 shows a single crystal of hAs (MBB (molecular beam epitaxy)) on an 8i substrate.
The relationship between the size of the substrate and the amount of warpage when grown is GaA.
The thickness of the s layer is shown as a parameter. Assuming that the resolution of the aligner can be expressed by the following equation, the amount of substrate warpage allowed to achieve a resolution of 1 μm must be 10#r1 or less.
２ｄ内θ ｄ：基板の反り量 θニアライナの性能による決まる値 ここでは３１を計算に用いた。θ within 2d d: Amount of warpage of the board Value determined by the performance of the θ near liner Here, 31 was used for calculation.
基板の反り量を１１１１４ｍ以下にするためには第１図
よりＧ■穆の成長膜厚を２μｍとして、基板の大きさは
１５０以下でなければならない。また、ＧａＡｓ層の厚
さを４μｍとした場合は基板の大きさは９關以下でなけ
ればならない。In order to make the amount of warpage of the substrate 11114 m or less, the thickness of the grown film of G.sub.2 must be 2 .mu.m from FIG. 1, and the size of the substrate must be 150 mm or less. Further, when the thickness of the GaAs layer is 4 μm, the size of the substrate must be 9 mm or less.
以上の条件を満たして２インチや３インチのＳｉウェハ
上にＧａＡｓ膜を形成する方法として第２図に示すよう
な格子状の溝をＳｉウェハ上に設けた。溝はホトレジス
トで幅２０ａｍのストライプ状にパターンニングした後
、このレジストをマスクとして深さ１０μｍにエツチン
グして作製した。このウェハの部分断面図を第３図に、
そのウェハ上にＧａＡｓを成長させた後の部分断面図を
第４図に示した。As a method for forming a GaAs film on a 2-inch or 3-inch Si wafer while satisfying the above conditions, lattice-shaped grooves as shown in FIG. 2 were provided on the Si wafer. The grooves were fabricated by patterning a photoresist into stripes with a width of 20 am, and then etching to a depth of 10 μm using the resist as a mask. A partial cross-sectional view of this wafer is shown in Figure 3.
FIG. 4 shows a partial cross-sectional view after growing GaAs on the wafer.
Ｓｉウェハに格子状の溝を設けることにより、この上に
エピタキシャル成長させたＧａＡｓ層は格子寸法に分割
される。したがってＧａＡｓ層に発生する応力は格子寸
法の内部に分散され基板の反りは緩和される。格子間隔
の寸法はエピタキシャル成長させるＧａＡｓ層の厚さと
成長時の温度条件によっても適正値は異なるが、おおよ
そ第１図に示した関係が適用できるので、ＧａＡｓ層の
厚さを２μｍ成長させる場合は格子間隔の寸法をＩＯＷ
として、反りの量を許容限界値以内におさめることがで
きる。By providing a lattice of grooves in the Si wafer, the GaAs layer epitaxially grown thereon is divided into lattice dimensions. Therefore, the stress generated in the GaAs layer is dispersed within the lattice dimensions, and the warpage of the substrate is alleviated. The appropriate value for the lattice spacing varies depending on the thickness of the GaAs layer to be epitaxially grown and the temperature conditions during growth, but the relationship shown in Figure 1 can be applied, so when growing the GaAs layer to a thickness of 2 μm, the lattice spacing Interval dimension IOW
As a result, the amount of warpage can be kept within acceptable limits.
本実施例によれば２インチウェハのようなＳｉの大面積
基板上に格子定数や熱膨張係数の異なるＧａＡｓ結晶を
エピタキシャル成長させても、基板の反り量を１０μｍ
以下の値に抑制できる効果がある。According to this example, even if GaAs crystals with different lattice constants and coefficients of thermal expansion are epitaxially grown on a large-area Si substrate such as a 2-inch wafer, the amount of warpage of the substrate can be reduced to 10 μm.
It has the effect of suppressing it to the following values.
本発明によれば大面積の基板結晶上に格子定数や熱膨張
係数の異なる別の結晶をエピタキシャル成長させた後も
基板の反りを一定値以下に抑えることができるので、こ
の基板を用いて微細なデバイス構造をホトリソグラフィ
ープロセスによす作製する場合に、その解像度を低下さ
せない効果がある。According to the present invention, even after another crystal with a different lattice constant or thermal expansion coefficient is epitaxially grown on a large-area substrate crystal, the warpage of the substrate can be suppressed to a certain value or less. When fabricating a device structure using a photolithography process, it has the effect of not reducing its resolution.
第１図は本発明の一実施例による基板の反り量の関係、
を説明する図、第２図は本発明の一実施例を示すＳｉ基
板表面に格子状の溝を設けたことを示す説明図、第３図
はＳｉ基板の部分断面図、第４図は８ｉ基板の表面Ｇａ
Ａｓ結晶をエピタキシャル成長させた後の状態を示す部
分断面図である。
ｌ・・・Ｓｉ基板 ２・・・格子状溝３・・・
ＧａＡｓ結晶層
代理人 弁理士 小 川 勝 男
棄１図
基板Φ大３Ｅ （？ｌＬマリ
亨１図
３、 （ｉｌｌＡ９Ｒ易ａFIG. 1 shows the relationship between the amount of warpage of a substrate according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram showing a grid-like groove provided on the surface of a Si substrate according to an embodiment of the present invention, FIG. 3 is a partial cross-sectional view of the Si substrate, and FIG. 4 is an 8i Surface Ga of the substrate
FIG. 3 is a partial cross-sectional view showing a state after epitaxial growth of As crystal. l...Si substrate 2...lattice groove 3...
GaAs crystal layer agent Masaru Ogawa, patent attorney
Claims (1)
膨張係数の異なる別の結晶をエピタキシャル成長させた
半導体基板において、エピタキシャル成長膜に生じる歪
応力を緩和するためにあらかじめ基板表面に格子状の溝
を設けたことを特徴とする化合物半導体結晶基板の製造
方法。1. In a semiconductor substrate in which a thin single-crystal substrate and another crystal with a different lattice constant or thermal expansion coefficient are epitaxially grown on the surface of the substrate, a lattice-like structure is formed on the substrate surface in advance in order to alleviate the strain stress that occurs in the epitaxially grown film. A method for manufacturing a compound semiconductor crystal substrate, characterized in that a groove is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21960786A JPS6376451A (en) | 1986-09-19 | 1986-09-19 | Manufacture of compound semiconductor crystal substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21960786A JPS6376451A (en) | 1986-09-19 | 1986-09-19 | Manufacture of compound semiconductor crystal substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6376451A true JPS6376451A (en) | 1988-04-06 |
Family
ID=16738180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21960786A Pending JPS6376451A (en) | 1986-09-19 | 1986-09-19 | Manufacture of compound semiconductor crystal substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6376451A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529454A (en) * | 1991-07-19 | 1993-02-05 | Seikosha Co Ltd | Manufacture of semiconductor integrated circuit chip |
| JP2007180556A (en) * | 1997-10-07 | 2007-07-12 | Cree Inc | Nitride photonic device of group iii on silicon carbide substrate having conductive buffer intermediate layer structure |
| JP2008536319A (en) * | 2005-04-15 | 2008-09-04 | ラティス パワー （チアンシ） コーポレイション | Method for forming an InGaAlN film and a light emitting device on a silicon substrate |
| JP2011129828A (en) * | 2009-12-21 | 2011-06-30 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device, and method of manufacturing semiconductor substrate |
| CN105990308A (en) * | 2015-03-17 | 2016-10-05 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
-
1986
- 1986-09-19 JP JP21960786A patent/JPS6376451A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529454A (en) * | 1991-07-19 | 1993-02-05 | Seikosha Co Ltd | Manufacture of semiconductor integrated circuit chip |
| JP2007180556A (en) * | 1997-10-07 | 2007-07-12 | Cree Inc | Nitride photonic device of group iii on silicon carbide substrate having conductive buffer intermediate layer structure |
| JP2008536319A (en) * | 2005-04-15 | 2008-09-04 | ラティス パワー （チアンシ） コーポレイション | Method for forming an InGaAlN film and a light emitting device on a silicon substrate |
| JP2011129828A (en) * | 2009-12-21 | 2011-06-30 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device, and method of manufacturing semiconductor substrate |
| CN105990308A (en) * | 2015-03-17 | 2016-10-05 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
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