JPS6373528A - Gettering structure of semiconductor device - Google Patents
Gettering structure of semiconductor deviceInfo
- Publication number
- JPS6373528A JPS6373528A JP21837586A JP21837586A JPS6373528A JP S6373528 A JPS6373528 A JP S6373528A JP 21837586 A JP21837586 A JP 21837586A JP 21837586 A JP21837586 A JP 21837586A JP S6373528 A JPS6373528 A JP S6373528A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gettering
- defective
- type
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005247 gettering Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 230000007547 defect Effects 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000009792 diffusion process Methods 0.000 abstract description 26
- 230000002950 deficient Effects 0.000 abstract description 17
- 230000000694 effects Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 4
- 230000001133 acceleration Effects 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract description 2
- 239000002245 particle Substances 0.000 abstract 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 238000001556 precipitation Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005488 sandblasting Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造におけるゲッタリングのた
めに設ける半導体装置のゲッタリング構造に関し、特に
リーク、ノイズ特性に対し優秀な半導体集積回路を製造
するのに適した半導体装置のゲッタリング構造に関する
。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a gettering structure of a semiconductor device provided for gettering in the manufacture of semiconductor devices, and in particular to a semiconductor integrated circuit with excellent leakage and noise characteristics. The present invention relates to a gettering structure for a semiconductor device suitable for manufacturing.
リークの少ない或いはノイズ特性の良好な集積回路用半
導体装置を製造するために、半導体基板の裏面または半
導体基板中に何らかの方法で欠陥層を発生させ、この欠
陥層で拡散プロセス中に必然的に侵入して来るナトリウ
ム等の重金属イオンをゲッタリングするのが一般的であ
る。In order to manufacture semiconductor devices for integrated circuits with low leakage or good noise characteristics, a defective layer is generated on the back side of the semiconductor substrate or in the semiconductor substrate by some method, and this defective layer inevitably invades during the diffusion process. Generally, heavy metal ions such as sodium are gettered.
従来の半導体装置のゲッタリング構造としては前述した
欠陥層を半導体基板表面に設はエクストリンシックゲッ
タリング（外部ゲッタリング）を行う構造と、半導体基
板内部に欠陥層を設け、イントリンシックゲッタリング
（内部ゲッタリング）を行う構造とがある。前者の例と
して、半導体基板裏面にサンドブラスト法等によシ機械
的歪みを与えて欠陥層を作っておく構造がある。後者の
例として、結晶引き上げ時の酸素濃度をコントロールし
て、基板内部にのみ酸素析出による欠陥層を作っておく
構造がある。Conventional gettering structures for semiconductor devices include a structure in which the aforementioned defect layer is provided on the surface of the semiconductor substrate to perform extrinsic gettering (external gettering), and a structure in which a defect layer is provided inside the semiconductor substrate to perform intrinsic gettering (internal gettering). There is a structure that performs gettering). An example of the former is a structure in which a defect layer is created by applying mechanical strain to the back surface of a semiconductor substrate by sandblasting or the like. An example of the latter is a structure in which the oxygen concentration during crystal pulling is controlled to create a defective layer due to oxygen precipitation only inside the substrate.
第２図に従来の半導体装置のゲッタリング構造を設けた
半導体集積回路装置の断面図を示す。図において、１は
Ｐ型半導体基板、２ｒｉＮ＋型埋込層、１ｌｒｉＮ型エ
ピタキシャル層、３ｒｉＰ＋型杷縁拡散層、５ｒｉＰ型
ベース拡散層、６ａｒｉコレクタ引出し用Ｎ＋型拡散層
、５ｂｒｉＮ＋型工きツタ拡散層、７は熱酸化膜等の絶
縁膜、８ｒｉアルにクム等の電極金属、９ｒｊプントブ
ラスト法等による牛導体基板裏面欠陥層、ｌｌｔ酸素析
出による内部欠陥層である。FIG. 2 shows a cross-sectional view of a semiconductor integrated circuit device provided with a conventional gettering structure of a semiconductor device. In the figure, 1 is a P-type semiconductor substrate, 2riN+ type buried layer, 1lriN type epitaxial layer, 3riP+ type rim diffusion layer, 5riP type base diffusion layer, 6ari collector extraction N+ type diffusion layer, 5briN+ type carved ivy diffusion layer , 7 is an insulating film such as a thermal oxide film, 8ri is an electrode metal such as cum, 9rj is a defective layer on the back surface of a conductor substrate by Punto blasting method, etc., and is an internal defective layer by llt oxygen precipitation.
上述した従来の半導体装置のゲッタリング構造は次のよ
うな欠点がある。The gettering structure of the conventional semiconductor device described above has the following drawbacks.
まず、サンドブラスト法等による欠陥層を作シエリスト
リンシ、クゲ、タリングを行う構造および基板中の酸素
析出による欠陥層でイントリンシックゲッタリングを行
う構造の共通の欠点は、これらが半導体基板製造時に形
成される欠陥層を利用しているため拡散プロセスの進行
と共にゲッタリングの効果がほとんど消失してしまい、
最も重要な工程であるベースやエミッタ拡散層形成時に
はグヅタリング効果がなく、リーク不良やノイズ発生と
いう問題点を生ずる。更に、実際のデバイスを作シ込む
半導体基板表面から、実際にゲッタリングを行なう欠陥
層までの距離が数百ばクロンと遠いため１重金属イオン
の拡散が大きいことを考慮に入れてもゲッタリング能力
にｒｔ限界がある。First of all, the common disadvantage of structures in which a defective layer is created by sandblasting, etc., and structures in which intrinsic gettering is performed on a defective layer due to oxygen precipitation in the substrate is that Since the defect layer that is formed is used, the gettering effect almost disappears as the diffusion process progresses.
There is no sagging effect during the most important process of forming the base and emitter diffusion layers, resulting in problems such as leakage defects and noise generation. Furthermore, the distance from the surface of the semiconductor substrate on which the actual device is fabricated to the defect layer where gettering is actually performed is a long distance of several hundred micrometers, so even taking into account the large diffusion of heavy metal ions, the gettering ability is still low. has an rt limit.
また単独の欠点としては、サンドブラスト法で裏面に歪
を与える構造では、半導体基板裏面に凹凸をつけるため
、拡散プロセス中でゴず等が凹凸に入シ、洗浄工程でそ
のゴミを除ききれず不良の原因となる。Another drawback is that with a structure in which the back surface is distorted by sandblasting, the back surface of the semiconductor substrate is made uneven, so dirt and the like get into the unevenness during the diffusion process, and the cleaning process cannot remove the dirt, resulting in defects. It causes
一方、酸素析出によシ欠陥層を設けた構造では。On the other hand, in a structure in which a defect layer is provided due to oxygen precipitation.
基板中の酸素濃度の制御が困難で、ＩＲ素濃度が少なす
ぎると欠陥層が形成できず、逆に酸素濃度が多すぎると
回路を実際に作シ込む半導体基板表面Ｋまで欠陥層が遅
し回路が電気的に不良になってしまうという欠点も有す
る。It is difficult to control the oxygen concentration in the substrate; if the IR element concentration is too low, a defective layer cannot be formed; on the other hand, if the oxygen concentration is too high, the defective layer slows down to the surface K of the semiconductor substrate where the circuit is actually fabricated. It also has the disadvantage that it becomes electrically defective.
本発明の半導体装置のゲッタリング構造は、第１導電型
の半導体基板と、この半導体基板上に設けられた第１導
電型と反対の第２導電型のエピタキシャル層と、このエ
ピタキシャル層を複数個の島状領域に絶縁分離するため
の第１導電型の絶縁拡散層と、前記絶縁拡散層の表面の
少なくとも一部にかつ前記絶縁拡散層よシ逸脱しなよう
に設けられた欠陥層とを含んで構成される。The gettering structure of the semiconductor device of the present invention includes a semiconductor substrate of a first conductivity type, an epitaxial layer of a second conductivity type opposite to the first conductivity type provided on the semiconductor substrate, and a plurality of epitaxial layers. an insulating diffusion layer of a first conductivity type for insulating isolation into island-like regions; and a defect layer provided on at least a part of the surface of the insulating diffusion layer so as not to deviate from the insulating diffusion layer. It consists of:
次に１本発明を図面を参照して説明する。 Next, one embodiment of the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
第２図に示す半導体集積回路装置とは、基板ＩＫ裏面欠
陥層９および内部欠陥層を設けてないのく対し、Ｐ＋型
絶縁拡散層３中にゲッタリング能力を有する欠陥層４を
設けである点が異なる。The semiconductor integrated circuit device shown in FIG. 2 has a defect layer 4 having a gettering ability in a P+ type insulating diffusion layer 3, whereas a substrate IK backside defect layer 9 and an internal defect layer are not provided. The points are different.
第１図は半導体集積回路装置中に作シ込まれるＮＰＮ）
ランジスタに適用した実施例で欠陥層４を拡散プロセス
中で選択的に絶縁分離層４の内部に形成し、ゲッタリン
グ作用を行なわしめるものである。Figure 1 shows NPN (NPN) which is fabricated in a semiconductor integrated circuit device.
In an embodiment applied to a transistor, a defective layer 4 is selectively formed inside the insulating separation layer 4 during a diffusion process to perform a gettering effect.
尚、欠陥層４をＰＮ接合を含むように形成すると当然接
合リークを生ずる。従って電気的特性に全く影響を与え
ないＰ＋型絶縁拡散層３中に形成することが好まじり、
また、これによシ素子サイズの増大は一切ない。Note that if the defective layer 4 is formed to include a PN junction, junction leakage will naturally occur. Therefore, it is preferable to form it in the P+ type insulating diffusion layer 3, which does not affect the electrical characteristics at all.
Furthermore, this does not result in any increase in element size.
更に、欠陥層４を形成するのは、Ｐ＋型絶縁拡散層３を
形成した直後、即ちＰ型ベース拡散層５の形成直前が良
−０即ち、埋込み工程を含め ｐ＋型型数散層３形成し
た後は高温、長時間の熱処理はなく、従って欠陥層４の
ゲッタリング能力の消失もな９゜しかも重要なペース、
エミッタ領域形成の直前なので最大限のゲッタリング能
力を発揮できるからである。Furthermore, the defect layer 4 is formed immediately after the formation of the P+ type insulating diffusion layer 3, that is, immediately before the formation of the P type base diffusion layer 5. After that, there is no high-temperature, long-term heat treatment, and therefore the gettering ability of the defect layer 4 is not lost.
This is because the maximum gettering ability can be exhibited because it is immediately before the formation of the emitter region.
尚、欠陥層４の形成は写真食刻工程−回の追加と、イオ
ン注入法等によシ可能である。即ち、高加速エネルギー
で半導体基板にイオン注入した場合、基板の原子がノッ
クオンされ格子欠陥を生ずる。一般的には加速エネルギ
ー１００ＫｅＶで格子欠陥は数十個程度発生する。イオ
ン注入で生じた格子欠陥はアニールをすることにより消
滅させることはできるが１本実施例はこのアニールを行
なわず、格子欠陥をゲッタリングのために積極的に利用
しようとするものである。Incidentally, the defect layer 4 can be formed by adding a photolithography process, ion implantation, or the like. That is, when ions are implanted into a semiconductor substrate with high acceleration energy, atoms in the substrate are knocked on, resulting in lattice defects. Generally, approximately several dozen lattice defects are generated at an acceleration energy of 100 KeV. Although lattice defects caused by ion implantation can be eliminated by annealing, this embodiment does not perform this annealing and actively utilizes the lattice defects for gettering.
以上説明したように本発明は、ゲッタリング能力を有す
る欠陥層を半導体基板上の回路に電気的に影響を与えな
いで、しかも回路部分から近距離に拡散プロセス中に作
シ込むことができるので。As explained above, the present invention allows a defect layer having gettering ability to be created during the diffusion process at a short distance from the circuit portion without electrically affecting the circuit on the semiconductor substrate. .
製造工程中の熱処理によるゲッタリング能力の消失１回
路部分からゲッタリング領域までの遠さによるゲッタリ
ングの不完全さ、ゴミの発生、ゲッタリング用欠陥層が
デバイス特性に悪影響を及ぼす等の欠点を全て解消でき
る効果がある。Loss of gettering ability due to heat treatment during the manufacturing process 1. Disadvantages such as incomplete gettering, generation of dust, and defective layers for gettering that adversely affect device characteristics due to the distance from the circuit part to the gettering region. It has the effect of eliminating everything.
第１図は本発明の一実施例を模式的に示す縦断面図、第
２図は従来の半導体装置のゲッタリング構造を用いた半
導体集積回路装置の模式的な縦断面図である。
１・・・・・・Ｐ型半導体基板、２・・・・・・Ｎ＋型
埋込層。
３・・・・・・Ｐ＋型絶縁拡散層、４・・・・・・欠陥
層、５・・・・・・Ｐ型ベース拡散層、６ａ・・・・・
・Ｎ十型コレクタ引出し拡散層、６ｂ・・・・・・Ｎ＋
型エミ、り拡散層、７・・・・・・絶縁膜、８・・・・
・・電極金属、９・・・・・・裏面欠陥層。
１０・・・・・・酸素析出による内部欠陥層。FIG. 1 is a vertical cross-sectional view schematically showing an embodiment of the present invention, and FIG. 2 is a schematic vertical cross-sectional view of a semiconductor integrated circuit device using a gettering structure of a conventional semiconductor device. 1...P type semiconductor substrate, 2...N+ type buried layer. 3...P+ type insulating diffusion layer, 4...Defect layer, 5...P type base diffusion layer, 6a...
・N10 type collector drawer diffusion layer, 6b...N+
Type emitter, diffusion layer, 7... Insulating film, 8...
...electrode metal, 9...back defect layer. 10... Internal defect layer due to oxygen precipitation.
Claims (1)
れた第１導電型と反対の第２導電型のエピタキシャル層
と、このエピタキシャル層を複数個の島状領域に絶縁分
離するための第１導電型の絶縁拡散層と、前記絶縁拡散
層の表面の少なくとも一部にかつ前記絶縁拡散層より逸
脱しなように設けられた欠陥層とを含むことを特徴とす
る半導体装置のゲッタリング構造。A semiconductor substrate of a first conductivity type, an epitaxial layer of a second conductivity type opposite to the first conductivity type provided on the semiconductor substrate, and a semiconductor substrate for insulating and separating the epitaxial layer into a plurality of island regions. A gettering structure for a semiconductor device, comprising: an insulating diffused layer of one conductivity type; and a defect layer provided on at least a part of the surface of the insulating diffused layer so as not to deviate from the insulating diffused layer. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21837586A JPS6373528A (en) | 1986-09-16 | 1986-09-16 | Gettering structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21837586A JPS6373528A (en) | 1986-09-16 | 1986-09-16 | Gettering structure of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6373528A true JPS6373528A (en) | 1988-04-04 |
Family
ID=16718909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21837586A Pending JPS6373528A (en) | 1986-09-16 | 1986-09-16 | Gettering structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6373528A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56111244A (en) * | 1980-02-08 | 1981-09-02 | Toshiba Corp | Preparation of semiconductor device |
| JPS6129537A (en) * | 1984-07-20 | 1986-02-10 | 日本特殊塗料株式会社 | Molded soundproof material with note sticking section and manufacture thereof |
-
1986
- 1986-09-16 JP JP21837586A patent/JPS6373528A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56111244A (en) * | 1980-02-08 | 1981-09-02 | Toshiba Corp | Preparation of semiconductor device |
| JPS6129537A (en) * | 1984-07-20 | 1986-02-10 | 日本特殊塗料株式会社 | Molded soundproof material with note sticking section and manufacture thereof |
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