JPS6369260A - 2-layered integrated circuit and manufacture thereof - Google Patents
2-layered integrated circuit and manufacture thereofInfo
- Publication number
- JPS6369260A JPS6369260A JP21331986A JP21331986A JPS6369260A JP S6369260 A JPS6369260 A JP S6369260A JP 21331986 A JP21331986 A JP 21331986A JP 21331986 A JP21331986 A JP 21331986A JP S6369260 A JPS6369260 A JP S6369260A
- Authority
- JP
- Japan
- Prior art keywords
- double
- sheet
- integrated circuit
- sided wiring
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 claims description 15
- 230000004927 fusion Effects 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims 2
- 238000007789 sealing Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 33
- 239000012790 adhesive layer Substances 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 238000007747 plating Methods 0.000 abstract description 5
- 239000011888 foil Substances 0.000 abstract description 3
- 238000004080 punching Methods 0.000 abstract description 2
- 238000005476 soldering Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 11
- 241000238413 Octopus Species 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007500 overflow downdraw method Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は二層構造を有する集積回路およびその製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an integrated circuit having a two-layer structure and a method for manufacturing the same.
（従来の技術）
従来は半導体素子を積層するために、半導体素子のボン
ディングバンド部同士を、ハンダを介して接続するフリ
ップチップ方式と称される方法を用いていた。第Ｓ図は
フリップチップ方式を用いて二層構造の集積回路を構成
した場合の接続部の拡大図を示すものである。(Prior Art) Conventionally, in order to stack semiconductor elements, a method called a flip-chip method has been used in which bonding band portions of semiconductor elements are connected to each other via solder. FIG. S shows an enlarged view of the connection portion when a two-layer integrated circuit is constructed using the flip-chip method.
（発明が解決しようとする問題点）
従来の技術によれば、積層する半導体素子間における層
間結線に際し、上下の半導体素子のボンディングバンド
の位置と電気的接続を必要とする箇所との関係は、必ず
しも一致していないため、該上下の半導体素子間におい
て、ボンディングバンドの位置を任意に選べないことか
ら、半導体素子の回路パターン設計の自由度が低くなる
という問題点がある。(Problems to be Solved by the Invention) According to the conventional technology, when making interlayer connections between stacked semiconductor elements, the relationship between the positions of the bonding bands of the upper and lower semiconductor elements and the locations requiring electrical connection is as follows. Since they do not necessarily match, the position of the bonding band cannot be arbitrarily selected between the upper and lower semiconductor elements, resulting in a problem that the degree of freedom in designing the circuit pattern of the semiconductor element is reduced.
そこで、本発明は、１責層される半導体素子のボンディ
ングバンドの位置によらず、該半導体素子どうしの電気
的条件が満足されるような層間結線の自由度が大きい二
層式集積回路およびその製造方法の提供を目的とする。SUMMARY OF THE INVENTION The present invention provides a two-layer integrated circuit and a two-layer integrated circuit that has a high degree of freedom in interlayer connection so that the electrical conditions between semiconductor elements are satisfied regardless of the position of the bonding band of the semiconductor elements in one layer. The purpose is to provide a manufacturing method.
（問題点を解決するための手段）
本発明によれば、積層しようとする半導体素子の間に中
間層を設け、この中間Ｉ※において、上下の半導体素子
の異なった位置に形成されているボンディングバンドど
うしが電気的に喀続されるように結線すると共に上下の
半導体素子どうしを機械的に強固に結合させるものであ
る。(Means for solving the problem) According to the present invention, an intermediate layer is provided between semiconductor elements to be stacked, and in this intermediate layer I*, bonding is formed at different positions of upper and lower semiconductor elements. The bands are connected so that they are electrically interconnected, and the upper and lower semiconductor elements are mechanically and firmly connected to each other.
前記中間層は、絶縁シートの両面に導電パターンおよび
スルホール電極を設けることによって形成された両面配
線回路シートである。そして、該両面配線回路シートを
介して、−悸の半導体素子をハンダリフロー法と称され
るハンダバンブを用いた熱融着方法によっ−〔ｉ′￥続
し、二層式集積回路を得るものである。The intermediate layer is a double-sided wiring circuit sheet formed by providing a conductive pattern and through-hole electrodes on both sides of an insulating sheet. Then, through the double-sided wiring circuit sheet, the semiconductor elements are connected by a heat fusion method using solder bumps called solder reflow method to obtain a two-layer integrated circuit. It is.
（作 用）
本発明によれば、積層しようとする各々の半導体素子に
おいて、異なった箇所に設けられたボンディングパッド
どうしを前記両面配線回路シートを介して電気的に接続
できるという作用がある。(Function) According to the present invention, bonding pads provided at different locations in each semiconductor element to be stacked can be electrically connected to each other via the double-sided wiring circuit sheet.
また、ハンダリフロー法により、両面配線回路シートを
介して前記半２９体素子どうしが強固に接続されるとい
う作用もある。Further, the solder reflow method has the effect that the half-29 elements are firmly connected to each other via the double-sided wiring circuit sheet.
（実施例）
本発明を図示する実施例にもとづいて、さらに詳しく説
明する。(Example) The present invention will be described in more detail based on an illustrative example.
第１図（、）乃至（ｈ）は本発明の二層式集積回路の製
造工程を説明するために示した断面図である。FIGS. 1(a) to 1(h) are cross-sectional views shown for explaining the manufacturing process of a two-layer integrated circuit according to the present invention.
図中、夕は絶縁シート、乙は絶縁シート左の表面に設け
た表面の接着剤層、７は積層する半導体素子の大きさに
合わせてバンチングして設けた孔、ｇは絶縁シートＳの
表面に接着剤層６を介して設けた表面導電層、ヲは絶縁
シートＳの裏面に設けた裏面の接着剤層、１０は絶縁シ
ート５の裏面に接着剤層ヲを介して設けた裏面導電層、
／／はスルーホールを形成するために設けた貫通孔、／
２は導′Ｍ５層ｇまたは１０の上面に設けた金属メッキ
膜、／３は貫通孔／／を充填して導電層ｇおよび１０を
接続するためのハンダ、／ｑおよび／Ｓは半導体素子、
／乙はハンダバンブ、ニアは単位両面配線回路、仁９は
両面配線回路シート、−北上は二層式集積回路である。In the figure, Y is an insulating sheet, B is a surface adhesive layer provided on the left surface of the insulating sheet, 7 is a hole prepared by bunching according to the size of the semiconductor elements to be stacked, g is the surface of an insulating sheet S 10 is a surface conductive layer provided on the back surface of the insulating sheet 5 via an adhesive layer 6; ,
// is a through hole provided to form a through hole, /
2 is a metal plating film provided on the upper surface of the conductive layer g or 10, /3 is a solder for filling the through hole // and connecting the conductive layers g and 10, /q and /S are semiconductor elements,
/ Otsu is a solder bump, Near is a unit double-sided wiring circuit, Jin 9 is a double-sided wiring circuit sheet, - Kitakami is a two-layer integrated circuit.
第二図は両面配縁回路シート二〇の平面図であり、３０
はスプロケットホール、７ｇは単位両面配線回路圧が形
成される領域、また黒く塗りつぶされた領域は孔７に対
応する領域である。FIG. 2 is a plan view of double-sided wiring circuit sheet 20, and 30
is a sprocket hole, 7g is a region where a unit double-sided wiring circuit pressure is formed, and the blacked out region is a region corresponding to hole 7.
第３図（ａ） （ｂ）はシリコンウェハの平面図を示し
ており、同図（ａ）は両面配線回路シート−〇の上側の
シリコンクエバ（５２１また同図（ｂ）は同下側のシリ
コンウェハ（４２）である。第３図（ａ） （ｂ）にお
いて、ｌＩ／は半２体素子／グ、Ｓ／は半導体素子／Ｓ
にそれぞれ対応しており、またｑ３１．５′３はシリコ
ンウェハのオリフラ部を示す。Figures 3(a) and 3(b) show plan views of the silicon wafer. Figure 3(a) shows the upper silicon cube (521) of the double-sided wiring circuit sheet, and Figure 3(b) shows the lower silicon wafer. The wafer (42) is a wafer (42). In FIGS.
and q31.5'3 indicates the orientation flat part of the silicon wafer.
第り図は両面配線回路シート２０の表裏両面にシリコン
ウェハを配置したときの断面図である。Figure 2 is a sectional view when silicon wafers are placed on both the front and back sides of the double-sided wiring circuit sheet 20.
しかして、二層式集積回路の製造工程について説明する
。The manufacturing process of the two-layer integrated circuit will now be described.
まず、第１図（ａ）に示すような、例えばポリイミドフ
ィルムなどの絶縁シートに対して積層する半導体素子の
大きさに合わせてパンチングによる孔７を設ける。これ
と同時に第３図（＝示すようにテープの両サイドに対し
てもスプロケットホール３０をパンチングであける。First, holes 7 are punched to match the size of the semiconductor elements to be laminated on an insulating sheet such as a polyimide film, as shown in FIG. 1(a). At the same time, sprocket holes 30 are punched on both sides of the tape as shown in FIG.
次に、第１図（ｂ）に示すようなエポキシ系樹脂などの
接着剤層６が塗布された金属箔テープ（例えば銅箔テー
プなど）を、絶縁シート＆の表面に接着し、その後フォ
トリソグラフィー法と
（写真蝕刻技術又は≠蝕刻技術）を用いて同図（ｃ）に
示すようなパターンコンクされた表面導電層ざを形成す
る。Next, a metal foil tape (for example, copper foil tape) coated with an adhesive layer 6 such as epoxy resin as shown in FIG. A patterned surface conductive layer as shown in FIG. 3(c) is formed using a method (photo-etching technique or ≠etching technique).
次に、同図（ｄｌに示すようなエポキシ系樹脂などの接
着剤層９が塗布された金属箔テープを前記表面導電層ｇ
を形成した絶縁シートＳの面と反対側の面に接着し、フ
ォトリソグラフィー法を用いて、同図（、）に示すよう
な、パターンコンクされた表面導電層ｉｏを形成する。Next, a metal foil tape coated with an adhesive layer 9 such as an epoxy resin as shown in the same figure (dl) is attached to the surface conductive layer g.
A patterned surface conductive layer io as shown in FIG.
なお、表面導電層／θを形成する工程においては、前記
表面導電層ｇをフォトレジスト等を用いて保護しておく
必要がある。In addition, in the step of forming the surface conductive layer /θ, it is necessary to protect the surface conductive layer g using a photoresist or the like.
次に、同図（ｆ）に示されるように絶縁シートＳの表裏
両面（皿形成された前記表面導電層ｇおよび前記裏面導
電層１０の所定の位置にスルーホールを形成させるため
の貫通孔／／をパンチングにより設ける。Next, as shown in FIG. 3(f), both the front and back surfaces of the insulating sheet S (through holes for forming through holes at predetermined positions of the surface conductive layer g and the back conductive layer 10 formed in a dish) are prepared. / is provided by punching.
次に、同図（ｇ）に示されるように、メッキ法にした後
、前記貫通孔／／をはんだ／３で接続することにより両
面配線回路シート二〇が出来上がる。Next, as shown in FIG. 3(g), after plating, the through holes // are connected with solder /3, thereby completing a double-sided wiring circuit sheet 20.
なお、第２図に上記の方法により製造された多数の単位
両面配線回路ｌ−７から成るテープ伏の両面配線回路シ
ート２０の上面図を示す。FIG. 2 shows a top view of a tape-covered double-sided wiring circuit sheet 20 comprising a large number of unit double-sided wiring circuits 1-7 manufactured by the above-described method.
このようにして得られた両面配線回路シート２０の表面
と裏面に半導体素子／’Ｉ、／！；を実装することによ
り第１図（ｈ）に示されるような二層式集積回路が形成
される。Semiconductor elements /'I, /! are placed on the front and back sides of the double-sided wiring circuit sheet 20 thus obtained. By implementing the above, a two-layer integrated circuit as shown in FIG. 1(h) is formed.
次に上記した両面配線回路シートへの半導体素子の実装
方法について第２図、第３図（ａ） （ｂ）および第４
図を用いて説明する。Next, FIGS. 2, 3(a), (b) and 4 show the method of mounting semiconductor elements on the above-mentioned double-sided wiring circuit sheet.
This will be explained using figures.
まず、第３図（ａ）に示されるような半導体素子Ｓ／が
多数配列されて成るシリコンウェハ！；、２において、
各半導体素子５／ｉ二具備されている）Ｎ１１
ボンディングパノド部にへンダ努ンプを形成する。同様
に第３図（ｂ）の各半導体素子ｑ／にμ備ハ”
されているボンディングバノド部にもハンダ哄ンプを形
成する。なお第２図に示される両面配線回路シート互ユ
の幅Ｗとシリコンウェハｑ二またはＳ２の外径とは等し
いものである。そして、第４図に示すよう（＝シリコン
ウェハぢのオリフラ部ｑ３と両面配線回路シート２０の
側面３／を位置合わせし、シリコンウェハ≦のボンディ
ングバット部上のハンダバンプｌｑと両面配線回路シー
ト２０のハンダによるスルーホール電極／３をハンダリ
フロー法を用いて熱融着する。First, a silicon wafer consisting of a large number of semiconductor elements S/ as shown in FIG. 3(a) is arranged! ;, In 2,
A solder bump is formed in the N11 bonding panod portion of each semiconductor device (5/i). Similarly, solder bumps are formed on the bonding plate portions provided on each semiconductor element q/ in FIG. 3(b). Note that the width of the double-sided wiring circuit sheet shown in FIG. W and the outer diameter of the silicon wafer q2 or S2 are equal. Then, as shown in FIG. The solder bump lq on the bonding butt portion of the silicon wafer≦ and the solder through-hole electrode /3 of the double-sided wiring circuit sheet 20 are thermally fused using a solder reflow method.
また、上記の熱融着を施した面（裏面）と反対側の面（
表面）においても、同様の方法でシリコンクエバ５２を
熱融着する。In addition, the side (back side) that was heat-sealed above and the opposite side (
The silicone cube 52 is also heat-sealed on the surface) in the same manner.
なお、上記の表面の熱融着と裏面の熱融着は同時に行な
ってもよい。Note that the above-mentioned heat fusion of the front surface and heat fusion of the back surface may be performed at the same time.
このようにして両面配線回路シート二〇を介して、シリ
コンウェハダコ上の半得体素子ダ／とシリコンウェハタ
コ上の半導体素子Ｓ／とが接続される。In this way, the semiconductor element DA/ on the silicon wafer octopus and the semiconductor element S/ on the silicon wafer octopus are connected via the double-sided wiring circuit sheet 20.
次にシリコンクエバの半導体素子が形成されている面に
対して垂直方向（′″−各半導体素子ごとにグイシング
することによって第１図（ｈ）に示されるような二層式
集積回路コ／が完成する。Next, a two-layer integrated circuit as shown in Fig. 1 (h) is completed by guising the silicon cube in a direction perpendicular to the surface on which the semiconductor elements are formed (''' - for each semiconductor element). do.
本発明によれば、一種の半導体素子を積層接続する際、
該半心体素子間（＝スルーホールメッキ及び表裏両面に
配線を施した、両面配線回路シートを中間層として用い
ることにより、上記半導体素子のボンディングパッド部
間の接続を自由に行うことができるという効果を奏する
。According to the present invention, when stacking and connecting one type of semiconductor element,
By using a double-sided wiring circuit sheet with through-hole plating and wiring on both the front and back sides as an intermediate layer between the half-core elements, it is possible to freely connect between the bonding pads of the semiconductor elements. be effective.
り
第１図（ａｌ乃至−は本発明に係る二層式集積回路の製
造方法を説明するため（＝示した各工程の断面図、第２
図は本発明に係る両面回路シートの平面図、第３図（ａ
） （ｂ）は本発明（＝係るシリコンクエバの平面図、
第９図（ａ）は本発明の二層式集積回路の断面図、第９
図（ｂ）は前記二層式集積回路の部分拡大図、第５図は
従来の二層構造の集積回路の構成を示す拡大図である。Figure 1 (al to - is a cross-sectional view of each step shown;
The figure is a plan view of a double-sided circuit sheet according to the present invention, and FIG.
) (b) is a plan view of the present invention (= a plan view of the silicon cube according to the invention,
FIG. 9(a) is a cross-sectional view of a two-layer integrated circuit according to the present invention;
FIG. 5B is a partially enlarged view of the two-layer integrated circuit, and FIG. 5 is an enlarged view showing the structure of a conventional two-layer integrated circuit.
Claims (4)
て成る二層式集積回路において、該中間層が絶縁シート
と該絶縁シートの表裏両面に設けた配線層と該配線層ど
うしを該絶縁シートを貫通して接続するスルーホールと
から成る両面配線回路シートであって、該両面配線回路
シートの表裏両面の所定の箇所に設けた電極部と該半導
体素子のボンディングパッドに設けたハンダバンプとが
熱融着によってボンディングされていることを特徴とす
る二層式集積回路。(1) In a two-layer integrated circuit in which two types of semiconductor elements are stacked one above the other with an intermediate layer in between, the intermediate layer connects an insulating sheet, a wiring layer provided on both the front and back surfaces of the insulating sheet, and the wiring layers to each other. A double-sided wiring circuit sheet comprising through holes penetrating and connecting the insulating sheet, electrode portions provided at predetermined locations on both the front and back surfaces of the double-sided wiring circuit sheet, and solder bumps provided on bonding pads of the semiconductor element. A two-layer integrated circuit characterized in that the and are bonded by heat fusion.
て成る二層式集積回路の製造方法において、該中間層が
絶縁シートの表裏両面に配線層を形成し、該配線層どう
しを該絶縁シートを貫通するスルーホールを設けて形成
した両面配線回路シートであって、該両面配線回路シー
トの表裏両面の所定の箇所に電極部を設け、該半導体素
子のボンディングパッドにハンダバンプを設け、両面配
線回路シートの両面に該半導体素子を配置し、該ハンダ
バンプを熱融着し、該半導体素子をボンディングするこ
とを特徴とする二層式集積回路の製造方法。(2) In a method for manufacturing a two-layer integrated circuit in which two types of semiconductor elements are stacked one above the other with an intermediate layer in between, the intermediate layer forms wiring layers on both the front and back surfaces of an insulating sheet, and the wiring layers are connected to each other. A double-sided wiring circuit sheet formed by providing through holes penetrating the insulating sheet, electrode portions being provided at predetermined locations on both the front and back sides of the double-sided wiring circuit sheet, and solder bumps being provided on bonding pads of the semiconductor element, 1. A method for manufacturing a two-layer integrated circuit, which comprises arranging the semiconductor elements on both sides of a double-sided wiring circuit sheet, heat-sealing the solder bumps, and bonding the semiconductor elements.
形成されていることを特徴とする特許請求の範囲第２項
記載の二層式集積回路の製造方法。(3) A method for manufacturing a two-layer integrated circuit according to claim 2, wherein the double-sided wiring circuit sheet described above is formed into a long tape.
いて、長尺のテープ状に形成された両面配線回路シート
に対して半導体素子を位置合せし、隔着によって行なわ
れることを特徴とする特許請求の範囲第２項および第３
項記載の二層式集積回路の製造方法。(4) Claims characterized in that the above bonding is performed by positioning the semiconductor element on a double-sided wiring circuit sheet formed in the shape of a long tape in a pre-dicing step, and by separating the semiconductor element and attaching the semiconductor element to the double-sided wiring circuit sheet formed in the shape of a long tape. Sections 2 and 3
A method for manufacturing a two-layer integrated circuit as described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21331986A JPS6369260A (en) | 1986-09-10 | 1986-09-10 | 2-layered integrated circuit and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21331986A JPS6369260A (en) | 1986-09-10 | 1986-09-10 | 2-layered integrated circuit and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6369260A true JPS6369260A (en) | 1988-03-29 |
Family
ID=16637180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21331986A Pending JPS6369260A (en) | 1986-09-10 | 1986-09-10 | 2-layered integrated circuit and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6369260A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0393258A (en) * | 1989-08-31 | 1991-04-18 | Hughes Aircraft Co | Three-dimensional integrated circuit construction using discrete chip |
-
1986
- 1986-09-10 JP JP21331986A patent/JPS6369260A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0393258A (en) * | 1989-08-31 | 1991-04-18 | Hughes Aircraft Co | Three-dimensional integrated circuit construction using discrete chip |
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