JP3801902B2 - Multilayer semiconductor device - Google Patents

Multilayer semiconductor device Download PDF

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JP3801902B2
JP3801902B2 JP2001332609A JP2001332609A JP3801902B2 JP 3801902 B2 JP3801902 B2 JP 3801902B2 JP 2001332609 A JP2001332609 A JP 2001332609A JP 2001332609 A JP2001332609 A JP 2001332609A JP 3801902 B2 JP3801902 B2 JP 3801902B2
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substrate
semiconductor device
semiconductor
stacked
connection
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JP2003133520A (en
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義樹 曽田
博行 十楚
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Sharp Corp
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップを有する半導体基板を複数互いに積層した、高機能化及び小型化（薄型化）に有用な積層型半導体装置に関するものである。
【０００２】
【従来の技術】
近年、電子機器の小型化の要求に対応するものとして、また、組立工程の自動化に適合するものとして、ＣＳＰ（Chip Size Package)式の半導体装置が広く用いられている。
【０００３】
これらの半導体装置においては、実装効率を高めるために、半導体装置としてのフィルムキャリア半導体モジュールを複数積み重ね、電気的に接続したマルチチップ半導体装置が特開平１０−１６３４１４号公報に開示されている。
【０００４】
上記マルチチップ半導体装置では、図１２に示すように、半導体チップ７２ａにバンプ７４ａが形成されており、バンプ７４ａとフィルムキャリアテープ７６ａはインナーリード部８０ａで電気的に接続され、アウターリード部８２ａを半導体チップ７２ａの外側に張り出している。
【０００５】
半導体チップ７２ａの上面及びインナーリード部８０ａを含む半導体チップ７２ａの側部には保護コート樹脂８４ａがコートしてある。
【０００６】
スペーサ９０ａには、表面パターン９２ａと裏面パターン９４ａが形成され、両パターンはスルーホール９６ａで電気的につながっており、表面パターン９２ａと前記アウターリード部８２ａは電気的につながっており、フィルムキャリア半導体モジュール８８ａを形成している。
【０００７】
上記において、図１２に示した最下段のフィルムキャリア半導体モジュール８８ａの構成について説明したが、下から第２段目、第３段目、第４段目もほぼ同様の構成であり、最下段のフィルムキャリア半導体モジュールには前記のように符号の後に「ａ」を、また。第２段目には「ｂ」を、第３段目には「ｃ」を、第４段目には「ｄ」をつけて表示する。
【０００８】
互いに隣り合う、例えば各フィルムキャリア半導体モジュール８８ａ、８８ｂ間の電気的な接続は、フィルムキャリア半導体モジュール８８ｂの接続位置における裏面パターン９４ｂ上に、はんだボールを設け、それに対面する位置のフィルムキャリア半導体モジュール８８ａのアウターリード部８２ａと上記はんだボールを当接させ、各フィルムキャリア半導体モジュール８８ａ〜８８ｄを、それらの厚さ方向にて押圧しながら、上記はんだボールが軟化する温度に加熱することにより形成される接続層７８ｂによってなされる。
【０００９】
【発明が解決しようとする課題】
ところが、上記従来では、各フィルムキャリア半導体モジュール８８ａ〜８８ｄを多段にて積層した場合、各接続層７８ｂ、７８ｃ、７８ｄ部分へのストレスが大きくなり、各接続層７８ｂ、７８ｃ、７８ｄや各スペーサ９０ａ〜９０ｄにおいて破断などの強度低下及び電気的な接続不良といった信頼性劣化という問題を生じている。
【００１０】
【課題を解決するための手段】
本発明の積層型半導体装置は、以上の課題を解決するために、それぞれ異なるサイズの半導体チップを搭載するための基板を備えた半導体装置が、２つ以上、上記基板の厚さ方向に互いに積層され、互いに隣り合う各半導体装置間や外部との電気的導通を確保するための接続部が基板上にそれぞれ設けられおり、搭載する半導体チップが大きい基板については、搭載する半導体チップが小さい基板よりも外側にずらして上記各接続部が設けられていることを特徴としている。
【００１１】
上記構成によれば、隣り合う各半導体装置間において、各接続部を基板の表面方向に沿って互いにずらしてそれぞれ設けたので、積層時に各接続部に印加される押圧力（ストレス）が分散されて緩和され、接続部の対応部分やその周囲部分の基板に対する、上記押圧力に起因する破断などの不都合の発生を抑制することが可能となる。さらに、搭載する半導体チップが小さい基板よりも、搭載する半導体チップが大きい基板については、接続部を外側にずらすことによって、互いに隣り合う各半導体装置同士間における、各接続部のずれを大きくすることができる。これにより、積層時に各接続部に印加される押圧力（ストレス）をより一層分散させ緩和させることができる。この結果、上記押圧力に起因する破断などの不都合の発生を抑制することができる。したがって、上記不都合に起因する電気的な接続不良や、機械的な強度不足を回避することができ、信頼性をより一層向上することができる。
【００１２】
本願発明の他の積層型半導体装置は、上記の課題を解決するために、半導体チップと、 半導体チップを保持するための基板とを有する半導体装置が、２つ以上、上記基板の厚さ方向に互いに積層され、互いに隣り合う各半導体装置間や外部との電気的導通を確保するための接続部が基板上にそれぞれ設けられ、上記各接続部の全て又は一部は、隣り合う半導体装置間で基板の表面方向に沿って互いにずらして設けられており、上記各接続部は、外部端子部からなり、最下段の半導体装置における外部端子部は、他の半導体装置における外部端子部の融点より高く設定されていることを特徴としている。
【００１３】
上記の構成によれば、最下段の半導体装置における外部接続部は、他の半導体装置における外部端子部の融点より高く設定されている。したがって、最下段の半導体装置における外部接続部は、その形状を維持することができ、上層の半導体装置を安定して積層することができる。
【００１４】
上記積層型半導体装置では、上記各接続部は、隣り合う半導体装置間で交互にずらして設けられていてもよい。
【００１５】
上記構成によれば、各接続部を、隣り合う半導体装置間で交互にずらして設けたので、各接続部をずらして設けることによる基板の大型化を軽減できる。
【００１６】
上記積層型半導体装置においては、上記各接続部は、隣り合う半導体装置間で順次ずらして設けられていてもよい。
【００１７】
上記構成によれば、各接続部を、隣り合う半導体装置間で順次ずらして設けたから、積層時に各接続部に印加される押圧力（ストレス）の分散をより大きくできて、上記押圧力に起因する破断などの不都合の発生を抑制することがより確実に可能となる。
【００１８】
上記積層型半導体装置では、互いに隣り合う各半導体装置間の各接続部は、上記各半導体装置を離間して互いに機械的に結合するようになっていることが好ましい。
【００１９】
上記積層型半導体装置においては、上記各接続部は、それぞれ略円柱状であり、各接続部の半径以上にて互いにずれていることが望ましい。
【００２０】
上記構成によれば、隣り合う各半導体装置間において、各接続部を基板の表面方向に沿って互いにずらしてそれぞれ設けたので、積層時に各接続部に印加される押圧力（ストレス）が分散されて緩和され、接続部の対応部分やその周囲部分の基板に対する、上記押圧力に起因する破断などの不都合の発生を抑制することが可能となる。
【００２１】
【発明の実施の形態】
本発明の実施の各形態について図１ないし図１１に基づいて説明すれば、以下の通りである。
【００２２】
本発明の積層型半導体装置は、図１に示すように、略長方形板状の半導体装置１を２つ以上、より好ましくは３つ以上、例えば５つ各半導体装置１の厚さ方向に互いに積層して有している。上記半導体装置１は、略長方形板状の基板２と、基板２の中央部上にフリップチップ方式にて搭載された半導体チップ３とを備えている。
【００２３】
基板２の素材としては、シリコン樹脂等の耐薬品性及び耐熱性に優れ、弾性を有するものであればよく、また、グラスファイバーを含ませた強化樹脂であってもよい。半導体チップ３としては、略長方形板状の樹脂製やセラミック製のパッケージに収納されたＣＰＵ(Central Processing Unit)やメモリが挙げられる。
【００２４】
以下では、同一の機能・サイズを有する半導体チップ３を複数用いた例を挙げるが、上記各半導体チップ３は相互に異なる機能やサイズをそれぞれ有していてもよい。
【００２５】
積層する前の半導体装置１の基板２には、図２に示すように、半導体チップ３の搭載部分と相違する位置、例えば上記基板２の周辺部上に、互いに隣り合う上記各半導体装置１を電気的に接続し、かつ機械的に結合するためのランド部４と、外部端子部５とが互いに対応する者同士を電気的に接続して設けられている。
【００２６】
ランド部４は、半導体チップ３を搭載した表面側である第一表面２ａに、かつ互いに隣り合う他の半導体装置１の外部端子部５に対面する位置に設けられている。なお、最上段となる半導体装置１ｅでは、ランド部４の形成を省いてもよい。外部端子部５は、はんだボールからなっており、第一表面２ａの反対面である第二表面２ｂに形成されている。
【００２７】
ランド部４と、外部端子部５との間の電気的な接続は、第一表面２ａ上の配線パターン、第二表面２ｂ上の配線パターン、及び基板２を厚さ方向に貫通したスルーホール部に充填された導電体部を介して行われている。
【００２８】
本発明の積層型半導体装置では、これらのような各半導体装置１をそれらの厚さ方向に互いに重ね合わせ、加熱して（好ましくは押圧しながら）積層したときに、互いに対面した位置のランド部４と、外部端子部５とによって、略円柱状の接続部６がマトリックス状（碁盤の目状）にそれぞれ形成されている。なお、最下段の半導体装置１には、現時点では接続部６とならない外部端子部５が残るが、上記外部端子部５は、後述するように最下段の半導体装置１が外部の実装基板に装着されるときに、接続部６になるので、機能的には接続部６と同等なものとして、以下取り扱うものとする。
【００２９】
上記接続部６の間隔は、特に限定されないが、互いの絶縁状態を維持しながら、全体の小型化を図るために、基板２の表面方向における外部端子部５の直径程度が好ましい。上記間隔が上記直径のとき、上記各接続部６のピッチは、上記直径の２倍程度となる。上記ピッチは、互いに隣り合う上記各接続部６の中心同士の間隔である。このような接続部６によって、積層により隣り合う各半導体装置１は、互いに間隔を有しながら（離間しながら）、電気的に接続され、かつ機械的に結合されている。
【００３０】
そして、上記積層型半導体装置においては、図１及び図２に示すように、互いに隣り合う各半導体装置１同士間（例えば、各半導体装置１ａ、１ｂ同士と、各半導体装置１ｂ、１ｃ同士との間）において、各接続部６は、基板２の表面方向に沿って互いにずらして、つまり相違する位置にそれぞれ設けられている。また、同様に、互いに隣り合う接続部６と外部端子部５とは、基板２の表面方向に沿って互いにずらして、つまり相違する位置にそれぞれ設けられている。
【００３１】
図１では、互いに隣り合う各半導体装置１間での、各接続部６は、基板２の表面方向に沿って部分的に交互の位置のずれ（つまり、例えば１ピッチ分ずつのずれ）となるように、かつ、最下段の半導体装置１ａの外部端子部５が、半導体チップ３より基板２の周辺部に近い外側に配置されている。
【００３２】
なお、上記では、互いに隣り合う各半導体装置１間の各接続部６や、接続部６と外部端子部５とを、互いにずらす方向としては、基板２の辺方向（長手辺方向）に沿った方向である例を挙げたが、上記方向に限定されるものではなく、例えば基板２の短手辺方向に沿った方向であっても、上記短手辺方向に対して傾斜した（例えば４５度）方向であってもよい。
【００３３】
特に、上記の互いにずらす方向が、図３に示すように、上記短手方向（長手方向でも同様）に対して４５度傾斜した積層型半導体装置は、大型化を軽減しながら、各接続部６や、接続部６と外部端子部５とのずれ量をより大きく確保できて、より好ましい。
【００３４】
次に、上記積層型半導体装置の製造方法について説明すると、図２に示すように、ランド部４と外部端子部５とを有する基板２の第一表面２ａ上の配線パターンに対して、半導体チップ３を電気的に接続すると共に上記第一表面２ａ上に固定して搭載して各半導体装置１ａ〜１ｅを作製する。
【００３５】
このとき、各半導体装置１ａ〜１ｅにおける、互いに対面するランド部４と外部端子部５の形成位置を、互いに隣り合う各半導体装置１同士の間において、基板２の表面方向に沿って互いにずらして、つまり相違する位置にそれぞれ設ける。また、最下段の半導体装置１ａにおける外部端子部５の融点は、他の各半導体装置１ｂ〜１ｅにおける外部端子部５の融点より高く設定されている。
【００３６】
続いて、各半導体装置１ａ、１ｂをそれらの厚さ方向に互いに重ね合わせる。
このとき、互いに対面するランド部４と外部端子部５とを当接させる。その後、重ね合わせた各半導体装置１ａ、１ｂを、それらの厚さ方向にて、上記当接部位に押圧力が発生するように押圧しながら、上記各半導体装置１ａ、１ｂ間における外部端子部５が軟化する温度に加熱する。
【００３７】
これにより、上記外部端子部５は、変形して接続部６となると共に上記ランド部４と接着する。一方、最下段の半導体装置１ａにおける外部端子部５は、その融点が、他の各半導体装置１ｂにおける外部端子部５の融点より高く設定されているので、その形状を維持している。その後、各半導体装置１ｃ〜１ｅを順次重ね合わせて、同様に接続部６を形成し、互いに積層させる。
【００３８】
このようにして、重ね合わせた各半導体装置１ａ〜１ｅは、互いに間隔を有しながら（離間しながら）、電気的に接続され、かつ機械的に結合されて互いに積層された積層型半導体装置になる。なお、上記では、順次積層した例を挙げたが、一度に各半導体装置１ａ〜１ｅを互いに重ね合わせて積層してもよい。
【００３９】
上記積層型半導体装置では、各半導体装置１ａ〜１ｅを各接続部６によって互いに例えば並列に接続できるから、積層型半導体装置の実装面積上に複数の半導体チップ３を搭載できて、上記各半導体チップ３の実装効率を向上できる。
【００４０】
また、上記積層型半導体装置においては、互いに隣り合う各半導体装置１間において、各接続部６や、接続部６と外部端子部５とを基板２の表面方向に沿って互いにずらしてそれぞれ設けたので、積層時の各接続部６に印加される押圧力（ストレス）が基板２の弾性によって分散され、上記接続部６の対応部分やその周囲部分の基板２に対する、上記押圧力に起因する破断などの不都合の発生を抑制できる。したがって、上記積層型半導体装置では、上記不都合に起因する電気的な接続不良や、機械的な強度不足を回避できて、信頼性（経時的な信頼性も）を向上できる。
【００４１】
その上、上記積層型半導体装置においては、最下段の半導体装置１ａの外部端子部５を、半導体チップ３より基板２の周辺部に近い外側つまり半導体チップ３に対して遠い位置に配置したので、積層型半導体装置の実装時（加熱時）に、半導体チップ３と基板２との線膨張率の違いによる、半導体チップ３の接続不良といった問題発生を軽減できる。
【００４２】
上記積層型半導体装置では、図４に示すように、最下段の半導体装置１ａの外部端子部５を、基板２の周辺部より半導体チップ３に近い内側つまり半導体チップ３に対して近い位置に配置し、互いに隣り合う各半導体装置１同士間において、各接続部６を交互にずらしてそれぞれ設けた構成としてもよい。
【００４３】
この構成では、押圧力の分散による、信頼性（経時的な信頼性も）の向上を上記と同様に図れると共に、最下段の半導体装置１ａの外部端子部５を、半導体チップ３に対して近い位置に配置したので、上記半導体チップ３の高速動作が可能となる。
【００４４】
また、積層型半導体装置のサイズの大型化が許容できる場合には、図５及び図６に示すように、互いに隣り合う各半導体装置１同士間において、各接続部６を交互に完全にずらして（各接続部６が２列のときは２ピッチ分以上）それぞれ設けた構成としてもよい。図５、図６は、用いた各半導体チップ３のサイズも相違する場合を示す。
【００４５】
このように、互いに隣り合う各半導体装置１同士間における、各接続部６のずれ量が大きくなると、積層時の各接続部６に印加される押圧力（ストレス）が基板２の弾性によってより一層分散され緩和されるので、上記押圧力に起因する破断などの不都合の発生を抑制できる。
【００４６】
したがって、上記積層型半導体装置では、上記不都合に起因する電気的な接続不良や、機械的な強度不足を回避できて、信頼性（経時的な信頼性も）をより一層向上できる。
【００４７】
さらに、図６は、半導体チップ３を、実装基板側である第二表面２ｂ上に設けた例である。この例では、積層型半導体装置を実装基板に装着したとき各半導体チップ３は各基板２によりそれぞれ覆われるので、上記各半導体チップ３の耐久性を向上できる。
【００４８】
一方、図７に示すように、各半導体装置１ｂ〜１ｅの接続部６や、最下段の半導体装置１ａの外部端子部５を、上段から下段に向かって順次内側となるようにに形成してもよく、また、図８に示すように、各半導体装置１ｂ〜１ｅの接続部６や、最下段の半導体装置１ａの外部端子部５を、上段から下段に向かって順次外側となるように形成してもよい。
【００４９】
このときのずらし量は、前述したように、一部がずれる位置でもよいし、完全にずれる位置でもよい。また、互いに隣り合う各半導体装置１同士間における、各接続部６のずれは、上記各接続部６のピッチに制約されるものではなく、図９及び図１０に示すように、ハーフピッチ量だけでもよい。
【００５０】
また、上記では、半導体チップ３を、基板２上にフリップチップ方式にて搭載した半導体装置１を用いた例を挙げたが、例えば図１１に示す、ワイヤボンディング方式にて搭載した半導体装置１１を上記半導体装置１に代えて用いて本発明の積層型半導体装置を作製できる。
【００５１】
上記半導体装置１１は、Ｃｕ箔により配線パターンが形成された基板１２の中央部に設けられた貫通開口部１２ａ内に半導体チップ１３を仮固定し、半導体チップ１３と基板１２の配線パターンとをＡｕワイヤ１７により接続し、貫通開口部１２ａ内に半導体チップ１３をトランスファーモールド法により封止した樹脂封止部１８を形成し、外部端子部５としては、はんだボールをリフロー処理により基板１２上に形成してなるものである。
【００５２】
また、半導体装置１１では、積層用のために、さらに、前述のランド部４とスルーホール１２ｂとを有している。上記スルーホール１２ｂは、互いに対応するランド部４と外部端子部５とを電気的に接続するために、基板１２をその厚さ方向に貫通するように設けられている。上記スルーホール１２ｂには、アルミニウムや銅のような導電体が充填されている。上記導電体における外部端子部５の形成面とは反対側の露出端面は、ランド部４となっている。
【００５３】
【発明の効果】
本発明の積層型半導体装置は、以上のように、それぞれ異なるサイズの半導体チップを搭載するための基板を備えた半導体装置が、２つ以上、上記基板の厚さ方向に互いに積層され、互いに隣り合う各半導体装置間や外部との電気的導通を確保するための接続部が基板上にそれぞれ設けられおり、搭載する半導体チップが大きい基板については、搭載する半導体チップが小さい基板よりも外側にずらして上記各接続部が設けられていることを特徴としている。
【００５４】
それゆえ、上記構成は、隣り合う各半導体装置間において、各接続部を基板の表面方向に沿って互いにずらしてそれぞれ設けたので、積層時に各接続部に印加される押圧力（ストレス）が分散され、上記接続部の対応部分やその周囲部分の基板に対する、上記押圧力に起因する破断などの不都合の発生を抑制することが可能となる。
【００５５】
したがって、上記構成では、上記不都合に起因する電気的な接続不良や、機械的な強度不足を回避できて、信頼性（経時的な信頼性も）を向上できるという効果を奏する。さらに、搭載する半導体チップが小さい基板よりも、搭載する半導体チップが大きい基板については、接続部を外側にずらすことによって、互いに隣り合う各半導体装置同士間における、各接続部のずれを大きくすることができる。これにより、積層時に各接続部に印加される押圧力（ストレス）をより一層分散させ緩和させることができる。この結果、上記押圧力に起因する破断などの不都合の発生を抑制することができる。したがって、上記不都合に起因する電気的な接続不良や、機械的な強度不足を回避することができ、信頼性をより一層向上することができる。
【００５６】
本願発明の他の積層型半導体装置は、半導体チップと、半導体チップを保持するための基板とを有する半導体装置が、２つ以上、上記基板の厚さ方向に互いに積層され、互いに隣り合う各半導体装置間や外部との電気的導通を確保するための接続部が基板上にそれぞれ設けられ、上記各接続部の全て又は一部は、隣り合う半導体装置間で基板の表面方向に沿って互いにずらして設けられており、上記各接続部は、外部端子部からなり、最下段の半導体装置における外部端子部は、他の半導体装置における外部端子部の融点より高く設定されていることを特徴としている。
【００５７】
これにより、最下段の半導体装置における外部接続部は、他の半導体装置における外部端子部の融点より高く設定されている。したがって、最下段の半導体装置における外部接続部は、その形状を維持することができ、上層の半導体装置を安定して積層することができるという効果を奏する。
【図面の簡単な説明】
【図１】 本発明の積層型半導体装置の正面構成図である。
【図２】 上記積層型半導体装置の製造工程を示す分解正面構成図である。
【図３】 上記積層型半導体装置の一変形例を示す平面構成図である。
【図４】 上記積層型半導体装置の他の変形例を示す正面構成図である。
【図５】 上記積層型半導体装置のさらに他の変形例を示す正面構成図である。
【図６】 上記積層型半導体装置のさらに他の変形例を示す正面構成図である。
【図７】 上記積層型半導体装置のさらに他の変形例を示す正面構成図である。
【図８】 上記積層型半導体装置のさらに他の変形例を示す正面構成図である。
【図９】 上記積層型半導体装置のさらに他の変形例を示す平面構成図である。
【図１０】 上記変形例の正面構成図である。
【図１１】 上記積層型半導体装置のさらに他の変形例を示す構成図であって、（ａ）は平面図、（ｂ）は正面図、（ｃ）裏面図である。
【図１２】 従来のマルチチップ半導体装置を示す正面構成図である。
【符号の説明】
１ 半導体装置
２ 基板
３ 半導体チップ
６ 接続部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a stacked semiconductor device that is useful for high functionality and downsizing (thinning), in which a plurality of semiconductor substrates having semiconductor chips are stacked on each other.
[0002]
[Prior art]
2. Description of the Related Art In recent years, CSP (Chip Size Package) type semiconductor devices have been widely used to meet the demand for downsizing electronic devices and to be compatible with automation of assembly processes.
[0003]
In these semiconductor devices, a multi-chip semiconductor device in which a plurality of film carrier semiconductor modules as semiconductor devices are stacked and electrically connected is disclosed in JP-A-10-163414 in order to increase mounting efficiency.
[0004]
In the multichip semiconductor device, as shown in FIG. 12, the bump 74a is formed on the semiconductor chip 72a, and the bump 74a and the film carrier tape 76a are electrically connected by the inner lead portion 80a, and the outer lead portion 82a is connected. It protrudes outside the semiconductor chip 72a.
[0005]
The upper surface of the semiconductor chip 72a and the side portion of the semiconductor chip 72a including the inner lead portion 80a are coated with a protective coating resin 84a.
[0006]
A surface pattern 92a and a back surface pattern 94a are formed on the spacer 90a. Both patterns are electrically connected through a through hole 96a. The surface pattern 92a and the outer lead portion 82a are electrically connected. A module 88a is formed.
[0007]
In the above, the configuration of the lowermost film carrier semiconductor module 88a shown in FIG. 12 has been described, but the second, third, and fourth stages from the bottom are also substantially the same, and the lowermost stage. As described above, “a” is also added to the film carrier semiconductor module. The second row is displayed with “b”, the third row with “c”, and the fourth row with “d”.
[0008]
For example, the electrical connection between the film carrier semiconductor modules 88a and 88b adjacent to each other is such that a solder ball is provided on the back surface pattern 94b at the connection position of the film carrier semiconductor module 88b, and the film carrier semiconductor module at a position facing it. The outer lead portion 82a of 88a and the solder ball are brought into contact with each other, and the film carrier semiconductor modules 88a to 88d are pressed in their thickness direction and heated to a temperature at which the solder ball is softened. The connection layer 78b is used.
[0009]
[Problems to be solved by the invention]
However, in the above conventional case, when the film carrier semiconductor modules 88a to 88d are laminated in multiple stages, the stress on the connection layers 78b, 78c and 78d increases, and the connection layers 78b, 78c and 78d and the spacers 90a are increased. At ~ 90d, there is a problem of reliability deterioration such as strength reduction such as fracture and poor electrical connection.
[0010]
[Means for Solving the Problems]
In order to solve the above-described problems, the stacked semiconductor device of the present invention includes two or more semiconductor devices each having a substrate for mounting semiconductor chips of different sizes, stacked in the thickness direction of the substrate. In addition, connecting portions for ensuring electrical continuity between semiconductor devices adjacent to each other and to the outside are provided on the substrate, respectively. For a substrate with a large semiconductor chip to be mounted, a semiconductor chip to be mounted is smaller than a substrate with a small size. Further, the above-described connecting portions are provided so as to be shifted outward.
[0011]
According to the above configuration, the connecting portions are provided so as to be shifted from each other along the surface direction of the substrate between adjacent semiconductor devices, so that the pressing force (stress) applied to each connecting portion at the time of stacking is dispersed. Thus, it is possible to suppress the occurrence of inconvenience such as breakage due to the pressing force with respect to the corresponding portion of the connecting portion and the substrate in the surrounding portion. Furthermore, for a substrate with a large semiconductor chip to be mounted over a substrate with a small semiconductor chip to be mounted, the displacement of each connection portion between adjacent semiconductor devices can be increased by shifting the connection portion outward. Can do. Thereby, the pressing force (stress) applied to each connection part at the time of lamination | stacking can be further disperse | distributed and relieve | moderated. As a result, the occurrence of inconveniences such as breakage due to the pressing force can be suppressed. Therefore, it is possible to avoid poor electrical connection and insufficient mechanical strength due to the above inconvenience, and the reliability can be further improved.
[0012]
In order to solve the above-described problem, another stacked semiconductor device of the present invention includes two or more semiconductor devices each having a semiconductor chip and a substrate for holding the semiconductor chip in the thickness direction of the substrate. Connection portions for securing electrical continuity between semiconductor devices adjacent to each other and the outside are provided on the substrate, respectively, and all or part of the connection portions are connected between adjacent semiconductor devices. They are provided so as to be shifted from each other along the surface direction of the substrate, and each of the connection parts comprises an external terminal part, and the external terminal part in the lowermost semiconductor device is higher than the melting point of the external terminal part in the other semiconductor device. It is characterized by being set.
[0013]
According to said structure, the external connection part in the semiconductor device of the lowest stage is set higher than melting | fusing point of the external terminal part in another semiconductor device. Therefore, the shape of the external connection portion in the lowermost semiconductor device can be maintained, and the upper semiconductor device can be stacked stably.
[0014]
In the stacked semiconductor device, the connection portions may be alternately shifted between adjacent semiconductor devices.
[0015]
According to the above configuration, since the connection portions are alternately shifted between the adjacent semiconductor devices, the increase in size of the substrate due to the shift of the connection portions can be reduced.
[0016]
In the stacked semiconductor device, the connection portions may be sequentially shifted between adjacent semiconductor devices.
[0017]
According to the above configuration, since each connection portion is sequentially shifted between adjacent semiconductor devices, the dispersion of the pressing force (stress) applied to each connection portion at the time of stacking can be further increased. It is possible to more reliably suppress the occurrence of inconvenience such as breaking.
[0018]
In the stacked semiconductor device, it is preferable that connection portions between adjacent semiconductor devices are mechanically coupled to each other with the semiconductor devices separated from each other.
[0019]
In the stacked semiconductor device, it is desirable that the connection portions are substantially columnar and are displaced from each other by a radius equal to or larger than the radius of each connection portion.
[0020]
According to the above configuration, the connecting portions are provided so as to be shifted from each other along the surface direction of the substrate between adjacent semiconductor devices, so that the pressing force (stress) applied to each connecting portion at the time of stacking is dispersed. Thus, it is possible to suppress the occurrence of inconvenience such as breakage due to the pressing force with respect to the corresponding portion of the connecting portion and the substrate in the surrounding portion.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Each embodiment of the present invention will be described with reference to FIGS. 1 to 11 as follows.
[0022]
As shown in FIG. 1, the stacked semiconductor device of the present invention has two or more, more preferably three or more, for example, five, substantially rectangular plate-like semiconductor devices 1 stacked in the thickness direction of each semiconductor device 1. Have. The semiconductor device 1 includes a substantially rectangular plate-like substrate 2 and a semiconductor chip 3 mounted on the central portion of the substrate 2 by a flip chip method.
[0023]
The material of the substrate 2 may be any material that is excellent in chemical resistance and heat resistance, such as silicon resin, and has elasticity, and may be a reinforced resin containing glass fiber. Examples of the semiconductor chip 3 include a CPU (Central Processing Unit) and a memory housed in a substantially rectangular plate-shaped resin or ceramic package.
[0024]
In the following, an example in which a plurality of semiconductor chips 3 having the same function and size are used will be described. However, the semiconductor chips 3 may have different functions and sizes.
[0025]
As shown in FIG. 2, the semiconductor devices 1 adjacent to each other are placed on the substrate 2 of the semiconductor device 1 before being stacked, at positions different from the mounting portion of the semiconductor chip 3, for example, on the periphery of the substrate 2. A land portion 4 for electrical connection and mechanical coupling and an external terminal portion 5 are provided by electrically connecting persons corresponding to each other.
[0026]
The land portion 4 is provided on the first surface 2a which is the surface side on which the semiconductor chip 3 is mounted, and at a position facing the external terminal portion 5 of another semiconductor device 1 adjacent to each other. Note that the formation of the land portion 4 may be omitted in the uppermost semiconductor device 1e. The external terminal portion 5 is made of a solder ball and is formed on the second surface 2b that is the opposite surface of the first surface 2a.
[0027]
The electrical connection between the land portion 4 and the external terminal portion 5 includes a wiring pattern on the first surface 2a, a wiring pattern on the second surface 2b, and a through-hole portion penetrating the substrate 2 in the thickness direction. It is carried out through a conductor portion filled in.
[0028]
In the stacked semiconductor device according to the present invention, when such semiconductor devices 1 are stacked on each other in the thickness direction and stacked by heating (preferably pressing), land portions at positions facing each other are stacked. 4 and the external terminal portion 5 form a substantially columnar connection portion 6 in a matrix (a grid pattern). In addition, although the external terminal part 5 which does not become the connection part 6 remains at the present time in the lowermost semiconductor device 1, the lowermost semiconductor device 1 is mounted on an external mounting substrate as described later. Since it becomes the connection part 6 when it is done, it shall be handled below as functionally equivalent to the connection part 6.
[0029]
The interval between the connecting portions 6 is not particularly limited, but is preferably about the diameter of the external terminal portion 5 in the surface direction of the substrate 2 in order to reduce the overall size while maintaining mutual insulation. When the distance is the diameter, the pitch of the connection portions 6 is about twice the diameter. The pitch is an interval between the centers of the connecting portions 6 adjacent to each other. By such a connection portion 6, the semiconductor devices 1 adjacent to each other by stacking are electrically connected and mechanically coupled while being spaced apart from each other.
[0030]
In the stacked semiconductor device, as shown in FIGS. 1 and 2, the semiconductor devices 1 adjacent to each other (for example, between the semiconductor devices 1a and 1b and between the semiconductor devices 1b and 1c). In the meantime, the connecting portions 6 are provided so as to be shifted from each other along the surface direction of the substrate 2, that is, at different positions. Similarly, the connection portion 6 and the external terminal portion 5 that are adjacent to each other are shifted from each other along the surface direction of the substrate 2, that is, provided at different positions.
[0031]
In FIG. 1, the connection portions 6 between the semiconductor devices 1 adjacent to each other are partially shifted in position along the surface direction of the substrate 2 (that is, for example, a shift of one pitch). As described above, the external terminal portion 5 of the lowermost semiconductor device 1 a is arranged outside the semiconductor chip 3 and closer to the peripheral portion of the substrate 2.
[0032]
In the above description, the direction of shifting the connection portions 6 between the semiconductor devices 1 adjacent to each other and the connection portions 6 and the external terminal portions 5 along the side direction (longitudinal side direction) of the substrate 2. Although the example which is a direction was given, it is not limited to the said direction, For example, even if it was the direction along the short side direction of the board | substrate 2, it inclined with respect to the said short side direction (for example, 45 degree | times) ) Direction.
[0033]
In particular, as shown in FIG. 3, the stacked semiconductor device in which the above-described shifting directions are inclined by 45 degrees with respect to the short direction (the same applies to the longitudinal direction) can reduce each of the connecting portions 6 while reducing the size. In addition, the displacement amount between the connection portion 6 and the external terminal portion 5 can be secured larger, which is more preferable.
[0034]
Next, the manufacturing method of the laminated semiconductor device will be described. As shown in FIG. 2, a semiconductor chip is formed on the wiring pattern on the first surface 2a of the substrate 2 having the land portion 4 and the external terminal portion 5. 3 are electrically connected and fixed and mounted on the first surface 2a to manufacture the semiconductor devices 1a to 1e.
[0035]
At this time, the formation positions of the land portions 4 and the external terminal portions 5 facing each other in each of the semiconductor devices 1 a to 1 e are shifted from each other along the surface direction of the substrate 2 between the adjacent semiconductor devices 1. That is, they are provided at different positions. The melting point of the external terminal portion 5 in the lowermost semiconductor device 1a is set higher than the melting point of the external terminal portion 5 in each of the other semiconductor devices 1b to 1e.
[0036]
Subsequently, the semiconductor devices 1a and 1b are overlapped with each other in the thickness direction.
At this time, the land portion 4 and the external terminal portion 5 facing each other are brought into contact with each other. Thereafter, the external terminal portions 5 between the semiconductor devices 1a and 1b are pressed while pressing the stacked semiconductor devices 1a and 1b in the thickness direction so that a pressing force is generated at the contact portion. Heat to a temperature that softens.
[0037]
As a result, the external terminal portion 5 is deformed to become the connection portion 6 and is bonded to the land portion 4. On the other hand, since the melting point of the external terminal portion 5 in the lowermost semiconductor device 1a is set higher than the melting point of the external terminal portion 5 in each of the other semiconductor devices 1b, the shape is maintained. Thereafter, the semiconductor devices 1c to 1e are sequentially overlapped to form the connection portion 6 in the same manner and are stacked on each other .
[0038]
In this way, the stacked semiconductor devices 1a to 1e are electrically connected and mechanically coupled to each other so as to be stacked on each other while being spaced apart from each other. Become. In addition, although the example which laminated | stacked sequentially was given above, each semiconductor device 1a-1e may be laminated | stacked on each other at once.
[0039]
In the stacked semiconductor device, since the semiconductor devices 1a to 1e can be connected to each other in parallel, for example, by the connecting portions 6, a plurality of semiconductor chips 3 can be mounted on the mounting area of the stacked semiconductor device. 3 mounting efficiency can be improved.
[0040]
Further, in the stacked semiconductor device described above, the connecting portions 6 and the connecting portions 6 and the external terminal portions 5 are provided so as to be shifted from each other along the surface direction of the substrate 2 between the adjacent semiconductor devices 1. Therefore, the pressing force (stress) applied to each connection portion 6 at the time of lamination is dispersed by the elasticity of the substrate 2, and the breakage caused by the pressing force with respect to the corresponding portion of the connection portion 6 and the peripheral portion of the substrate 2. The occurrence of inconvenience such as can be suppressed. Therefore, in the laminated semiconductor device, it is possible to avoid electrical connection failure and mechanical strength deficiency due to the above disadvantages, and to improve reliability (and reliability over time).
[0041]
In addition, in the stacked semiconductor device, the external terminal portion 5 of the lowermost semiconductor device 1a is disposed outside the semiconductor chip 3 nearer to the periphery of the substrate 2, that is, at a position far from the semiconductor chip 3. When the stacked semiconductor device is mounted (at the time of heating), it is possible to reduce the occurrence of problems such as poor connection of the semiconductor chip 3 due to the difference in linear expansion coefficient between the semiconductor chip 3 and the substrate 2.
[0042]
In the stacked semiconductor device, as shown in FIG. 4, the external terminal portion 5 of the lowermost semiconductor device 1 a is disposed closer to the semiconductor chip 3 than the peripheral portion of the substrate 2, that is, closer to the semiconductor chip 3. However, the connection portions 6 may be alternately shifted between the adjacent semiconductor devices 1.
[0043]
In this configuration, the reliability (and reliability over time) can be improved by the dispersion of the pressing force in the same manner as described above, and the external terminal portion 5 of the lowermost semiconductor device 1a is close to the semiconductor chip 3. Since the semiconductor chip 3 is disposed at the position, the semiconductor chip 3 can be operated at high speed.
[0044]
Further, when the size of the stacked semiconductor device can be increased, as shown in FIGS. 5 and 6, the connection portions 6 are alternately and completely shifted between the adjacent semiconductor devices 1. (When each connection part 6 is two rows, it is 2 pitches or more) It is good also as a structure each provided. 5 and 6 show cases where the sizes of the used semiconductor chips 3 are also different.
[0045]
As described above, when the displacement amount of each connection portion 6 between the adjacent semiconductor devices 1 increases, the pressing force (stress) applied to each connection portion 6 at the time of stacking is further increased by the elasticity of the substrate 2. Since it is dispersed and relaxed, it is possible to suppress the occurrence of inconvenience such as breakage due to the pressing force.
[0046]
Therefore, in the stacked semiconductor device, it is possible to avoid electrical connection failure and mechanical strength deficiency due to the above disadvantages, and further improve reliability (and reliability over time).
[0047]
Furthermore, FIG. 6 is an example in which the semiconductor chip 3 is provided on the second surface 2b on the mounting substrate side. In this example, since each semiconductor chip 3 is covered with each substrate 2 when the stacked semiconductor device is mounted on the mounting substrate, the durability of each semiconductor chip 3 can be improved.
[0048]
On the other hand, as shown in FIG. 7, the connection portions 6 of the respective semiconductor devices 1b to 1e and the external terminal portions 5 of the lowermost semiconductor device 1a are formed so as to be sequentially inward from the upper stage to the lower stage. Further, as shown in FIG. 8, the connection portions 6 of the semiconductor devices 1b to 1e and the external terminal portions 5 of the lowermost semiconductor device 1a are formed so as to be sequentially outward from the upper stage toward the lower stage. May be.
[0049]
As described above, the shift amount at this time may be a position where a part is shifted or a position where it is completely shifted. Further, the displacement of the connection portions 6 between the semiconductor devices 1 adjacent to each other is not limited by the pitch of the connection portions 6, but only a half pitch amount as shown in FIGS. But you can.
[0050]
In the above example, the semiconductor device 1 in which the semiconductor chip 3 is mounted on the substrate 2 by the flip chip method is used. However, for example, the semiconductor device 11 mounted by the wire bonding method illustrated in FIG. It can replace with the said semiconductor device 1 and can produce the laminated semiconductor device of this invention.
[0051]
In the semiconductor device 11, the semiconductor chip 13 is temporarily fixed in the through opening 12a provided in the central portion of the substrate 12 on which the wiring pattern is formed by the Cu foil, and the wiring pattern of the semiconductor chip 13 and the substrate 12 is Au. A resin sealing portion 18 is formed by connecting with a wire 17 and sealing the semiconductor chip 13 in the through-opening portion 12a by a transfer molding method. As the external terminal portion 5, a solder ball is formed on the substrate 12 by a reflow process. It is made.
[0052]
Further, the semiconductor device 11 further includes the land portion 4 and the through hole 12b described above for stacking. The through hole 12b is provided so as to penetrate the substrate 12 in the thickness direction in order to electrically connect the land portion 4 and the external terminal portion 5 corresponding to each other. The through hole 12b is filled with a conductor such as aluminum or copper. The exposed end surface of the conductor opposite to the surface on which the external terminal portion 5 is formed is a land portion 4.
[0053]
【The invention's effect】
In the stacked semiconductor device of the present invention , as described above, two or more semiconductor devices each including a substrate for mounting semiconductor chips of different sizes are stacked on each other in the thickness direction of the substrate and adjacent to each other. Connection parts for ensuring electrical continuity between the respective semiconductor devices and the outside are provided on the substrate, respectively. For a substrate with a large semiconductor chip to be mounted, the semiconductor chip to be mounted is shifted outward from a substrate with a small size. The above-described connection portions are provided.
[0054]
Therefore, in the above configuration, each connection portion is provided to be shifted from each other along the surface direction of the substrate between adjacent semiconductor devices, so that the pressing force (stress) applied to each connection portion during stacking is dispersed. In addition, it is possible to suppress the occurrence of inconvenience such as breakage due to the pressing force with respect to the corresponding portion of the connection portion and the peripheral portion of the substrate.
[0055]
Therefore, with the above configuration, it is possible to avoid poor electrical connection and insufficient mechanical strength due to the above disadvantages, and to improve the reliability (and reliability over time). Furthermore, for a substrate with a large semiconductor chip to be mounted over a substrate with a small semiconductor chip to be mounted, the displacement of each connection portion between adjacent semiconductor devices can be increased by shifting the connection portion outward. Can do. Thereby, the pressing force (stress) applied to each connection part at the time of lamination | stacking can be further disperse | distributed and relieve | moderated. As a result, the occurrence of inconveniences such as breakage due to the pressing force can be suppressed. Therefore, it is possible to avoid poor electrical connection and insufficient mechanical strength due to the above inconvenience, and the reliability can be further improved.
[0056]
According to another stacked semiconductor device of the present invention , two or more semiconductor devices each having a semiconductor chip and a substrate for holding the semiconductor chip are stacked in the thickness direction of the substrate and adjacent to each other. Connection portions for ensuring electrical continuity between devices and the outside are provided on the substrate, respectively, and all or a part of each of the connection portions are shifted from each other along the surface direction of the substrate between adjacent semiconductor devices. Each of the connection parts is composed of an external terminal part, and the external terminal part in the lowermost semiconductor device is set higher than the melting point of the external terminal part in the other semiconductor device. .
[0057]
Thereby, the external connection part in the lowermost semiconductor device is set higher than the melting point of the external terminal part in the other semiconductor device. Therefore, the external connection portion of the lowermost semiconductor device can maintain its shape, and the upper semiconductor device can be stably stacked.
[Brief description of the drawings]
FIG. 1 is a front view of a stacked semiconductor device according to the present invention.
FIG. 2 is an exploded front view showing the manufacturing process of the stacked semiconductor device.
FIG. 3 is a plan view showing a modification of the stacked semiconductor device.
FIG. 4 is a front configuration diagram showing another modification of the stacked semiconductor device.
FIG. 5 is a front configuration diagram showing still another modification of the stacked semiconductor device.
FIG. 6 is a front configuration diagram showing still another modified example of the stacked semiconductor device.
FIG. 7 is a front configuration diagram showing still another modification of the stacked semiconductor device.
FIG. 8 is a front configuration diagram showing still another modification of the stacked semiconductor device.
FIG. 9 is a plan configuration diagram showing still another modification of the stacked semiconductor device.
FIG. 10 is a front configuration diagram of the modified example.
11A and 11B are configuration diagrams showing still another modification of the stacked semiconductor device, wherein FIG. 11A is a plan view, FIG. 11B is a front view, and FIG.
FIG. 12 is a front configuration diagram showing a conventional multichip semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Board | substrate 3 Semiconductor chip 6 Connection part

Claims (6)

それぞれ異なるサイズの半導体チップを搭載するための基板を備えた半導体装置が、２つ以上、上記基板の厚さ方向に互いに積層され、
互いに隣り合う各半導体装置間や外部との電気的導通を確保するための接続部が基板上にそれぞれ設けられおり、
搭載する半導体チップが大きい基板については、搭載する半導体チップが小さい基板よりも外側にずらして上記各接続部が設けられていることを特徴とする積層型半導体装置。 Two or more semiconductor devices each having a substrate for mounting semiconductor chips of different sizes are stacked on each other in the thickness direction of the substrate,
Connection portions for ensuring electrical continuity between semiconductor devices adjacent to each other and the outside are provided on the substrate, respectively.
A stacked semiconductor device characterized in that a substrate having a large semiconductor chip to be mounted is provided with the connection portions shifted outward from a substrate having a small semiconductor chip to be mounted. 半導体チップと、半導体チップを保持するための基板とを有する半導体装置が、２つ以上、上記基板の厚さ方向に互いに積層され、Two or more semiconductor devices having a semiconductor chip and a substrate for holding the semiconductor chip are stacked on each other in the thickness direction of the substrate,
互いに隣り合う各半導体装置間や外部との電気的導通を確保するための接続部が基板上にそれぞれ設けられ、Connection parts for ensuring electrical continuity between each semiconductor device adjacent to each other and the outside are provided on the substrate, respectively.
上記各接続部の全て又は一部は、隣り合う半導体装置間で基板の表面方向に沿って互いにずらして設けられており、All or a part of each of the connection parts is provided to be shifted from each other along the surface direction of the substrate between adjacent semiconductor devices,
上記各接続部は、外部端子部からなり、最下段の半導体装置における外部端子部は、他の半導体装置における外部端子部の融点より高く設定されていることを特徴とする積層型半導体装置。Each of the connection parts comprises an external terminal part, and the external terminal part in the lowermost semiconductor device is set higher than the melting point of the external terminal part in another semiconductor device. 上記各接続部は、隣り合う半導体装置間で交互にずらして設けられていることを特徴とする請求項１または２記載の積層型半導体装置。 3. The stacked semiconductor device according to claim 1, wherein each of the connecting portions is provided by being alternately shifted between adjacent semiconductor devices . 上記各接続部は、隣り合う半導体装置間で順次ずらして設けられていることを特徴とする請求項１または２記載の積層型半導体装置。 3. The stacked semiconductor device according to claim 1, wherein each of the connection portions is sequentially shifted between adjacent semiconductor devices . 互いに隣り合う各半導体装置間の各接続部は、上記各半導体装置を離間して互いに機械的に結合するようになっていることを特徴とする請求項１ないし４の何れか１項に記載の積層型半導体装置。 5. The connection part according to claim 1, wherein each connection part between adjacent semiconductor devices is mechanically coupled to each other with the semiconductor devices being separated from each other. Stacked semiconductor device . 上記各接続部は、それぞれ略円柱状であり、各接続部の半径以上にて互いにずれていることを特徴とする請求項１ないし５の何れか１項に記載の積層型半導体装置。 6. The stacked semiconductor device according to claim 1, wherein each of the connection portions has a substantially columnar shape and is displaced from each other by a radius greater than or equal to each connection portion .
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