JPS6366427B2 - - Google Patents

Info

Publication number
JPS6366427B2
JPS6366427B2 JP56203754A JP20375481A JPS6366427B2 JP S6366427 B2 JPS6366427 B2 JP S6366427B2 JP 56203754 A JP56203754 A JP 56203754A JP 20375481 A JP20375481 A JP 20375481A JP S6366427 B2 JPS6366427 B2 JP S6366427B2
Authority
JP
Japan
Prior art keywords
plating film
silver plating
lead frame
leads
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56203754A
Other languages
Japanese (ja)
Other versions
JPS58106853A (en
Inventor
Usuke Enomoto
Hisayoshi Chigira
Kunio Tsushima
Haruo Kugimya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56203754A priority Critical patent/JPS58106853A/en
Publication of JPS58106853A publication Critical patent/JPS58106853A/en
Publication of JPS6366427B2 publication Critical patent/JPS6366427B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造に用いるリードフレ
ームに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead frame used for manufacturing semiconductor devices.

レジンモールド型の半導体装置の製造において
は、一般にリードフレームが用いられている。リ
ードフレームは、銅や鉄―ニツケル系等の薄い金
属板を精密プレスやエツチング加工でパターニン
グすることによつて形成され、電気回路素子（ペ
レツト）を取り付けるタブおよびワイヤを取り付
けるリードを有している。タブおよびリードの接
続面（ボンデイング面）は接続性向上のために、
一般に銀メツキ膜で被つている。銀メツキ膜にあ
つては、光沢メツキ膜は接続性が悪いことから、
従来、この銀メツキ膜は接続性（ボンダビリテ
イ）の良好な純銀からなる無光沢メツキによつて
形成している。 Lead frames are generally used in the manufacture of resin mold type semiconductor devices. A lead frame is formed by patterning a thin metal plate such as copper or iron-nickel using precision pressing or etching, and has tabs for attaching electrical circuit elements (pellets) and leads for attaching wires. . The connection surface (bonding surface) of the tab and lead is
It is generally covered with a silver plating film. Regarding silver plating film, since glossy plating film has poor connectivity,
Conventionally, this silver plating film is formed by matte plating made of pure silver with good connectivity (bondability).

しかし、この無光沢メツキ膜はボンダビリテイ
は高いが下地保護性が低く、リードフレーム母材
（素材）の酸化防止性が低い。このため、下地保
護性を良好とするためには無光沢メツキ膜を最小
2.0μm（製造時の厚さバラツキを考慮した場合、
3.5μm）必要とし、銀使用量の多さからしてリー
ドフレームコストが高くなる難点がある。 However, although this matte plating film has high bondability, it has low ability to protect the base and has low ability to prevent oxidation of the lead frame base material (material). Therefore, in order to provide good protection for the base, the matte plating film should be kept to a minimum.
2.0μm (taking into account thickness variations during manufacturing,
3.5 μm), and the lead frame cost is high due to the large amount of silver used.

したがつて、本発明の目的は下地保護性、接続
性が高くかつ銀使用量の少ない製造コストの安い
リードフレームを提供することにある。 Accordingly, an object of the present invention is to provide a lead frame that has high base protection properties and high connectivity, uses a small amount of silver, and is inexpensive to manufacture.

このような目的を達成するために本発明は、金
属素材の主面に銀メツキ膜を形成してなるリード
フレームにおいて、前記金属素材の主面に直接ま
たは他の金属を介して光沢銀メツキ膜を形成する
とともに、この光沢銀メツキ膜上に無光沢銀メツ
キ膜を形成してなるものであつて、以下実施例に
より本発明を説明する。 In order to achieve such an object, the present invention provides a lead frame in which a silver plating film is formed on the main surface of a metal material, in which a bright silver plating film is formed on the main surface of the metal material directly or through another metal. The present invention will be described below with reference to Examples.

第１図は本発明の一実施例によるレジンモール
ド型トランジスタ用のリードフレームを示す平面
図であり、第２図は第１図の―線に沿う一部
の拡大断面図である。第１図に示すように、この
リードフレーム１の単位ブロツクは、それぞれ先
端が幅広となる細長の３本のリード２〜４と、こ
れらリード２〜４を連結する外枠５およびダム片
６とからなつている。各リード２〜４は相互に平
行となるとともに、後端部分でリード２〜４に直
交する方向に延在する外枠５によつて連結されて
いる。ダム片６は前記外枠５に平行に延びるとと
もに、各リード２〜４の中間部で連結され、外枠
５とともにリード２〜４を支持する補強部材とな
つている。また、ダム片６はレジンモールド時の
レジンの流出を防止するダムの働きをする。 FIG. 1 is a plan view showing a lead frame for a resin-molded transistor according to an embodiment of the present invention, and FIG. 2 is an enlarged cross-sectional view of a portion taken along the line -- in FIG. As shown in FIG. 1, the unit block of this lead frame 1 includes three elongated leads 2 to 4 each having a wide tip, an outer frame 5 and a dam piece 6 that connect these leads 2 to 4. It is made up of The leads 2 to 4 are parallel to each other and connected at their rear end portions by an outer frame 5 extending in a direction perpendicular to the leads 2 to 4. The dam piece 6 extends parallel to the outer frame 5 and is connected to each of the leads 2 to 4 at the intermediate portion thereof, and serves as a reinforcing member that supports the leads 2 to 4 together with the outer frame 5. Further, the dam piece 6 functions as a dam to prevent resin from flowing out during resin molding.

一方、中央のリード３はコレクタ用リードとな
り、先端の幅広部は電気回路素子（ペレツト）７
を取り付けるタブ８を形作つている。両側のリー
ド２，４はエミツタ用リードあるいはベース用リ
ードとなり、それぞれ先端の幅広部はワイヤ９を
接続するパツド１０を形作つている。また、この
リードフレーム１は第２図に示すように、母材１
１はたとえば0.45mmの厚さの銅板からなるととも
に、タブ８およびリード２，４のパツド１０表面
には光沢銀メツキ膜１２を介して無光沢銀メツキ
膜１３が形成されている。光沢銀メツキ膜１２は
銀にアンチモン（Sb）を含有させたものであり、
その厚さはたとえば1.3μmとなつていて、その膜
は緻密となり、下地（母材）保護性が高い。ま
た、無光沢銀メツキ膜１３は純銀からなり、その
厚さはたとえば0.2μmと薄い。この無光沢銀メツ
キ膜１３は表面が鏡面とならず微視的に見れば凹
凸が多いことから、ペレツト７やワイヤ９との接
続性が高い。 On the other hand, the lead 3 in the center is a collector lead, and the wide part at the tip is the electrical circuit element (pellet) 7.
Forms a tab 8 for attaching. The leads 2 and 4 on both sides serve as emitter leads or base leads, and the wide portions at their tips form pads 10 to which wires 9 are connected. In addition, this lead frame 1 has a base material 1 as shown in FIG.
1 is made of a copper plate having a thickness of, for example, 0.45 mm, and a matte silver plating film 13 is formed on the surface of the tab 8 and the pad 10 of the leads 2 and 4 with a bright silver plating film 12 interposed therebetween. The bright silver plating film 12 is made of silver containing antimony (Sb),
The thickness is, for example, 1.3 μm, and the film is dense and highly protective of the base material. Further, the matte silver plating film 13 is made of pure silver, and its thickness is as thin as, for example, 0.2 μm. Since the surface of this matte silver plating film 13 is not mirror-like and has many irregularities when viewed microscopically, it has high connectivity with the pellets 7 and wires 9.

このようなリードフレーム１を用いてのトラン
ジスタの製造にあつては、第１図に示すように、
タブ８上にペレツト７を固定した後、ペレツト７
の電極とこれに対応するリード２，４のパツド１
０とをワイヤ（金線）９で接続し、その後、ペレ
ツト７、ワイヤ９を含むリード先端部をレジンモ
ールドしてレジンパツケージ１４で封止する。つ
いで、図示はしないが、不要となるダム片６およ
び外枠５を切断除去して、レジンモールド型のト
ランジスタを製造する。 When manufacturing a transistor using such a lead frame 1, as shown in FIG.
After fixing the pellet 7 on the tab 8, the pellet 7
electrode and corresponding pad 1 of leads 2 and 4
0 is connected with a wire (gold wire) 9, and then the lead tip portion including the pellet 7 and the wire 9 is resin molded and sealed with a resin package 14. Although not shown, the unnecessary dam piece 6 and outer frame 5 are then cut and removed to manufacture a resin molded transistor.

このようなリードフレーム１は、下地保護性の
優れた光沢銀メツキ膜１２を下層にすることによ
つて、ペレツトやワイヤの接続時の熱によるリー
ドフレーム母材の酸化（この酸化はリード先端部
のみが加熱されることから、タブ、パツド部で生
じる。）を防止している。また、上層はボンダビ
リテイの良好な無光沢銀メツキ膜１３としている
ことから、ペレツト７およびワイヤ９との接続性
は強く剥離し難い。したがつて、歩留の向上、信
頼性の向上が図れる。 This type of lead frame 1 has a glossy silver plating film 12 with excellent base protection properties as the lower layer to prevent oxidation of the lead frame base material due to heat during connection of pellets and wires (this oxidation occurs at the lead tips). This prevents heat from occurring at the tabs and pads. Furthermore, since the upper layer is a matte silver plating film 13 with good bondability, the connectivity with the pellets 7 and the wires 9 is strong and it is difficult to peel off. Therefore, yield and reliability can be improved.

また、このリードフレーム１は下地保護は光沢
銀メツキ膜１２で行なうため、銀メツキ膜全体の
厚さはたとえば1.5μmと従来の3.5μmに比較して
大幅に薄くできる。この結果、銀の使用量を低減
できることから、リードフレームの製造コストを
軽減できる。 Further, since the base of this lead frame 1 is protected by the bright silver plating film 12, the thickness of the entire silver plating film can be significantly thinner, for example, to 1.5 μm, compared to the conventional 3.5 μm. As a result, since the amount of silver used can be reduced, the manufacturing cost of the lead frame can be reduced.

なお、本発明は前記実施例に限定されるもので
はなく、本発明の技術思想に基いて変形可能であ
る。たとえば、光沢銀メツキ膜を形成する添加金
属は、Sb以外のSe，Ｓ，Sn等でもよい。 Note that the present invention is not limited to the above-mentioned embodiments, but can be modified based on the technical idea of the present invention. For example, the additive metal forming the bright silver plating film may be Se, S, Sn, etc. other than Sb.

また、第３図に示すように、光沢銀メツキ膜１
２と母材１１との間にニツケル膜１５を介在させ
て銀メツキ膜と母材との密着性（接合性）を向上
させるようにしてもよい。 In addition, as shown in FIG. 3, a glossy silver plating film 1
A nickel film 15 may be interposed between the silver plating film 2 and the base material 11 to improve the adhesion (bondability) between the silver plating film and the base material.

さらに、本発明は他の半導体装置、IC（集積回
路装置）用のリードフレームにも適用できること
は勿論である。 Furthermore, it goes without saying that the present invention can be applied to lead frames for other semiconductor devices and ICs (integrated circuit devices).

以上のように、本発明によれば、下地保護性、
接続性が高くかつ製造コストが安価となるリード
フレームを提供することができる。 As described above, according to the present invention, base protection properties,
A lead frame with high connectivity and low manufacturing cost can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例によるリードフレー
ムの平面図、第２図は第１図の―線に沿う一
部の拡大断面図、第３図は他の実施例によるリー
ドフレームの一部の拡大断面図である。 １…リードフレーム、２〜４…リード、５…外
枠、６…ダム片、７…ペレツト、８…タブ、９…
ワイヤ、１０…パツド、１１…母材、１２…光沢
銀メツキ膜、１３…無光沢銀メツキ膜、１４…レ
ジンパツケージ、１５…ニツケル膜。 FIG. 1 is a plan view of a lead frame according to an embodiment of the present invention, FIG. 2 is an enlarged cross-sectional view of a portion taken along line - in FIG. 1, and FIG. 3 is a portion of a lead frame according to another embodiment. FIG. 1...Lead frame, 2-4...Lead, 5...Outer frame, 6...Dam piece, 7...Pellet, 8...Tab, 9...
Wire, 10... Pad, 11... Base material, 12... Bright silver plating film, 13... Matte silver plating film, 14... Resin package, 15... Nickel film.

Claims (1)

【特許請求の範囲】[Claims] １ 金属リードフレーム素材におけるペレツトが
接続されるべき主面部およびワイヤが接続される
べき主面部には直接またはNi膜を介して光沢銀
メツキ膜が形成され、その光沢銀メツキ膜上に無
光沢銀メツキ膜が形成されてなることを特徴とす
るリードフレーム。1 A bright silver plating film is formed directly or via a Ni film on the main surface portion of the metal lead frame material to which the pellets are to be connected and the main surface portion to which the wire is to be connected, and a matte silver plating film is formed on the bright silver plating film. A lead frame characterized by forming a plating film.
JP56203754A 1981-12-18 1981-12-18 Lead frame Granted JPS58106853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56203754A JPS58106853A (en) 1981-12-18 1981-12-18 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56203754A JPS58106853A (en) 1981-12-18 1981-12-18 Lead frame

Publications (2)

Publication Number Publication Date
JPS58106853A JPS58106853A (en) 1983-06-25
JPS6366427B2 true JPS6366427B2 (en) 1988-12-20

Family

ID=16479279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56203754A Granted JPS58106853A (en) 1981-12-18 1981-12-18 Lead frame

Country Status (1)

Country Link
JP (1) JPS58106853A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130651U (en) * 1984-02-13 1985-09-02 凸版印刷株式会社 lead frame
US5530284A (en) * 1995-03-06 1996-06-25 Motorola, Inc. Semiconductor leadframe structure compatible with differing bond wire materials
JP3685057B2 (en) * 1999-12-08 2005-08-17 日亜化学工業株式会社 LED lamp and manufacturing method thereof
EP3462482A1 (en) 2017-09-27 2019-04-03 Nexperia B.V. Surface mount semiconductor device and method of manufacture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5373969A (en) * 1976-12-14 1978-06-30 Toshiba Corp Lead frame for semicinductor
JPS53108757A (en) * 1977-03-04 1978-09-21 Matsushita Electric Ind Co Ltd Coding method
JPS5596662A (en) * 1979-01-17 1980-07-23 Toshiba Corp Electronic component member

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5373969A (en) * 1976-12-14 1978-06-30 Toshiba Corp Lead frame for semicinductor
JPS53108757A (en) * 1977-03-04 1978-09-21 Matsushita Electric Ind Co Ltd Coding method
JPS5596662A (en) * 1979-01-17 1980-07-23 Toshiba Corp Electronic component member

Also Published As

Publication number Publication date
JPS58106853A (en) 1983-06-25

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