JPS6365641A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS6365641A JPS6365641A JP21016186A JP21016186A JPS6365641A JP S6365641 A JPS6365641 A JP S6365641A JP 21016186 A JP21016186 A JP 21016186A JP 21016186 A JP21016186 A JP 21016186A JP S6365641 A JPS6365641 A JP S6365641A
- Authority
- JP
- Japan
- Prior art keywords
- region
- film
- molybdenum
- circuit block
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000013078 crystal Substances 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 claims description 2
- 230000001747 exhibiting effect Effects 0.000 claims description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 10
- 239000011733 molybdenum Substances 0.000 abstract description 10
- 230000005669 field effect Effects 0.000 abstract description 7
- 230000008878 coupling Effects 0.000 abstract description 4
- 238000010168 coupling process Methods 0.000 abstract description 4
- 238000005859 coupling reaction Methods 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 239000000470 constituent Substances 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に高周波帯領域ある
いは高速での動作が要求される半導体集積回路における
各素子間又は各回路ブロック間の分＊構造に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and in particular, to semiconductor integrated circuits that require high-frequency operation or high-speed operation. Regarding structure.
従来の半導体集積回路のうち、例えばｎチャネル型のＭ
Ｏ３集積回路においては、その構成要素たるＭＯＳ電界
効果トランジスタ同士の分離を行なうに際して、ｐ型の
基板と、それぞれのＭＯ３電界効果トランジスタを形成
するｎ型である所のソース領域あるいはトレイン領域と
が形成するＰＮ接合を利用するのが普通である。Among conventional semiconductor integrated circuits, for example, n-channel type M
In an O3 integrated circuit, when separating the MOS field effect transistors that are its constituent elements, a p-type substrate and an n-type source or train region forming each MO3 field effect transistor are formed. Usually, a PN junction is used.
上述した従来の構造では、各素子間の分離がＰＮ接合に
よっているため、直流的には分離され得ても、交流的に
はＰＮ接合の容量を介して結合が起こることとなり、こ
のことは特に数百ＭＨ２帯〜数Ｇ Ｈｚ帯と云った高周
波領域で使用されるアナログ集積回路や、超高速性が要
求されるディジタル集積回路においては、回路の不安定
性、特性劣化、あるいは回路の誤動作を招くこととなる
。In the conventional structure described above, each element is separated by a PN junction, so even if they can be separated in direct current terms, coupling occurs in alternating current terms through the capacitance of the PN junction. In analog integrated circuits used in high frequency ranges from several hundred MHz to several GHz, and in digital integrated circuits that require ultra-high speed, this can lead to circuit instability, characteristic deterioration, or circuit malfunction. It happens.
またバイポーラ系集積回路で近年盛んに用いられる様に
なった、素子周辺をＰＮ接合でなく酸化シリコン膜を用
いて分離する手法く例えばＬＯＣＯＳ法）においても、
集積度が上がるにつれて、分離帯の物理的寸法が極めて
小さくなりつつあり、やはりその酸化膜を介しての容量
による結合も無視し得なくなりつつある。In addition, in the method (for example, LOCOS method) that uses silicon oxide film instead of PN junction to isolate the periphery of the element, which has become popular in recent years in bipolar integrated circuits,
As the degree of integration increases, the physical dimensions of the isolation zone are becoming extremely small, and the coupling due to capacitance through the oxide film is also becoming impossible to ignore.
本発明の半導体集積回路は、半導体基板上に、前記半導
体基板結晶とエピタキシーを示す半導体からなる島状領
域が、その底面及び側面を絶縁層−導体層−絶縁層の３
層構造体で覆って設置され、前記島状領域に半導体素子
が形成されていることを要旨としている。In the semiconductor integrated circuit of the present invention, an island-like region made of a semiconductor exhibiting epitaxy with the semiconductor substrate crystal is formed on a semiconductor substrate, and its bottom and side surfaces are formed by three layers: an insulating layer, a conductor layer, and an insulating layer.
The main feature is that the island-like region is covered with a layered structure and a semiconductor element is formed in the island-like region.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の主要部を示す半導体チップ
の断面図である。FIG. 1 is a sectional view of a semiconductor chip showing the main parts of an embodiment of the present invention.
この実施例は、ｐ型シリコン単結晶からなる半導体基板
１上に、ｐ型シリコン単結晶からなる島状領域２−１．
・・・・がその底面を窒化シリコン膜３−２−モリブデ
ン膜６−窒化シリコン膜３−１゜からなる３層構造体で
覆い、側面を酸化シリコン膜４ａ−モリブデン膜６ａ−
酸化シリコン膜４ｂからなる３Ｍ構造体で覆って設置さ
れ、島状領域２−１にｎチャネルＭＯＳ電界効果トラン
ジスタが形成されているものである。In this embodiment, on a semiconductor substrate 1 made of p-type silicon single crystal, island-like regions 2-1. made of p-type silicon single crystal.
... is covered with a three-layer structure consisting of a silicon nitride film 3-2 - a molybdenum film 6 - a silicon nitride film 3-1°, and its side faces are covered with a silicon oxide film 4a - a molybdenum film 6a -.
It is covered with a 3M structure made of a silicon oxide film 4b, and an n-channel MOS field effect transistor is formed in the island region 2-1.
ｎ型ソース領域１０．ｎ型ドレイン領域１１−１、モリ
ブデンゲート電極７−１、アルミニウムからなるソース
電極８及びドレイン電極９−１、バックゲートコンタク
ト領域１２とでｎチャネルＭＯ３電界効果１〜ランジス
タが構成されていて、モリブデン膜６，６ａは接地され
てゼロ電位となっているので、このトランジスタはシー
ルドされていることとなり、直流的にも、又高周波的に
も他の回路構成要素とは不必要な結合をしていないこと
となるので、直流から数ギガヘルツの周波数にわたって
電気的に分離絶縁される。なお、このｎチャネルＭＯＳ
電界効果トランジスタの他の要素への接続用配線と、６
，６ａとの交差部は通常の多層配線技術による。n-type source region 10. An n-channel MO3 field effect 1 to transistor is constituted by an n-type drain region 11-1, a molybdenum gate electrode 7-1, a source electrode 8 and a drain electrode 9-1 made of aluminum, and a back gate contact region 12. Since the membranes 6 and 6a are grounded and have zero potential, this transistor is shielded, and there is no unnecessary coupling with other circuit components in terms of direct current or high frequency. Therefore, it is electrically isolated from direct current to frequencies of several gigahertz. Note that this n-channel MOS
wiring for connecting the field effect transistor to other elements, and 6
, 6a are formed using normal multilayer wiring technology.
次に、この実施例の製造方法について説明する。Next, the manufacturing method of this example will be explained.
第２図〜第３図はこの実施例の製造方法を説明するため
の半導体チップの図であって、図（ａ）は平面図、図（
ｂ）は図（ａ）のＸ−χ′線断面図である。FIGS. 2 and 3 are diagrams of a semiconductor chip for explaining the manufacturing method of this embodiment, and FIG.
b) is a cross-sectional view taken along the line X-χ' in FIG.
まず、第２図に示すように、ｐ型シリコン単結晶からな
る半導体基板１の一表面に厚さ１０００人の窒化シリコ
ン膜３−１を被着し、その上に厚さ３０００〜５０００
人のモリブデン膜６を被着したのち半導体基板１に達す
る穴を設け、厚さ１０００人の窒化シリコン膜３−２を
被着し、穴の底部の窒化シリコン膜を除去することによ
り一辺が５μｍの正方形の開口２０を設ける。この開口
の間隔は約１００μｍとする。次に、多結晶シリコン層
を被着したのち、露出した半導体基板面を核として厚さ
２〜３μｍのｐ型シリコン単結晶層２′に変換する。First, as shown in FIG. 2, a silicon nitride film 3-1 with a thickness of 1,000 thick is deposited on one surface of a semiconductor substrate 1 made of p-type silicon single crystal, and a silicon nitride film 3-1 with a thickness of 3,000 to 5,000
After depositing a silicon nitride film 6, a hole reaching the semiconductor substrate 1 is formed, a silicon nitride film 3-2 with a thickness of 1,000 grams is deposited, and the silicon nitride film at the bottom of the hole is removed to form a hole with a side of 5 μm. A square opening 20 is provided. The interval between the openings is approximately 100 μm. Next, after depositing a polycrystalline silicon layer, the exposed semiconductor substrate surface is converted into a p-type silicon single crystal layer 2' having a thickness of 2 to 3 μm.
次に、第３図に示すように、前述の開口２０を避けて窒
化シリコン膜３−１に達する溝を掘り、厚さ１０００〜
２０００人の酸化シリコン膜４を熱酸化法により形成し
たのち溝の底部のシリコン膜３−２を除去することによ
り、溝２１で囲まれた島状領域２−１．・・・を形成す
る。Next, as shown in FIG. 3, a trench is dug to reach the silicon nitride film 3-1, avoiding the opening 20 described above, and to a thickness of 1000 to 1000.
After forming a silicon oxide film 4 of 2,000 layers by a thermal oxidation method, the silicon film 3-2 at the bottom of the trench is removed, thereby forming an island region 2-1 surrounded by the trench 21. ... to form.
次に満２１を埋めるモリブデン膜を形成してパターニン
グを行ってから、島状領域にｎチャネルＭＯＳ電界効果
トランジスタを形成すればよい。Next, a molybdenum film is formed to fill the area 21 and patterned, and then an n-channel MOS field effect transistor is formed in the island region.
なお、不純物領域の形成は前述した溝の底部の窒化シリ
コン膜を除去する前に行ってもよい。Note that the impurity region may be formed before removing the silicon nitride film at the bottom of the trench described above.
以上の説明において、モリブデンの代りにタングステン
等の高融点金属を用いてもよい。又、エピタキシャル成
長を行う場合、窒化シリコン膜３−１を設けず直接半導
体基板上にエピタキシャル層を形成する部分を設けてお
いて、そこにはそれほど高速動作を要求されない回路部
分を集積してもよい。更に島状領域は半導体基板にエピ
タキシャル成長させ得る物質であれば、必ずしも基板と
同一でなくてもよい。In the above description, a high melting point metal such as tungsten may be used instead of molybdenum. Furthermore, when epitaxial growth is performed, a portion where the epitaxial layer is directly formed on the semiconductor substrate without providing the silicon nitride film 3-1 may be provided, and a circuit portion that does not require high-speed operation may be integrated there. . Furthermore, the island-shaped region does not necessarily have to be the same as the substrate, as long as it is made of a material that can be epitaxially grown on the semiconductor substrate.
以上説明した様に、本発明は集積回路の一要素あるいは
複数の要素からなる回路ブロックを、薄い絶縁層領域及
びＯ電位に接地された金属領域で収り囲むことにより、
他の要素あるいは回路ブロックから、ＤＣ〜数ＧＨ２と
云った極めて広い周波数範囲に渡って電気的に分離絶縁
することを可能とする効果がある。As explained above, the present invention enables a circuit block consisting of one or more elements of an integrated circuit to be surrounded by a thin insulating layer region and a metal region grounded to O potential.
It has the effect of making it possible to electrically isolate it from other elements or circuit blocks over an extremely wide frequency range from DC to several GH2.
したがって本発明によるｖＩ造を用いることにより、極
めて高い周波数領域あるいは高速領域においても、安定
でかつ高性能に動作する半導体集積回路が得られる効果
がある。Therefore, by using the vI structure according to the present invention, it is possible to obtain a semiconductor integrated circuit that operates stably and with high performance even in an extremely high frequency region or high speed region.
第１図は本発明の一実施例の主要部を示す半導体チップ
の断面図、第２図〜第３図は第１図の実施例の製造方法
を説明するための半導体チップの図であり図（ａ）は平
面図、図（ｂ）は図（ａ）のｘ−ｘ’線断面図である。
１・・・半導体基板、２−１．２−２・・・島状領域、
２′・・・シリコン単結晶層、Ｂ−１，３−２・・・窒
化シリコン膜、４．４−１．４−２．４ａ、４ｂ−・・
シリコン酸化膜、５−１．５−２．５−３・・・リンガ
ラス層、６，６ａ・・・モリブデン膜、７−１゜７−２
・・・モリブデンゲート電極、８・・・ソース電極、９
−１．９−２・・・ドレイン電極、１ｏ・・・ｎ型ソー
ス領域、１１−１．１１−２・・・ｎ型トレイン領域、
１２・・・バックゲートコンタクト領域、１３・・・裏
面金属電極、２０・・・開口、２１・・・溝。FIG. 1 is a sectional view of a semiconductor chip showing the main parts of an embodiment of the present invention, and FIGS. 2 and 3 are diagrams of the semiconductor chip for explaining the manufacturing method of the embodiment of FIG. 1. (a) is a plan view, and figure (b) is a sectional view taken along line xx' in figure (a). 1... Semiconductor substrate, 2-1.2-2... Island region,
2'...Silicon single crystal layer, B-1, 3-2...Silicon nitride film, 4.4-1.4-2.4a, 4b-...
Silicon oxide film, 5-1.5-2.5-3... Phosphorus glass layer, 6,6a... Molybdenum film, 7-1°7-2
...Molybdenum gate electrode, 8...Source electrode, 9
-1.9-2...Drain electrode, 1o...N-type source region, 11-1.11-2...N-type train region,
12... Back gate contact region, 13... Back metal electrode, 20... Opening, 21... Groove.
Claims (1)
示す半導体からなる島状領域が、その底面及び側面を絶
縁層−導体層−絶縁層の３層構造体で覆って設置され、
前記島状領域に半導体素子が形成されていることを特徴
とする半導体集積回路。An island-like region made of a semiconductor exhibiting epitaxy with the semiconductor substrate crystal is placed on a semiconductor substrate with its bottom and side surfaces covered with a three-layer structure of an insulating layer, a conductor layer, and an insulating layer,
A semiconductor integrated circuit characterized in that a semiconductor element is formed in the island-like region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21016186A JPS6365641A (en) | 1986-09-05 | 1986-09-05 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21016186A JPS6365641A (en) | 1986-09-05 | 1986-09-05 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6365641A true JPS6365641A (en) | 1988-03-24 |
Family
ID=16584774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21016186A Pending JPS6365641A (en) | 1986-09-05 | 1986-09-05 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6365641A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5017999A (en) * | 1989-06-30 | 1991-05-21 | Honeywell Inc. | Method for forming variable width isolation structures |
| US5264720A (en) * | 1989-09-22 | 1993-11-23 | Nippondenso Co., Ltd. | High withstanding voltage transistor |
| US5306942A (en) * | 1989-10-11 | 1994-04-26 | Nippondenso Co., Ltd. | Semiconductor device having a shield which is maintained at a reference potential |
| US5310446A (en) * | 1990-01-10 | 1994-05-10 | Ricoh Company, Ltd. | Method for producing semiconductor film |
| US5449946A (en) * | 1993-03-10 | 1995-09-12 | Nippondenso Co., Ltd. | Semiconductor device provided with isolation region |
| US5459346A (en) * | 1988-06-28 | 1995-10-17 | Ricoh Co., Ltd. | Semiconductor substrate with electrical contact in groove |
| US5644157A (en) * | 1992-12-25 | 1997-07-01 | Nippondenso Co., Ltd. | High withstand voltage type semiconductor device having an isolation region |
| US5789793A (en) * | 1995-07-31 | 1998-08-04 | Kurtz; Anthony D. | Dielectrically isolated well structures |
| US5811868A (en) * | 1996-12-20 | 1998-09-22 | International Business Machines Corp. | Integrated high-performance decoupling capacitor |
| US5939755A (en) * | 1995-06-08 | 1999-08-17 | Kabushiki Kaisha Toshiba | Power IC having high-side and low-side switches in an SOI structure |
| US6104078A (en) * | 1994-03-09 | 2000-08-15 | Denso Corporation | Design for a semiconductor device having elements isolated by insulating regions |
| US6242792B1 (en) | 1996-07-02 | 2001-06-05 | Denso Corporation | Semiconductor device having oblique portion as reflection |
| US6411155B2 (en) | 1994-12-30 | 2002-06-25 | Sgs-Thomson Microelectronics S.A. | Power integrated circuit |
| US6580142B1 (en) * | 1994-12-30 | 2003-06-17 | Sgs-Thomson Microelectronics S.A. | Electrical control methods involving semiconductor components |
-
1986
- 1986-09-05 JP JP21016186A patent/JPS6365641A/en active Pending
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5565697A (en) * | 1988-06-28 | 1996-10-15 | Ricoh Company, Ltd. | Semiconductor structure having island forming grooves |
| US5459346A (en) * | 1988-06-28 | 1995-10-17 | Ricoh Co., Ltd. | Semiconductor substrate with electrical contact in groove |
| US5017999A (en) * | 1989-06-30 | 1991-05-21 | Honeywell Inc. | Method for forming variable width isolation structures |
| US5264720A (en) * | 1989-09-22 | 1993-11-23 | Nippondenso Co., Ltd. | High withstanding voltage transistor |
| US5403769A (en) * | 1989-10-11 | 1995-04-04 | Nippondenso Co., Ltd. | Process for producing a semiconductor device |
| US5474952A (en) * | 1989-10-11 | 1995-12-12 | Nippondenso Co., Ltd. | Process for producing a semiconductor device |
| US5306942A (en) * | 1989-10-11 | 1994-04-26 | Nippondenso Co., Ltd. | Semiconductor device having a shield which is maintained at a reference potential |
| US5627399A (en) * | 1989-10-11 | 1997-05-06 | Nippondenso Co., Ltd. | Semiconductor device |
| US5310446A (en) * | 1990-01-10 | 1994-05-10 | Ricoh Company, Ltd. | Method for producing semiconductor film |
| US5644157A (en) * | 1992-12-25 | 1997-07-01 | Nippondenso Co., Ltd. | High withstand voltage type semiconductor device having an isolation region |
| US5449946A (en) * | 1993-03-10 | 1995-09-12 | Nippondenso Co., Ltd. | Semiconductor device provided with isolation region |
| US6104078A (en) * | 1994-03-09 | 2000-08-15 | Denso Corporation | Design for a semiconductor device having elements isolated by insulating regions |
| US6411155B2 (en) | 1994-12-30 | 2002-06-25 | Sgs-Thomson Microelectronics S.A. | Power integrated circuit |
| US6580142B1 (en) * | 1994-12-30 | 2003-06-17 | Sgs-Thomson Microelectronics S.A. | Electrical control methods involving semiconductor components |
| US5939755A (en) * | 1995-06-08 | 1999-08-17 | Kabushiki Kaisha Toshiba | Power IC having high-side and low-side switches in an SOI structure |
| US5789793A (en) * | 1995-07-31 | 1998-08-04 | Kurtz; Anthony D. | Dielectrically isolated well structures |
| US6242792B1 (en) | 1996-07-02 | 2001-06-05 | Denso Corporation | Semiconductor device having oblique portion as reflection |
| US5811868A (en) * | 1996-12-20 | 1998-09-22 | International Business Machines Corp. | Integrated high-performance decoupling capacitor |
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