JPS6364294A - Thin film electroluminescence device - Google Patents
Thin film electroluminescence deviceInfo
- Publication number
- JPS6364294A JPS6364294A JP61207944A JP20794486A JPS6364294A JP S6364294 A JPS6364294 A JP S6364294A JP 61207944 A JP61207944 A JP 61207944A JP 20794486 A JP20794486 A JP 20794486A JP S6364294 A JPS6364294 A JP S6364294A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- transparent electrode
- insulating layer
- electrode pattern
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 18
- 238000005401 electroluminescence Methods 0.000 title description 15
- 239000000758 substrate Substances 0.000 claims description 28
- 230000005684 electric field Effects 0.000 description 10
- 239000011521 glass Substances 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000005083 Zinc sulfide Substances 0.000 description 4
- 239000011572 manganese Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 4
- 229910052984 zinc sulfide Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000009125 cardiac resynchronization therapy Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000012190 activator Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- -1 rare earth compound Chemical class 0.000 description 2
- 229910052761 rare earth metal Inorganic materials 0.000 description 2
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- QHGNHLZPVBIIPX-UHFFFAOYSA-N tin(ii) oxide Chemical class [Sn]=O QHGNHLZPVBIIPX-UHFFFAOYSA-N 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electroluminescent Light Sources (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は交流電界の印加によりエレクトロルミネセンス
（ＥＬ）を呈する薄膜エレクトロルミネセンス素子（以
下薄膜ＥＬ素子と称する）に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film electroluminescent device (hereinafter referred to as a thin film EL device) that exhibits electroluminescence (EL) upon application of an alternating current electric field.
近年、大容量ディスプレイとして、ブラウン管（以下Ｃ
ＲＴと称する）が広く用いられているが、ＣＲＴは真空
管であるため、大重量で破損の危険性もあり、また奥行
き寸法が太きい、偏向走査歪が避けにく（、さらには数
ＫＶ以上の高電圧を必要とするなどの問題があった。In recent years, cathode ray tubes (C
(referred to as RT) are widely used, but since CRTs are vacuum tubes, they are heavy and have the risk of breakage, and their depth is large, making it difficult to avoid deflection and scanning distortion (and even more There were problems such as the high voltage required.
一方、平面形のディスプレイとしては、プラズマディス
プレイパネル（以下ＦＤＰと称する）の開発が進められ
ているが、ＦＤＰはＣＲＴに比較して薄形であり、動作
電圧も低く、マトリックス形であるため走査歪がないと
いう利点があるが、ガス放電管であり、また真空管の一
種であるために重量が大きく、破損の危険性は避けられ
ない。On the other hand, as a flat display, plasma display panels (hereinafter referred to as FDPs) are being developed, but FDPs are thinner than CRTs, have lower operating voltages, and are matrix-type, so they cannot be scanned. Although it has the advantage of not being distorted, since it is a gas discharge tube and a type of vacuum tube, it is heavy and the risk of breakage is unavoidable.
また、液晶ディスプレイディバイス（以下ＬＣＤと称す
る）は、固体素子に近く、動作′重圧も数■ないし十数
Ｖと低いが、応答速度が小さい、動作可能温度範囲が狭
く、さらには受光形デバイスのため表示面が暗いといっ
た問題を抱えている。In addition, liquid crystal display devices (hereinafter referred to as LCDs) are similar to solid-state devices and have low operating pressures of several to several tens of volts, but their response speeds are low, their operating temperature ranges are narrow, and they are light-receiving devices. Therefore, there is a problem that the display screen is dark.
これに対してＥＬを呈する薄膜ＥＬ素子を用いた薄膜Ｅ
Ｌパネルは、ＣＲＴと比較して駆動電圧が低く、またＦ
ＤＰに比較して重量、大きさ等において優れ、ＬＣＤに
比較して動作可能温度範囲が広い等、多くの利点を、有
しており、文字、グラフィック表示に対して最適である
。On the other hand, thin film E using a thin film EL element exhibiting EL
The L panel has a lower driving voltage than a CRT, and
It has many advantages such as being superior in weight and size compared to DP, and has a wider operating temperature range than LCD, making it ideal for displaying characters and graphics.
この薄膜ＥＬ素子は１例えば硫化亜鉛（ＺｎＳ）を母体
とし、これに付活剤としてマンガン（Ｍ ｎ ）や希土
類化合物等を添加した発光層の両側あるいは片側に酸化
イツトリウム（Ｙ２Ｏ３）や窒化シリコン（ＳｉＮｘ）
等の絶縁層を設け、対向電極でサンドイッチ状に挟持し
た構成が輝度、寿命等の点で優れている。This thin film EL element has a light-emitting layer made of zinc sulfide (ZnS) as a base material, to which manganese (M n ) or a rare earth compound is added as an activator, and yttrium oxide (Y2O3) or silicon nitride ( SiNx)
A structure in which an insulating layer is provided and sandwiched between opposing electrodes is superior in terms of brightness, lifespan, etc.
第２図は発光層を絶縁層で挟持させた二重絶縁層構造の
薄膜ＥＬ素子の一例を示す要部断面図である。同図にお
いて、１はガラス基板、２は酸化インジウム（Ｉｒ＋ｚ
Ｏａ）あるいはインジウムと錫との酸化物（ＩＴ○）等
からなる透明電極、３はＹ２Ｏ５，ＳｉＮｘ等からなる
第１の絶縁層、４はＭｎあるいは希土類化合物等を添加
したＺｎＳ発光層、５は第２の絶縁層、６はアルミニウ
ム（ＡＱ）等からなる背面電極、７は交流電源である。FIG. 2 is a sectional view of a main part showing an example of a thin film EL element having a double insulating layer structure in which a light emitting layer is sandwiched between insulating layers. In the figure, 1 is a glass substrate, 2 is indium oxide (Ir+z
3 is a first insulating layer made of Y2O5, SiNx, etc., 4 is a ZnS light-emitting layer doped with Mn or a rare earth compound, etc., 5 is a transparent electrode made of Oa) or an oxide of indium and tin (IT○), etc. A second insulating layer, 6 a back electrode made of aluminum (AQ) or the like, and 7 an AC power source.
このような構成による薄膜ＥＬ索子は、透明電極２と背
面電極６との間に交流な源７により交流電界を印加する
と、約１０６Ｖ／ａｎ程度の高電界により高輝度に発光
する。このように高輝度を得るためには、極めて高い電
界を必要とするため、第１、第２の絶縁層３，５は極め
て高い絶縁耐圧をもつことが不可欠である。When an alternating current electric field is applied between the transparent electrode 2 and the back electrode 6 by an alternating current source 7, the thin film EL cord having such a structure emits light with high brightness due to the high electric field of about 106 V/an. In order to obtain such high brightness, an extremely high electric field is required, so it is essential that the first and second insulating layers 3 and 5 have an extremely high dielectric strength voltage.
なお、絶Ｍ層全体の絶縁性を向上させる方法としては、
絶縁層成膜後、真空中、４００〜６００℃で熱処理する
方法が特公昭５９−１００３３号公報において詳記され
ている。In addition, as a method to improve the insulation of the entire absolute M layer,
Japanese Patent Publication No. 59-10033 describes in detail a method of heat-treating in vacuum at 400 to 600° C. after forming an insulating layer.
しかしながら、このように構成される薄膜ＥＬ索子は、
同図から明らかなようにガラス基板１上に形成する透明
゛正極２．第１の絶縁層３．Ｚｎ’Ｓ発光層４．第２の
絶縁層５および背面′市極６を真空蒸着あるいはスパッ
タリング法等で成膜し、透明電極２および背面電極６に
ついては所望のパターンをエツチング法あるいはマスク
成膜法により得た場合、パターンエツジ部に段差を生し
る。特に透明電極２のパターンエツジ部ではこの上に積
層した第１の絶縁層３４発光層４および第２の絶８層５
にも段差が生じ１局部的に膜厚が小さくなる。また、こ
の第２の絶縁層５上に背面電極６を形成し、透明電極２
と背面電極６との間に高電界を印加すると、透明電極２
のパターンエツジ部に電界集中が生じ、絶縁破壊の起点
となる可能性があり、また高輝度を得るために著しく悪
影響を与え、信頼性を著しく低下させていることが判明
した。However, the thin film EL cord configured in this way,
As is clear from the figure, a transparent positive electrode 2 is formed on a glass substrate 1. First insulating layer 3. Zn'S light emitting layer 4. When the second insulating layer 5 and the back electrode 6 are formed by vacuum evaporation or sputtering, and the desired pattern is obtained for the transparent electrode 2 and the back electrode 6 by an etching method or a mask film forming method, the pattern Creates a step at the edge. In particular, at the pattern edge portion of the transparent electrode 2, a first insulating layer 34, a light emitting layer 4, and a second insulating layer 5 are laminated thereon.
A difference in level also occurs, and the film thickness becomes locally small. Further, a back electrode 6 is formed on this second insulating layer 5, and a transparent electrode 2 is formed on the second insulating layer 5.
When a high electric field is applied between the transparent electrode 2 and the back electrode 6, the transparent electrode 2
It has been found that electric field concentration occurs at the edge of the pattern, which may become a starting point for dielectric breakdown, and has a significant negative effect on obtaining high brightness, significantly reducing reliability.
したがって本発明は、前述した従来の問題に鑑みてなさ
れたものであり、その目的とするところは、高電界印加
時に絶縁性基板上に形成した電極パターンのエツジ部に
生じる電界集中を抑止し、品質および信頼性を向上させ
た薄膜ＥＬ；＋３子を提供することにある。Therefore, the present invention has been made in view of the above-mentioned conventional problems, and its purpose is to suppress electric field concentration occurring at the edge portion of an electrode pattern formed on an insulating substrate when a high electric field is applied; Our objective is to provide thin film EL with improved quality and reliability.
このような目的を達成するために、本発明による薄膜Ｅ
Ｌ索子は、透明電極パターンを絶縁性基板内に埋め込ん
で設け、この上に積層する絶縁層および発光層を平坦化
させたものである。In order to achieve this purpose, the thin film E according to the present invention
The L-shaped element has a transparent electrode pattern embedded in an insulating substrate, and an insulating layer and a light emitting layer laminated thereon are planarized.
透明電極パターンを絶縁性基板内に埋めこんで設ける結
果、透明電極パターンを十分厚く形成しても、絶縁性基
板と透明′１ｊｌｆ極パターンとの上面を而−にもしく
は段差を減少した状態で構成することができ、したがっ
て、透明゛電極パターンのエツジ部による段差の問題が
少なくなる。As a result of providing the transparent electrode pattern embedded in the insulating substrate, even if the transparent electrode pattern is formed sufficiently thick, the top surface of the insulating substrate and the transparent electrode pattern can be formed with the same structure or with a reduced level difference. Therefore, the problem of steps caused by the edge portions of the transparent electrode pattern is reduced.
次に図面を用いて本発明の実施例を詳細に説明する。 Next, embodiments of the present invention will be described in detail using the drawings.
第１図（ａ）、（ｂ）は本発明による薄膜ＥＬ素子の一
例を示す要部平面図、そのＡ−Ａ’断面図である。同図
において、絶縁性基板として例えばホウケイ酸ガラス基
板８を用い、この基板全面にフォトレジストを塗布する
９次にこのレジストを所望のストライブ状パターンに形
成し、この状態でガラス基板８をフッ酸系のエツチング
液に浸漬し、２０００人程度基板をエツチングして、透
明電極パターン９を埋設するためのストライプ状の溝を
形成する。この場合、フォトレジストの股ノ１メは０゜
５〜５．０μｍの範囲が良く、望ましくは１〜２μｍの
厚さに形成し、これを所定のフォトマスクを用いて露光
してｊｕ！し、このレジストパターンを用いて基板のエ
ツチングを行なって透明電極パターン９を埋設するため
の溝を形成する。次にフォトレジストをそのまま残した
状態で全面にインジウムと錫の酸化物をスパッタリング
して厚さ約２０００基稈度の透明導電膜を形成する。次
にフォトレジストの溶剤中にこれを浸漬し、リフトオフ
によりガラス鋸板８上のフォトレジストとその上の透明
導電膜とを除去し、基板８の溝中に埋設された透明電極
９を形成する。これにより透明電極パターン９のエツジ
に段差のない基板が形成される。次にこの表面が平坦な
透明電極パターン９が形成されたガラス基板８上に基板
温度約３００°ＣでＹ２Ｏ３をＥＢ蒸着して膜厚約３０
００基稈度の第１の絶縁層１０を形成する。次にこの絶
縁層１０上に付活剤としてＭｎを約０，５ｗｔ％加えた
ＺｎＳの焼結体を材料として基板温度約２５０℃でＥＢ
蒸着により発光層１１を約５ｏｏｏ人の厚さに形成する
。その後、真空中において約５５０℃で２時間アニール
処理を行ない、発光！１１中のＭ ｎの分布の均一化と
各薄膜の欠陥の低減をはかる。次にこの発光層１上上に
鎖板温度３００℃でＹ２Ｏ３を約３０００基板度の厚さ
にＥＢ蒸着して第２の絶縁層１２を形成する。最後に透
明電極パターン９と直交する方向にアルミニウムを約２
０００基稈度の厚さにマスク蒸着してストライプ状の背
面電極１３を形成して素子を完成する。FIGS. 1(a) and 1(b) are a plan view of a main part showing an example of a thin film EL element according to the present invention, and a sectional view thereof taken along line AA'. In the figure, a borosilicate glass substrate 8, for example, is used as an insulating substrate, and a photoresist is applied to the entire surface of the substrate.Next, this resist is formed into a desired striped pattern, and in this state, the glass substrate 8 is covered with a film. The substrate is immersed in an acid-based etching solution and etched by about 2000 steps to form striped grooves in which the transparent electrode pattern 9 is to be embedded. In this case, the thickness of the photoresist is preferably in the range of 0°5 to 5.0 μm, preferably 1 to 2 μm, and exposed using a predetermined photomask. Then, using this resist pattern, the substrate is etched to form a groove in which the transparent electrode pattern 9 is to be buried. Next, with the photoresist left intact, indium and tin oxides are sputtered over the entire surface to form a transparent conductive film with a thickness of about 2000 silica. Next, this is immersed in a photoresist solvent, and the photoresist on the glass saw plate 8 and the transparent conductive film thereon are removed by lift-off, thereby forming a transparent electrode 9 buried in the groove of the substrate 8. . As a result, a substrate with no step at the edge of the transparent electrode pattern 9 is formed. Next, on the glass substrate 8 on which the transparent electrode pattern 9 with a flat surface was formed, Y2O3 was EB-deposited at a substrate temperature of about 300°C to a film thickness of about 30°C.
A first insulating layer 10 having a 00 base culmness is formed. Next, on this insulating layer 10, a sintered body of ZnS to which about 0.5 wt% of Mn was added as an activator was used as a material, and EB was carried out at a substrate temperature of about 250°C.
The light emitting layer 11 is formed by vapor deposition to a thickness of about 5 mm. After that, annealing is performed in a vacuum at approximately 550°C for 2 hours, and light is emitted! The aim is to make the distribution of Mn in No. 11 uniform and to reduce defects in each thin film. Next, a second insulating layer 12 is formed on the light emitting layer 1 by EB vapor deposition of Y2O3 to a thickness of about 3000 substrates at a chain plate temperature of 300.degree. Finally, add approximately 2 pieces of aluminum in the direction perpendicular to the transparent electrode pattern 9.
A stripe-shaped back electrode 13 is formed by mask vapor deposition to a thickness of 0.000 bases, and the device is completed.
このような構成によれば、ガラス基板８内に埋め込んで
透明電極パターン９を形成したことにより、透明電極パ
ターン９のパターンエツジによる電界の集中の発生が抑
止され、絶縁破壊の起点となることを防止できるので、
素子の絶縁耐圧が飛界的に向上し、発光の寿命を向上さ
せることができる。According to such a configuration, by forming the transparent electrode pattern 9 by embedding it in the glass substrate 8, the occurrence of electric field concentration due to the pattern edges of the transparent electrode pattern 9 is suppressed, thereby preventing it from becoming a starting point of dielectric breakdown. Because it can be prevented,
The dielectric strength of the element is dramatically improved, and the lifetime of light emission can be extended.
なお、前述した実施例においては、透明電極パターン９
のエツジの影響を抑止するために透明電極パターン９の
１漠厚は、基板に設ける溝の深さと同一とした場合につ
いて説明したが、これが最も効果的であるが、全く同じ
にすることが困難な場合は、透明電極パターン９の膜厚
に対する溝深さの比を０．５〜２．０の範囲に抑えれば
前述と同様の効果が得ら塾る。この場合、この比が０．
５以下とすると、透明電極パターンのエツジの影響を抑
止することができなくなる。またこの比を２゜０以上と
すると、第１の絶縁層１０が透明電極パターン９上に均
一な膜厚で形成されにくくなるため好ましくない。した
がってその比は０．５〜２゜０の範囲が好ましい。In addition, in the embodiment described above, the transparent electrode pattern 9
In order to suppress the influence of the edges, a case has been described in which the thickness of the transparent electrode pattern 9 is set to be the same as the depth of the groove provided in the substrate. Although this is most effective, it is difficult to make it exactly the same. In such a case, the same effect as described above can be obtained by suppressing the ratio of the groove depth to the film thickness of the transparent electrode pattern 9 within the range of 0.5 to 2.0. In this case, this ratio is 0.
When it is less than 5, it becomes impossible to suppress the influence of edges of the transparent electrode pattern. Further, if this ratio is 2° or more, it is not preferable because it becomes difficult to form the first insulating layer 10 with a uniform thickness on the transparent electrode pattern 9. Therefore, the ratio is preferably in the range of 0.5 to 2.0.
また、前述した実施例において、ガラス基板８はホウケ
イ酸ガラスを用いたが、本発明はこれに限定されるもの
ではなく、不透明基板を用いた場合でもこの不透明基板
上の電極（この場合は背面電極となる）のパターンのエ
ツジを同様の方法で平坦化することにより、前述した実
施例の場合と全く同様の効果が得られることは明白であ
る。Further, in the above embodiment, the glass substrate 8 was made of borosilicate glass, but the present invention is not limited to this, and even when an opaque substrate is used, the electrodes on this opaque substrate (in this case, the back surface It is clear that by flattening the edges of the pattern (which will become the electrode) in a similar manner, exactly the same effect as in the embodiment described above can be obtained.
以上説明したように本発明によれば、絶縁性基板上に形
成した電極パターンのエツジによる段差がなくなるので
、この電極パターン上に積層形成する絶縁層９発光層お
よび対向電極の平坦化が容易に実現可能となり、電極パ
ターンエツジ部の電界集中が著しく抑制でき、信頼性の
高い高品質。As explained above, according to the present invention, there are no steps caused by the edges of the electrode pattern formed on the insulating substrate, so it is easy to flatten the insulating layer 9, the light-emitting layer, and the counter electrode that are laminated on the electrode pattern. It is now possible to achieve high reliability and high quality by significantly suppressing electric field concentration at the edge of the electrode pattern.
高性能、長寿命の薄膜ＥＬ素子が′４１）られるという
極めて優れた効果を有する。This has the extremely excellent effect of producing a thin film EL element with high performance and long life '41).
第１図（ａ）、 （ｉ））は本発明による薄膜ＥＬ素子
の一例を説明するための要部断面図、並びにそのＡ−Ａ
’断面回、第２図は従来周知の薄膜ＥＬ素子の要部断面
図である。
８・・・ガラス基板、９・・・透明電極パターン、１ｏ
・・・第１の絶縁層、１１・・・発光層。
１２・・・第２の絶縁層、１３・・・背面電極。FIGS. 1(a) and 1(i) are sectional views of essential parts for explaining an example of a thin film EL element according to the present invention, and A-A thereof.
Figure 2 is a sectional view of a main part of a conventionally known thin film EL element. 8...Glass substrate, 9...Transparent electrode pattern, 1o
. . . first insulating layer, 11 . . . light emitting layer. 12... Second insulating layer, 13... Back electrode.
Claims (1)
層および背面電極を形成してなる薄膜エレクトロルミネ
センス素子において、前記絶縁性基板上の透明電極パタ
ーンを絶縁性基板内に埋め込んで設けたことを特徴とす
る薄膜エレクトロルミネセンス素子。1. In a thin film electroluminescent device comprising at least a transparent electrode, an insulating layer, a light emitting layer, and a back electrode formed on an insulating substrate, the transparent electrode pattern on the insulating substrate is embedded in the insulating substrate. Characteristic thin film electroluminescent elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61207944A JPS6364294A (en) | 1986-09-05 | 1986-09-05 | Thin film electroluminescence device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61207944A JPS6364294A (en) | 1986-09-05 | 1986-09-05 | Thin film electroluminescence device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6364294A true JPS6364294A (en) | 1988-03-22 |
Family
ID=16548121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61207944A Pending JPS6364294A (en) | 1986-09-05 | 1986-09-05 | Thin film electroluminescence device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6364294A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04250673A (en) * | 1991-01-16 | 1992-09-07 | Toshiba Corp | Semiconductor light emitting element and manufacture thereof |
-
1986
- 1986-09-05 JP JP61207944A patent/JPS6364294A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04250673A (en) * | 1991-01-16 | 1992-09-07 | Toshiba Corp | Semiconductor light emitting element and manufacture thereof |
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