JPS6362341A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6362341A JPS6362341A JP61207097A JP20709786A JPS6362341A JP S6362341 A JPS6362341 A JP S6362341A JP 61207097 A JP61207097 A JP 61207097A JP 20709786 A JP20709786 A JP 20709786A JP S6362341 A JPS6362341 A JP S6362341A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- insulating film
- semiconductor device
- barrier metal
- covering insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 66
- 229910052751 metal Inorganic materials 0.000 claims abstract description 66
- 230000004888 barrier function Effects 0.000 claims abstract description 39
- 238000012360 testing method Methods 0.000 claims abstract description 19
- 238000011056 performance test Methods 0.000 abstract description 11
- 230000006866 deterioration Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 34
- 239000010931 gold Substances 0.000 description 13
- 238000000034 method Methods 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 241001422033 Thestylus Species 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 206010011224 Cough Diseases 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（概 要〕
チップ構造を有する半導体装置において、配線材料金属
とバンプ材料金属との反応を防止するためにバンプ配設
部に介在せしめるバリアメタル層を、被覆絶縁膜上にパ
ッド状に延在させ、これをブローμによる性能試験用の
電極とすることにより、該ブローμによる性能試験にお
けるバンプ部の劣化を防止してチップ構造半導体装置の
外部回路への接続の信頼度を向上する。Detailed Description of the Invention (Summary) In a semiconductor device having a chip structure, a barrier metal layer interposed in a bump placement area is provided on a coating insulating film to prevent a reaction between wiring material metal and bump material metal. By extending it in the shape of a pad and using it as an electrode for performance testing using the blow μ, deterioration of the bump portion in the performance test using the blow μ can be prevented, thereby increasing the reliability of the connection of the chip structure semiconductor device to the external circuit. Improve your degree.
本発明はチップ構造の半導体装置の外部電極構造の改良
に関する。The present invention relates to an improvement in the external electrode structure of a chip-structured semiconductor device.
半導体装置の集積密度を上げて、各種情報処理装置の小
型大容量化を図るために、チップ構造の半導体装置が用
いられる。Chip-structured semiconductor devices are used to increase the integration density of semiconductor devices and to make various information processing devices smaller and larger in capacity.
チップ構造の半導体装置においては、外部回路に取りつ
けられる以前にその性能試験がブローμを用いる触針法
でなされるが、この際該半導体装置の外部電極部即ちバ
ンプ部が損傷され易く、このため該半導体装置を情報処
理装置等の配線基板に金属バンプを介して取りつけた際
の接続の信頼性が低下するという問題があり、バンプ部
に損傷を与えずにブローμによる性能試験が行える外部
電極構造が要望されている。For chip-structured semiconductor devices, performance tests are performed using the stylus method using a blow μ before being attached to an external circuit, but in this case, the external electrode portions, that is, the bump portions of the semiconductor device are likely to be damaged. There is a problem that the reliability of the connection decreases when the semiconductor device is attached to a wiring board of an information processing device etc. via a metal bump, so an external electrode that allows performance testing by blowing μ without damaging the bump portion is necessary. structure is required.
第３図は、上記チップ構造の半導体装置における従来の
バンプ部の構造を示す要部模式側断面図である。FIG. 3 is a schematic side sectional view of a main part showing the structure of a conventional bump portion in the semiconductor device having the above-mentioned chip structure.
同図において、１は層間絶縁膜、２は上層のアルミニウ
ム（Ａｌ）配線、３は被覆絶縁膜、４は上層配線を表出
する被覆絶縁膜の開孔、５はバリアメタルパターン、６
は金属バンプを示す。In the figure, 1 is an interlayer insulating film, 2 is an upper layer aluminum (Al) wiring, 3 is a covering insulation film, 4 is an opening in the covering insulation film that exposes the upper wiring, 5 is a barrier metal pattern, and 6
indicates a metal bump.
従来上記バンプを形成する際には、被覆絶縁膜３に上層
Ａｔ配線２の一部を表出する開孔４を形成した後、該開
孔４内を含む被覆絶縁膜３上にバリアメタル層をスパッ
タリング法等により被着し、該バリアメタル層上にバン
プ形成領域を表出する開孔を有するレジスト膜を形成し
、該レジスト膜をマスクにして電気メツキ法により該レ
ジスト膜の開孔内に例えば金（Ａｕ）よりなる金属バン
プ６を成長させ、上記レジスト膜を除去した後、上記金
属（Ａｕ）バンプ６をマスクにしてエツチング手段によ
りバリアメタル層の表出領域を選択的に除去する方法が
用いられていた。そこで従来のバンプ部は同図に示すよ
うに金属（Ａｕ）バンプ５の下部のみにバリアメタルパ
ターン５が配設される構造であった。Conventionally, when forming the above-mentioned bump, after forming an opening 4 in the covering insulating film 3 to expose a part of the upper layer At wiring 2, a barrier metal layer is formed on the covering insulating film 3 including the inside of the opening 4. A resist film is formed on the barrier metal layer by a sputtering method or the like, and a resist film is formed on the barrier metal layer with an opening that exposes a bump formation region. After growing a metal bump 6 made of, for example, gold (Au) and removing the resist film, the exposed area of the barrier metal layer is selectively removed by etching using the metal (Au) bump 6 as a mask. method was used. Therefore, the conventional bump section has a structure in which a barrier metal pattern 5 is provided only at the lower part of the metal (Au) bump 5, as shown in the figure.
そのため、従来チップ構造の半導体装置の性能を外部回
路への取りつけに先立ってブローμを用いて試験する際
には、金属バンプ６上に触針を立てて試験せざるを得す
、その際金属バンプ６が脱落して該半導体装置が不良に
なったり、また金属バンプ６が変形して一様に良好な外
部回路との接続が得られず外部回路との接続の信頼度が
低下するという問題を生じていた。Therefore, when testing the performance of a semiconductor device with a conventional chip structure using a blow μ prior to attachment to an external circuit, it is necessary to test with a stylus placed on the metal bump 6. The problem is that the bumps 6 fall off and the semiconductor device becomes defective, or the metal bumps 6 are deformed and a uniformly good connection with the external circuit cannot be obtained, reducing the reliability of the connection with the external circuit. was occurring.
また上記金属バンプの脱落、変形をなくすために、被覆
絶縁膜にＡｔ配線を表出する開孔を形成した時点で、表
出するＡｌ配線上にブローμの触針を立てて試験を行う
方法も行われるが、この方法によると開孔内に表出する
Ａｌ配線の表面に深い穴が形成され、該Ａｌ配線の表出
面上に被着されるバリアメタル層に特別薄い部分や欠陥
部を生じバリア効果が損なわれて、Ａｌ配線と金属（Ａ
ｕ）バンプが反応し、該金属（Ａｕ）バンプが脱落し易
くなるという問題がある。In addition, in order to prevent the metal bumps from falling off or deforming, a test is conducted by placing a blow μ stylus on the exposed Al wiring after forming an opening in the covering insulating film to expose the At wiring. However, according to this method, a deep hole is formed on the surface of the Al wiring exposed in the opening, and a particularly thin part or defective part is formed in the barrier metal layer deposited on the exposed surface of the Al wiring. occurs, the barrier effect is impaired, and the Al wiring and metal (A
u) There is a problem that the bumps react and the metal (Au) bumps tend to fall off.
更に又、バリアメタル層を被覆絶縁膜の開孔上のみに形
成し、該開孔上のバリアメタル層上にブローμの触針を
立てて試験を行う方法も試みられたが、この方法だと触
針によってバリアメタル層が破壊されてバリア機能を失
い、上記同様Ａｌ配線と金属（Ａｕ）バンプの反応によ
りバンプ脱落の障害を生ずる。Furthermore, a method was also attempted in which the barrier metal layer was formed only over the openings in the coating insulating film, and the test was conducted by placing a blow μ probe on the barrier metal layer above the openings, but this method was not successful. The barrier metal layer is destroyed by the stylus and loses its barrier function, and as described above, the reaction between the Al wiring and the metal (Au) bump causes the bump to fall off.
本発明が解決しようとする問題点は、上記のように従来
構造において、性能試験に際して金属バンプの脱落や変
形を生じ、該半導体装置の歩留り低下や、外部回路との
接続の信頬性低下を生じていた点である。The problem to be solved by the present invention is that, as described above, in the conventional structure, metal bumps may fall off or deform during performance tests, resulting in a decrease in the yield of the semiconductor device and a decrease in reliability of connection with external circuits. This is what was happening.
上記問題点は、被覆絶縁膜（３）の開孔（４）内に表出
する配線パターン（２）上に、バリアメタル層を（５）
介して金属バンプ（６）が配設されるチップ構造を有し
、該バリアメタル層（５）が該金属バンプ（６）に覆わ
れない該被覆絶縁膜（３）上に延在され試験用電極パッ
ド（５ｂ）を構成してなる本発明による半導体装置によ
って解決される。The problem mentioned above is that the barrier metal layer (5) is placed on the wiring pattern (2) exposed in the opening (4) of the covering insulating film (3).
It has a chip structure in which metal bumps (6) are disposed through the chip structure, and the barrier metal layer (5) is extended on the covering insulating film (3) that is not covered by the metal bumps (6). This problem is solved by the semiconductor device according to the present invention, which includes an electrode pad (5b).
即ち本発明に係るチ・ノブ構造の半導体装置においては
、被覆絶縁膜の開孔に表出する上層配線とその上に配役
接続される金属バンプとの間に、配線金属とバンプ金属
との反応を防止するために介在せしめられるバリアメタ
ル層を、金属バンプに覆われない被覆絶縁膜上にパッド
状に延在させた構造を有する。That is, in the semiconductor device having the chi-knob structure according to the present invention, a reaction between the wiring metal and the bump metal occurs between the upper layer wiring exposed in the opening of the covering insulating film and the metal bump connected thereon. It has a structure in which a barrier metal layer interposed to prevent the metal bumps is extended in a pad-like manner on the covering insulating film that is not covered with the metal bumps.
従って該半導体装置のブローμによる性能試験は、金属
バンプ完成後に、金属バンプに触れずに上記バリアメタ
ル層の延在部に針立てをして行うことができるので、該
性能試験によってバンプ接続部が劣化せしめられてハン
プの脱落を生じたり、バンプの変形を生じたりすること
がなくなり、該半導体装置の歩留りや外部回路への接続
の信頼度が向上する。Therefore, the performance test by blow μ of the semiconductor device can be performed after the completion of the metal bump by placing a needle on the extended portion of the barrier metal layer without touching the metal bump. This prevents the hump from falling off or deforming due to deterioration of the semiconductor device, thereby improving the yield of the semiconductor device and the reliability of connection to external circuits.
〔実施例〕 以下本発明を、図示実施例により具体的に説明する。〔Example〕 The present invention will be specifically explained below with reference to illustrated embodiments.
第１図は本発明に係るチップ構造の半導体装置の一実施
例の要部を示す模式平面図（ａｌ及び模式側断面図（ｂ
ｌで、第２図（ａ）〜（ｄ）はその製造方法の一実施例
を示す要部工程断面図である。FIG. 1 is a schematic plan view (al) and a schematic side sectional view (b) showing essential parts of an embodiment of a chip-structured semiconductor device according to the present invention.
1, and FIGS. 2(a) to 2(d) are cross-sectional views of main parts showing one embodiment of the manufacturing method.
第１図（ａｌ、（ｂｌにおいて、１は燐珪酸ガラス（Ｐ
ＳＧ）等よりなる層間絶縁膜、２はアルミニウム（Ａ１
）若しくはＡ１合金よりなる上層ＡＩ配線、３はＰＳＧ
等よりなる被覆絶縁膜、４は被覆絶縁膜に形成した開孔
、５は例えばチタン（Ｔｉ）と白金（Ｐｔ）の２層構造
を有するバリアメタルパターン、５ａは同パターンのバ
リア部、５ｂは同パターンの試験用パッド部、６は金（
Ａｕ）バンブを示す。In Figure 1 (al, (bl), 1 is phosphosilicate glass (P
2 is an interlayer insulating film made of aluminum (A1
) or upper layer AI wiring made of A1 alloy, 3 is PSG
4 is an opening formed in the covering insulating film, 5 is a barrier metal pattern having a two-layer structure of, for example, titanium (Ti) and platinum (Pt), 5a is a barrier portion of the same pattern, and 5b is a Test pad part with the same pattern, 6 is gold (
Au) indicates a bump.
同図に示すように本発明に係るチップ構造の半導体装置
は、該半導体チップにおける上層ＡＩ配線２の形成面上
を覆う被覆絶縁膜３に形成した上層ＡＩ配線２の一部を
表出する開孔４部において、上記ＡＩ配′＃！Ａ２の表
出部とＡｕバンプ６との間に従来通り介在せしめられる
バリ７メタルパターン５の１端部が、Ａｕバンプ６に覆
われない被覆絶縁膜３上に例えば図示のような形状に延
在されて試験用パッド部５ｂを構成した構造を有してい
る。As shown in the figure, the semiconductor device having a chip structure according to the present invention has an opening exposing a part of the upper layer AI wiring 2 formed in the covering insulating film 3 covering the surface on which the upper layer AI wiring 2 is formed in the semiconductor chip. In the hole 4 section, the above AI arrangement '#! One end of the burr 7 metal pattern 5, which is conventionally interposed between the exposed portion of A2 and the Au bump 6, is extended in the shape shown in the figure, for example, on the covering insulating film 3 that is not covered with the Au bump 6. It has a structure in which the test pad section 5b is configured by the test pad section 5b.
そのため本発明に係るチップ構造の半導体装置において
は、該半導体装置の構造完成時に上記バリアメタルパタ
ーン５の試験用パッド部５ｂにブローバによる針車てを
行って該半導体装置の性能試験を行うことができる。Therefore, in the semiconductor device having a chip structure according to the present invention, when the structure of the semiconductor device is completed, the test pad portion 5b of the barrier metal pattern 5 may be touched by a blower to perform a performance test of the semiconductor device. can.
従って従来構造のようにバンプ形成前にバンブ配設部に
針車てして性能試験を行ってパリアメクルの損傷を招い
たり、バンブ上に針車てして性能試験を行ってバンブを
脱落させたり変形させたりすることがないので、該半導
体装置の歩留りや外部回路への接続の信顛度が向上する
。Therefore, unlike the conventional structure, before forming bumps, a performance test is carried out by placing a needle wheel on the bump placement part, which may lead to damage to the barrier, or a performance test is carried out by placing a needle wheel on top of the bump, and the bumps fall off. Since there is no deformation, the yield of the semiconductor device and the reliability of connection to external circuits are improved.
以下に上記実施例の構造を形成する際の製造方法を、第
２図（ａ）〜（ｄｌに示す要部工程断面図を参照して説
明する。The manufacturing method for forming the structure of the above embodiment will be explained below with reference to the main process cross-sectional views shown in FIGS. 2(a) to 2(dl).
第２図（ａ）参照
図示しない半導体基板に素子が形成され、該半導体基板
上に形成されたＰＳＧ等よりなる眉間絶縁膜１上に下部
の図示しない前記半導体素子から導出された上層のＡ１
配線２が形成されている基板上に、気相成長法によりＰ
ＳＧ等よりなる厚さ１μｍ程度の被覆絶縁膜３を形成し
、通常のりソグラフィ技術により該被覆絶縁膜３にＡＩ
配線２の予め広い面積に形成した所定の領域を表出する
例えば５０〜１００μｍ角程度の開孔４開孔成した後、
該基板面にスパッタリング法により３０００人程度０厚
さのＴｉ層と３０００人程度０厚さのｐｔ層とを続けて
堆積せしめて上記開孔４の内部を含む被覆絶縁膜３の全
面上にＴｉとＰｔとの２層構造よりなるバリアメタル層
１０５を形成する。Refer to FIG. 2(a) An element is formed on a semiconductor substrate (not shown), and an upper layer A1 is formed on the glabella insulating film 1 made of PSG or the like formed on the semiconductor substrate, which is led out from the semiconductor element (not shown) in the lower part.
P is deposited on the substrate on which the wiring 2 is formed by vapor phase growth.
A covering insulating film 3 made of SG or the like with a thickness of about 1 μm is formed, and AI is applied to the covering insulating film 3 by ordinary glue lithography technique.
After forming 4 holes of, for example, about 50 to 100 μm square to expose a predetermined region formed in advance over a wide area of the wiring 2,
A Ti layer with a thickness of approximately 3,000 layers and a PT layer with a thickness of approximately 3,000 layers are successively deposited on the substrate surface by sputtering to form a Ti layer over the entire surface of the covering insulating film 3 including the inside of the opening 4. A barrier metal layer 105 having a two-layer structure of Pt and Pt is formed.
そして、次ぎに咳バリアメタル層１０５上に前記被覆絶
縁膜３の開孔４の上部を該開孔４よりもやや大きめに覆
い、且つバリアメタルパターンの試験用パッドとしての
延在部に対応する延在部分を有する第１のレジストパタ
ーン７を形成する。Then, on the cough barrier metal layer 105, the upper part of the opening 4 of the covering insulating film 3 is covered slightly larger than the opening 4, and the upper part of the opening 4 of the covering insulating film 3 is covered to correspond to the extension part of the barrier metal pattern as a test pad. A first resist pattern 7 having an extended portion is formed.
第２図（ｂ）参照
次いで上記第１のレジストパターン７をマスクにし、例
えば塩素系のガスによるドライエツチング処理を行って
バリアメタル層１０５を選択的にエツチング除去し、バ
リア部５ａと該バリア部５ａから引出された試験用パッ
ド部５ｂを有するバリアメタルパターン５を形成する。Referring to FIG. 2(b), the barrier metal layer 105 is selectively etched away by dry etching using, for example, a chlorine-based gas using the first resist pattern 7 as a mask, and the barrier metal layer 105 is selectively etched away. A barrier metal pattern 5 having a test pad portion 5b drawn out from 5a is formed.
第２図（Ｃ１参照
次いで上記バリアメタルパターン５を有する被覆絶縁膜
３上に該被覆絶縁膜３の開孔４上の金属バンド形成領域
を表出する例えば１１０μｍ角程度の開孔８を有する第
２のレジスト膜９を形成し、該第２のレジスト膜９をマ
スクにし通常の電気メツキ技術により上記開孔８内に表
出するバリアメタルパターン５上に＾Ｕを厚さ例えば２
０〜３０μｍ程度に成長させて高さ２０〜３０μｍ（７
）Ａｕバンプ６を形成する。FIG. 2 (See C1) Next, on the covering insulating film 3 having the barrier metal pattern 5, a hole 8 having a size of, for example, about 110 μm square is formed to expose a metal band formation region on the opening 4 of the covering insulating film 3. A resist film 9 of 2 is formed, and using the second resist film 9 as a mask, ^U is formed to a thickness of, for example, 2 on the barrier metal pattern 5 exposed in the opening 8 by ordinary electroplating technology.
Grow to about 0-30μm and height 20-30μm (7
) Au bumps 6 are formed.
第２図（ｄ）参照
次いで上記第２のレジスト膜９を除去し、上記Ａｕバン
プ６の下部から被覆絶縁膜３上に延在するバリアメタル
パターン５の試験用パッド部５ｂを表出せしめる。Referring to FIG. 2(d), the second resist film 9 is then removed to expose the test pad portion 5b of the barrier metal pattern 5 extending from the bottom of the Au bump 6 onto the covering insulating film 3.
以上説明のように本発明に係るチップ構造の半導体装置
においては、該半導体装置の構造完成時に金属バンプ下
部のバリアメタル層が被覆絶縁膜上に延在されてなる試
験用パッド部にプローバによる畦立てを行って該半導体
装置の性能試験を行うことができる。As described above, in the semiconductor device having a chip structure according to the present invention, when the structure of the semiconductor device is completed, a prober is used to form a ridge on the test pad portion formed by extending the barrier metal layer below the metal bump onto the covering insulating film. The performance of the semiconductor device can be tested by performing a stand-up.
従って性能試験に際して金属バンプ下部のバリアメタル
層に不完全部を形成することなく、且つ金属バンブに外
力を与えることがないので、金属バンプの脱落や変形が
防止され、該半導体装置の歩留りや外部回路への接続の
信頼度が向上する。Therefore, during the performance test, no imperfections are formed in the barrier metal layer below the metal bumps, and no external force is applied to the metal bumps, which prevents the metal bumps from falling off or deforming, thereby reducing the yield of the semiconductor device and the external appearance. The reliability of the connection to the circuit is improved.
第１図は本発明に係る半導体装置の一実施例の要部を示
す模式平面図（ａｌ及び模式側断面図（ｂ）、第２図（
ａｌ〜（ｄ）は本発明に係る半導体装置の製造方法の一
実施例を示す要部工程断面図、第３図は従来のチップ構
造の半導体装置の要部模式側断面図である。
図において、
１は層間絶縁膜、
２は上層Ａｔ配線、
３は被覆絶縁膜、
４は被覆絶縁膜の開孔、
５はバリアメタルパターン、
５ａはバリア部、
５ｂは試験用パッド部、
６は金属（Ａｕ）バンブ
を示す。
（ａ）−７面 図
（，１，） イ卵・ＩＰｉｆｒ面 図木イこ日月に
イ季う半４林Ｍ崖Ｌｆ）−ｊｅ方方今９の中宮Ｈ瞬式図
第ｊ図
０辷采Ｑ＋・ツブ杉りた十尋偵（装屑ンいｔ秤膜戊伊・
ｊ藺丁面図あ ３ 図
第 ２図FIG. 1 is a schematic plan view (al) showing essential parts of an embodiment of a semiconductor device according to the present invention, a schematic side sectional view (b), and FIG.
al to (d) are main part step sectional views showing one embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 3 is a schematic side sectional view of main parts of a conventional chip-structured semiconductor device. In the figure, 1 is an interlayer insulating film, 2 is an upper layer At wiring, 3 is a covering insulating film, 4 is an opening in the covering insulating film, 5 is a barrier metal pattern, 5a is a barrier part, 5b is a test pad part, 6 is a test pad part A metal (Au) bump is shown. (a) - 7th plane Figure (, 1,) Ieki/IPifr plane Fig. Iko Sun/Moon ni Han 4 Lin M cliff Lf) - je direction now 9 Chugu H instantaneous map No. j Fig. 0辷采Q+・Tsubusugi Ritta Tenhi Detective
Figure 3 Figure 2
Claims (1)
ン（２）上に、バリアメタル層（５）を介して金属バン
プ（６）が配設されるチップ構造を有し、該バリアメタ
ル層（５）が該金属バンプ（６）に覆われない該被覆絶
縁膜（３）上に延在され試験用電極パッド（５ｂ）を構
成してなることを特徴とする半導体装置。It has a chip structure in which metal bumps (6) are arranged on a wiring pattern (2) exposed in an opening (4) of a covering insulating film (3) via a barrier metal layer (5), A semiconductor device characterized in that the barrier metal layer (5) extends over the covering insulating film (3) not covered by the metal bumps (6) to constitute a test electrode pad (5b).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61207097A JPS6362341A (en) | 1986-09-03 | 1986-09-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61207097A JPS6362341A (en) | 1986-09-03 | 1986-09-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6362341A true JPS6362341A (en) | 1988-03-18 |
Family
ID=16534150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61207097A Pending JPS6362341A (en) | 1986-09-03 | 1986-09-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6362341A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02154426A (en) * | 1988-12-06 | 1990-06-13 | Fuji Electric Co Ltd | Manufacture of semiconductor integrated circuit device |
| EP0530758A2 (en) * | 1991-09-02 | 1993-03-10 | Fujitsu Limited | Semiconductor package for flip-chip mounting process |
| US6313541B1 (en) * | 1999-06-08 | 2001-11-06 | Winbond Electronics Corp. | Bone-pad with pad edge strengthening structure |
| KR100327442B1 (en) * | 1995-07-14 | 2002-06-29 | 구본준, 론 위라하디락사 | Bump structure of semiconductor device and fabricating method thereof |
| US6509645B2 (en) * | 1998-07-09 | 2003-01-21 | Nippon Steel Corporation | Spherical semiconductor device and method for fabricating the same |
-
1986
- 1986-09-03 JP JP61207097A patent/JPS6362341A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02154426A (en) * | 1988-12-06 | 1990-06-13 | Fuji Electric Co Ltd | Manufacture of semiconductor integrated circuit device |
| EP0530758A2 (en) * | 1991-09-02 | 1993-03-10 | Fujitsu Limited | Semiconductor package for flip-chip mounting process |
| US5475236A (en) * | 1991-09-02 | 1995-12-12 | Fujitsu Limited | Semiconductor chip for mounting on a semiconductor package substrate by a flip-clip process |
| KR100327442B1 (en) * | 1995-07-14 | 2002-06-29 | 구본준, 론 위라하디락사 | Bump structure of semiconductor device and fabricating method thereof |
| US6509645B2 (en) * | 1998-07-09 | 2003-01-21 | Nippon Steel Corporation | Spherical semiconductor device and method for fabricating the same |
| US6313541B1 (en) * | 1999-06-08 | 2001-11-06 | Winbond Electronics Corp. | Bone-pad with pad edge strengthening structure |
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