JPH0732157B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0732157B2 JPH0732157B2 JP61169126A JP16912686A JPH0732157B2 JP H0732157 B2 JPH0732157 B2 JP H0732157B2 JP 61169126 A JP61169126 A JP 61169126A JP 16912686 A JP16912686 A JP 16912686A JP H0732157 B2 JPH0732157 B2 JP H0732157B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- electrode
- window
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置及びその製造方法に関し、特に突起
電極を有する半導体装置及びその製造方法に関する。The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a bump electrode and a manufacturing method thereof.
最近、半導体装置の高密度実装のためやごく最近のカー
ド用ICの薄型化のために、従来のワイヤーボンディング
に代り、テープ自動ボンディング（TAB）の技術が使用
されてきている。このために、半導体ウェーハプロセス
では、ICチップのボンディング領域に突起電極（以降バ
ンプと称す）を設ける方式が一般的となっている。Recently, tape automatic bonding (TAB) technology has been used in place of conventional wire bonding for high-density mounting of semiconductor devices and, more recently, for thinner ICs for cards. For this reason, in a semiconductor wafer process, a method of providing a bump electrode (hereinafter referred to as a bump) in a bonding region of an IC chip is generally used.
第４図は従来の半導体装置の一例の断面図である。FIG. 4 is a sectional view of an example of a conventional semiconductor device.
この従来例は、シリコン基板１上に内部の半導体素子と
接続したAl電極３を設け、その上にAl電極３上に開孔部
を有する絶縁膜２を設け、開孔部と開孔部周辺の絶縁膜
２とを覆うように金属層４″,5″,6″及びバンプ８″を
積層するように設け、金属層４″,5″,6″及びバンプ
８″の側面を覆うようにポリイミド膜９″を設けた構造
をしている。In this conventional example, an Al electrode 3 connected to an internal semiconductor element is provided on a silicon substrate 1, an insulating film 2 having an opening is provided on the Al electrode 3, and the opening and the periphery of the opening are provided. The metal layers 4 ", 5", 6 "and the bumps 8" are provided so as to be laminated so as to cover the insulating film 2 and the side surfaces of the metal layers 4 ", 5", 6 "and the bumps 8" are covered. The structure is such that a polyimide film 9 ″ is provided.
第５図（ａ）〜（ｇ）は従来の半導体装置の製造方法の
一例を説明するための半導体チップの断面図である。5A to 5G are cross-sectional views of a semiconductor chip for explaining an example of a conventional method for manufacturing a semiconductor device.
この例はまず、第５図（ａ）に示すように、シリコン基
板１上のボンディング領域の絶縁膜２をホトエッチング
法により開孔し、ボンディング領域のAl電極３表面を露
出させる。In this example, first, as shown in FIG. 5A, the insulating film 2 in the bonding region on the silicon substrate 1 is opened by a photoetching method to expose the surface of the Al electrode 3 in the bonding region.
次に、第５図（ｂ）に示すように、Al電極３との接着用
の金属層４″、中間にあって障壁用となる金属層５″及
びめっき法で形成されるバンプと直接接する金属層６″
例えば金を全面に連続的に被着する。Next, as shown in FIG. 5 (b), a metal layer 4 ″ for adhesion to the Al electrode 3, a metal layer 5 ″ in the middle and for a barrier, and a metal directly contacting the bump formed by the plating method. Layer 6 "
For example, gold is continuously deposited on the entire surface.
次に、第５図（ｃ）に示すように、ホトレジスト７″を
所定のパターンでバンプを形成しようとしている開孔部
を除いて形成する。Next, as shown in FIG. 5 (c), a photoresist 7 "is formed in a predetermined pattern except for the openings where the bumps are to be formed.
この後、第５図（ｄ）に示すように、ホトレジスト７″
を保護膜として金あるいは銅のめっきを施し、所望の高
さの金属のバンプ８″を形成する。After this, as shown in FIG. 5 (d), a photoresist 7 "
Is plated with gold or copper as a protective film to form metal bumps 8 ″ having a desired height.
次に、第５図（ｅ）に示すように、不要となったホトレ
ジスト７″を除去した後、金属層６″、金属層５″及び
第１の金属層４″を順次エッチングし、バンプを形成す
る。Next, as shown in FIG. 5 (e), after removing the unnecessary photoresist 7 ″, the metal layer 6 ″, the metal layer 5 ″, and the first metal layer 4 ″ are sequentially etched to form bumps. Form.
この後、通常は素子表面の保護とボンディング時の機械
的衝撃やストレスを吸収する目的で第５図（ｆ）に示す
ように、ポリイミド膜９″をバンプを覆うように半導体
チップの表面に形成する。Thereafter, a polyimide film 9 ″ is usually formed on the surface of the semiconductor chip so as to cover the bumps, as shown in FIG. 5 (f), for the purpose of protecting the element surface and absorbing mechanical shock and stress during bonding. To do.
次に、第５図（ｇ）に示すように、バンプ８″の上部を
開孔したホトレジスト10″を形成する。Next, as shown in FIG. 5 (g), a photoresist 10 "in which the upper portion of the bump 8" is opened is formed.
最後に、ホトレジスト10″をマスクとしてポリイミド膜
９″をエッチングした後ホトレジスト10″を除去すれ
ば、第４図に示すような、従来の半導体装置の一例がで
きる。Finally, by etching the polyimide film 9 "using the photoresist 10" as a mask and then removing the photoresist 10 ", an example of a conventional semiconductor device as shown in FIG. 4 can be obtained.
上述した従来の半導体装置及びその製造方法では、第１
の導体層であるAl電極上に開孔部を有する絶縁膜表面に
直接接着用の第２の導体層、障壁用の第３の導体層を含
む複数の導体層を積層するので、その導体層に使う金属
の種類がパターニングするためのエッチング等の条件に
よって非常に限られるという欠点がある。例えばPtを第
３の導体層に使用する場合には、湿式エッチングによっ
てパターニングするには熱王水を使うので適当な保護マ
スクが無く、イオンミリングあるいは最近の反応性イオ
ンエッチング等の一般的な乾式エッチングではシリコン
基板上に半導体素子を形成する過程で生じる種々の段差
部にエッチングされた白金が再付着して短絡不良を起す
ので、Ptを含むTi−Pt−Au三層によって構成される複数
の導体層を使うことができないという欠点がある。In the above-described conventional semiconductor device and manufacturing method thereof, the first
Since a plurality of conductor layers including a second conductor layer for direct bonding and a third conductor layer for barrier are laminated on the surface of an insulating film having openings on the Al electrode which is the conductor layer of There is a drawback in that the kind of metal used for is very limited depending on conditions such as etching for patterning. For example, when Pt is used for the third conductor layer, thermal aqua regia is used for patterning by wet etching, so there is no suitable protective mask, and general dry etching such as ion milling or recent reactive ion etching is used. In etching, platinum that has been etched in various steps generated during the process of forming a semiconductor element on a silicon substrate redeposits and causes a short circuit failure.Therefore, a plurality of Pt-containing Ti-Pt-Au trilayers are used. The disadvantage is that no conductor layer can be used.
又、この従来例のようにバンプの側面をポリイミド膜で
覆った構造では、ホトリソグラフィー工程中の目合せず
れや、ポリイミド膜のエッチング時のアンダーカット等
によりポリイミド膜をバンプの側面に接して安定に形成
することが非常に困難であり、これらに起因するボンデ
ィング不良等によって製造歩留りが低下するという欠点
もある。Further, in the structure in which the side surface of the bump is covered with the polyimide film as in this conventional example, the polyimide film is stably contacted with the side surface of the bump due to misalignment during the photolithography process or undercut during etching of the polyimide film. However, there is also a drawback that the manufacturing yield is lowered due to defective bonding or the like caused by these.
本発明の目的は、半導体基板上の第１の導体層とバンプ
との間をつなぐ複数の導体層としてTi-Pt-Auの三層構造
が使えてしかもポリイミド膜がバンプの側面に安定に接
して形成でき製造歩留りの高い半導体装置及びその製造
方法を提供することにある。An object of the present invention is to use a three-layer structure of Ti-Pt-Au as a plurality of conductor layers connecting the first conductor layer on the semiconductor substrate and the bumps, and moreover, the polyimide film stably contacts the side surface of the bump. It is to provide a semiconductor device which can be formed by a high manufacturing yield and a manufacturing method thereof.
本発明の特徴は、半導体素子が形成されている半導体基
板上に前記半導体素子と接続したアルミ（Al）電極を設
け、前記アルミ電極を覆いかつ前記アルミ電極上の所定
の位置にコンタクト用の窓を有する絶縁性の第１の膜と
樹脂性の第２の膜との積層膜を設け、前記積層膜の前記
窓と前記樹脂性の第２の膜の前記窓周辺とを覆うように
所定のパターンで前記アルミ電極との接着用のチタン
（Ti）層と障壁用の白金（Pt）層とバンプとの接着用の
金（Au）層との複数導体層を設け、前記金属上に金のバ
ンプを設けた半導体装置にある。A feature of the present invention is that an aluminum (Al) electrode connected to the semiconductor element is provided on a semiconductor substrate on which a semiconductor element is formed, the aluminum electrode is covered and a contact window is provided at a predetermined position on the aluminum electrode. A laminated film of an insulating first film and a resinous second film is provided, and a predetermined film is formed so as to cover the window of the laminated film and the periphery of the window of the resinous second film. A pattern is provided with a plurality of conductor layers of a titanium (Ti) layer for adhesion to the aluminum electrodes, a platinum (Pt) layer for barriers, and a gold (Au) layer for adhesion to bumps, and a gold layer is formed on the metal. It is in a semiconductor device provided with bumps.
本発明の他の特徴は、半導体素子が形成された半導体基
板上に前記半導体素子と接続したアルミ（Al）電極を形
成する工程と、前記アルミ電極を覆いかつ前記アルミ電
極上の所定の位置にコンタクト用の窓を有する絶縁性の
第１の膜と樹脂性の第２の膜との積層膜を形成する工程
と、前記積層膜の前記窓と前記樹脂性の第２の膜の前記
窓周辺とを覆うように前記アルミ電極との接着用のチタ
ン（Ti）層と障壁用の白金（Pt）層と突起電極との接着
用の金（Au）層とを順次積層する工程と、前記金層上に
前記窓を囲むような開孔部を有するホトレジスト膜を形
成する工程と、前記ホトレジスト膜の前記開口部の内部
から該開口部を覆うように金のバンプを形成する工程
と、前記ホトレジスト膜を除去した後に前記バンプをマ
スクとして乾式エッチングで前記金層、白金層およびチ
タン層を選択的に除去する半導体装置の製造方法にあ
る。Another feature of the present invention is a step of forming an aluminum (Al) electrode connected to the semiconductor element on a semiconductor substrate on which a semiconductor element is formed, and a step of covering the aluminum electrode and at a predetermined position on the aluminum electrode. Forming a laminated film of an insulating first film having a window for contact and a resinous second film, and surrounding the window of the laminated film and the resinous second film A step of sequentially laminating a titanium (Ti) layer for adhesion to the aluminum electrode, a platinum (Pt) layer for barrier and a gold (Au) layer for adhesion to the bump electrode so as to cover Forming a photoresist film having an opening on the layer so as to surround the window, forming a gold bump from the inside of the opening of the photoresist film so as to cover the opening, and the photoresist Dry etch using the bumps as a mask after removing the film Said gold layer at grayed, in a method of manufacturing a semiconductor device for selectively removing the platinum layer and titanium layer.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の半導体装置の第１の実施例の断面図で
ある。FIG. 1 is a sectional view of the first embodiment of the semiconductor device of the present invention.
この第１の実施例は、半導体素子を形成したシリコン基
板１上に半導体素子と接続したAl電極を設け、Al電極３
の所定の位置に開孔部を有しかつAl電極３とシリコン基
板１とを覆うように絶縁膜２を設け、絶縁膜２の開孔部
より狭いAl電極３のコンタクト用の窓を有しかつ絶縁膜
２を覆うようにポリイミド膜９を設け、コンタクト用の
窓及び窓周辺のポリイミド膜９を覆うようにAl電極３と
の接着用の金属層４、障壁用の金属層５及びバンプと直
接接する金属層６の３層を積層した複数の金属層を設
け、金属層4,5及び６の上にバンプ８を設けた構造をし
ている。In the first embodiment, an Al electrode connected to a semiconductor element is provided on a silicon substrate 1 on which a semiconductor element is formed, and an Al electrode 3
Has an opening portion at a predetermined position and an insulating film 2 is provided so as to cover the Al electrode 3 and the silicon substrate 1, and has a contact window for the Al electrode 3 narrower than the opening portion of the insulating film 2. Further, a polyimide film 9 is provided so as to cover the insulating film 2, and a metal layer 4 for adhesion with the Al electrode 3, a metal layer 5 for barrier, and a bump are provided so as to cover the window for contact and the polyimide film 9 around the window. A structure is provided in which a plurality of metal layers in which three layers of the metal layer 6 that are in direct contact are stacked are provided, and the bumps 8 are provided on the metal layers 4, 5, and 6.
第２図は本発明の半導体装置の第２の実施例の断面図で
ある。FIG. 2 is a sectional view of a second embodiment of the semiconductor device of the present invention.
第２の実施例は、シリコン基板１上にAl電極３と絶縁膜
２とを設けるところまでは上述の第１の実施例と同じで
あるが、絶縁膜２より上が、絶縁膜２の開孔部を囲むよ
うに大きく開孔したポリイミド膜９′を絶縁膜２上に設
け、絶縁膜２の開孔部をコンタクト用の窓としてその窓
と窓周辺の絶縁膜２及びポリイミド膜９′と覆うように
積層した金属層４′,5′及び６′を設け、金属層４′、
５′及び６′の上にバンプ８′を設けた構造になってい
る。The second embodiment is the same as the first embodiment described above up to the point where the Al electrode 3 and the insulating film 2 are provided on the silicon substrate 1, but the insulating film 2 is opened above the insulating film 2. A polyimide film 9'having a large opening so as to surround the hole is provided on the insulating film 2, and the opening of the insulating film 2 is used as a contact window for the window and the insulating film 2 around the window and the polyimide film 9 '. The metal layers 4 ', 5'and 6'which are laminated so as to cover are provided, and the metal layer 4',
The structure is such that bumps 8'are provided on 5'and 6 '.
第３図（ａ）〜（ｇ）は本発明の半導体装置の製造方法
の一実施例を説明するための工程順に示した半導体チッ
プの断面図である。3 (a) to 3 (g) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention.
この実施例は、先ず、第３図（ａ）に示すように、シリ
コン基板１上に形成されかつ半導体素子と接続したAl電
極３上の所定の位置の絶縁膜２を通常のエッチング法に
より開孔し、Al電極３の表面を露出する。In this embodiment, as shown in FIG. 3 (a), first, an insulating film 2 formed at a predetermined position on an Al electrode 3 formed on a silicon substrate 1 and connected to a semiconductor element is opened by a usual etching method. The surface of the Al electrode 3 is exposed by making a hole.
次に、第３図（ｂ）に示すように、ポリイミド膜９を回
転塗布法により全面に形成し、適当な熱処理によってキ
ュアされた後、コンタクト用の窓に相当する開孔部をも
つようにホトレジストを通常のホトリソグラフィプロセ
スにより形成する。Next, as shown in FIG. 3B, a polyimide film 9 is formed on the entire surface by a spin coating method, and after being cured by an appropriate heat treatment, an opening corresponding to a contact window is formed. The photoresist is formed by a conventional photolithography process.
次に、第３図（ｃ）に示すように、ホトレジスト７をマ
スクとしてポリイミド膜９をエッチングした後、不要と
なったホトレジスト７を除去する。Next, as shown in FIG. 3C, after the polyimide film 9 is etched using the photoresist 7 as a mask, the photoresist 7 that is no longer needed is removed.
次に、第３図（ｄ）に示すように、Al電極との接着用の
金属層４、障壁用の金属層５及びバンプと直接接する金
属６を全面に連続的に堆積する。次に、第３図（ｅ）に
示すように、コンタクト用の窓を囲むような開孔部を有
するホトレジスト10を形成する。Next, as shown in FIG. 3 (d), a metal layer 4 for adhering to the Al electrode, a metal layer 5 for barrier, and a metal 6 in direct contact with the bump are continuously deposited on the entire surface. Next, as shown in FIG. 3 (e), a photoresist 10 having an opening portion surrounding the contact window is formed.
次に、第３図（ｆ）に示すように、ホトレジスト10を保
護膜として金のバンプ８をめっき法で形成する。Next, as shown in FIG. 3 (f), gold bumps 8 are formed by plating using the photoresist 10 as a protective film.
次に、第３図（ｇ）に示すように、ホトレジスト10を除
去する。Next, as shown in FIG. 3 (g), the photoresist 10 is removed.
最後に、露出した部分の金属層6,5及び４を順次除去す
れば、第１図に示すような本発明の半導体装置の第１の
実施例ができる。Finally, the exposed portions of the metal layers 6, 5 and 4 are sequentially removed to obtain the first embodiment of the semiconductor device of the present invention as shown in FIG.
以上説明したように本発明は、ポリイミド膜をバンプ下
の複数の金属層を積層した導体層の下に形成するので、
導体層のエッチングの時に、半導体チップの表面を保護
すると共に段差のある部分が均らされ、乾式エッチング
時の段差部への再付着の問題が無くなって乾式エッチン
グが使えるようになり、導体層としてTi-Pt-Auの三層構
造が使えるようになるという効果がある。As described above, the present invention forms the polyimide film under the conductor layer in which a plurality of metal layers under the bump are laminated,
When the conductor layer is etched, it protects the surface of the semiconductor chip and evens out the stepped portion, eliminating the problem of redeposition on the stepped portion during dry etching, and dry etching can be used. The effect is that the three-layer structure of Ti-Pt-Au can be used.
又、バンプ側面の下の部分にポリイミド膜が接して設け
られているので、これがボンディング時の機械的及び熱
的衝撃やストレスを緩和し、ボンディング剥れ不良を防
止すると共に従来のようにポリイミド膜をバンプの側面
全体に接して形成するような場合に問題となっていた目
合せずれやアンダーカットによる製造歩留りの低下がほ
とんど起こらないという効果もある。Also, since the polyimide film is provided in contact with the lower part of the bump side surface, this alleviates mechanical and thermal shocks and stress during bonding, prevents defective peeling of the bonding, and prevents the polyimide film from being damaged as in the conventional case. There is also an effect that there is almost no decrease in manufacturing yield due to misalignment or undercut, which has been a problem when the bumps are formed in contact with the entire side surface of the bump.
第１図及び第２図はそれぞれ本発明の半導体装置の第１
及び第２の実施例の断面図、第３図（ａ）〜（ｇ）は本
発明の半導体装置の製造方法の一実施例を説明するため
の工程順に示した半導体チップの断面図、第４図は従来
の半導体装置の一例の断面図、第５図（ａ）〜（ｇ）は
従来の半導体装置の製造方法の一例を説明するための半
導体チップの断面図である。 １……シリコン基板、２……絶縁膜、４……Al電極、4,
4′,4″,5,5′,5″,6,6′,6″……金属層、7,7″……ホ
トレジスト、8,8′,8″……バンプ、9,9′,9″……ポリ
イミド膜、10,10″……ホトレジスト。1 and 2 show the first semiconductor device of the present invention, respectively.
And a sectional view of the second embodiment, and FIGS. 3 (a) to 3 (g) are sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention. FIG. 5 is a sectional view of an example of a conventional semiconductor device, and FIGS. 5A to 5G are sectional views of a semiconductor chip for explaining an example of a method of manufacturing a conventional semiconductor device. 1 ... Silicon substrate, 2 ... Insulating film, 4 ... Al electrode, 4,
4 ′, 4 ″, 5,5 ′, 5 ″, 6,6 ′, 6 ″ …… metal layer, 7,7 ″ …… photoresist, 8,8 ′, 8 ″ …… bump, 9,9 ′, 9 ″ …… Polyimide film, 10,10 ″ …… Photoresist.
Claims (2)
に前記半導体素子と接続したアルミ（Al）電極を設け、
前記アルミ電極を覆いかつ前記アルミ電極上の所定の位
置にコンタクト用の窓を有する絶縁性の第１の膜と樹脂
性の第２の膜との積層膜を設け、前記積層膜の前記窓と
前記樹脂性の第２の膜の前記窓周辺とを覆うように所定
のパターンで前記アルミ電極との接着用のチタン（Ti）
層と障壁用の白金（Pt）層と突起電極との接着用の金
（Au）層との複数導体層を設け、前記金層上に金の突起
電極を設けたことを特徴とする半導体装置。1. An aluminum (Al) electrode connected to the semiconductor element is provided on a semiconductor substrate on which the semiconductor element is formed,
A laminated film of an insulating first film and a resinous second film that covers the aluminum electrode and has a contact window at a predetermined position on the aluminum electrode is provided, and the window of the laminated film is provided. Titanium (Ti) for adhering to the aluminum electrode in a predetermined pattern so as to cover the window of the resinous second film.
Layer and a platinum (Pt) layer for a barrier and a plurality of conductor layers of a gold (Au) layer for adhering the bump electrode are provided, and a gold bump electrode is provided on the gold layer. .
記半導体素子と接続したアルミ（Al）電極を形成する工
程と、前記アルミ電極を覆いかつ前記アルミ電極上の所
定の位置にコンタクト用の窓を有する絶縁性の第１の膜
と樹脂性の第２の膜との積層膜を形成する工程と、前記
積層膜の前記窓と前記樹脂性の第２の膜の前記窓周辺と
を覆うように前記アルミ電極との接着用のチタン（Ti）
層と障壁用の白金（Pt）層と突起電極との接着用の金
（Au）層とを順次積層する工程と、前記金層上に前記窓
を囲むような開孔部を有するホトレジスト膜を形成する
工程と、前記ホトレジスト膜の前記開口部の内部から該
開口部を覆うように金の突起電極を形成する工程と、前
記ホトレジスト膜を除去した後に前記突起電極をマスク
として乾式エッチングで前記金層、白金層およびチタン
層を選択的に除去することを特徴とする半導体装置の製
造方法。2. A step of forming an aluminum (Al) electrode connected to the semiconductor element on a semiconductor substrate on which a semiconductor element is formed, and a step of covering the aluminum electrode and making a contact at a predetermined position on the aluminum electrode. Forming a laminated film of an insulating first film having a window and a resinous second film, and covering the window of the laminated film and the periphery of the window of the resinous second film Titanium (Ti) for adhesion with the aluminum electrode
A layer, a platinum (Pt) layer for a barrier, and a gold (Au) layer for adhering the bump electrodes to each other, and a photoresist film having an opening portion surrounding the window on the gold layer. A step of forming, a step of forming a gold protruding electrode from the inside of the opening of the photoresist film so as to cover the opening, and a step of dry etching using the protruding electrode as a mask after removing the photoresist film. A method for manufacturing a semiconductor device, which comprises selectively removing a layer, a platinum layer and a titanium layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61169126A JPH0732157B2 (en) | 1986-07-17 | 1986-07-17 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61169126A JPH0732157B2 (en) | 1986-07-17 | 1986-07-17 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6325954A JPS6325954A (en) | 1988-02-03 |
| JPH0732157B2 true JPH0732157B2 (en) | 1995-04-10 |
Family
ID=15880761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61169126A Expired - Lifetime JPH0732157B2 (en) | 1986-07-17 | 1986-07-17 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0732157B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0828366B2 (en) * | 1988-04-27 | 1996-03-21 | カシオ計算機株式会社 | Method for forming electrode of semiconductor device |
| JPH02125621A (en) * | 1988-11-04 | 1990-05-14 | Nec Corp | Bump electrode forming method for semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5850756A (en) * | 1981-09-19 | 1983-03-25 | Ricoh Elemex Corp | Forming method for bump |
-
1986
- 1986-07-17 JP JP61169126A patent/JPH0732157B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6325954A (en) | 1988-02-03 |
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