JPS6353928A - Dry etching - Google Patents
Dry etchingInfo
- Publication number
- JPS6353928A JPS6353928A JP19678486A JP19678486A JPS6353928A JP S6353928 A JPS6353928 A JP S6353928A JP 19678486 A JP19678486 A JP 19678486A JP 19678486 A JP19678486 A JP 19678486A JP S6353928 A JPS6353928 A JP S6353928A
- Authority
- JP
- Japan
- Prior art keywords
- dry etching
- gas
- substrate
- film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001312 dry etching Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000010408 film Substances 0.000 claims abstract description 14
- 239000010409 thin film Substances 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052681 coesite Inorganic materials 0.000 abstract description 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 6
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 6
- 229910052682 stishovite Inorganic materials 0.000 abstract description 6
- 229910052905 tridymite Inorganic materials 0.000 abstract description 6
- 230000002950 deficient Effects 0.000 abstract description 5
- 239000004215 Carbon black (E152) Substances 0.000 abstract description 3
- 229930195733 hydrocarbon Natural products 0.000 abstract description 3
- -1 hydrocarbon fluoride Chemical class 0.000 abstract 2
- 238000009832 plasma treatment Methods 0.000 abstract 2
- 230000007547 defect Effects 0.000 description 14
- 239000013078 crystal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、シリコン基板（以下、８１基板）上のＳｉ欠
陥層のドライエツチング方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for dry etching a Si defect layer on a silicon substrate (hereinafter referred to as 81 substrate).
（従来の技術とその問題点）
現在、プラズマエツチング方法はＬＳＩ製造において不
可欠の技術となっている。特にＬＳＩの微細化が急速に
進んで最小寸法が１〜２μｍ以下の微細加工が要求され
、そのために、フロロカーボン系ガス等の反応性ガスの
イオンで試料表面を照射する方向性エツチング方法が用
いられている。(Prior art and its problems) Currently, plasma etching has become an indispensable technology in LSI manufacturing. In particular, the miniaturization of LSIs is progressing rapidly, and microfabrication with a minimum dimension of 1 to 2 μm or less is required. For this purpose, a directional etching method is used in which the sample surface is irradiated with ions of a reactive gas such as a fluorocarbon gas. ing.
この技術はりアクティブ・イオン・エツチング（ＲＩＥ
）と呼ばれ、これには通常平行平板型の装置が用いられ
ている。即ち、高周波電力が印加される陰極と、それに
対向する接地電極（陽極）とを設廟た真空容器に、例え
ば、１Ｏ−２Ｔｏｒｒ程度のＣＦ４や０２Ｆ５等のフロ
ロカーボン系ガスを導入し、平行平板電極に高周波電力
を印加してグロー放電を発生させると、電子とイオンの
易動度の差により陰極が負にバイアスされ、陰極上に暗
部を生ずると共に自己バイアス電圧即ち陰極降下電圧（
Ｖｄｃ）を生じ、このＶｄｃによってプラズマ内の反応
性正イオンが加速されて陰極上の試料を衝撃しこれをエ
ツチングする。現在は、Ｓｉ基板上のＳｉＯ２膜がフォ
トレジストパターンスクとしてＣＨＦ３＋Ｏ□ガスでエ
ツチングされている。This technology is active ion etching (RIE).
), and a parallel plate type device is usually used for this. That is, a fluorocarbon gas such as CF4 or 02F5 of about 10-2 Torr is introduced into a vacuum container equipped with a cathode to which high-frequency power is applied and a ground electrode (anode) facing it, and a parallel plate electrode is introduced. When high-frequency power is applied to generate a glow discharge, the cathode is negatively biased due to the difference in mobility between electrons and ions, creating a dark area on the cathode and increasing the self-bias voltage, that is, the cathode drop voltage (
Vdc) is generated, and reactive positive ions in the plasma are accelerated by this Vdc and impact the sample on the cathode, etching it. Currently, the SiO2 film on the Si substrate is etched with CHF3+O□ gas as a photoresist pattern mask.
（発明が解決しようとする問題点）
しかし、例えば、ＣＦ３″′イオンのＳ１表面の照射に
よって、Ｓｉ表面にはＣＦ３”が分解し・て生じたＣや
Ｆが付着し、かつ、Ｓｉ表面下にもこれらが分布する。(Problem to be solved by the invention) However, for example, when the S1 surface is irradiated with CF3'' ions, C and F produced by the decomposition of CF3'' adhere to the Si surface, and These are also distributed.
また前述のＶｄｃ即ち数百■にも達する加速電圧によっ
て、Ｓ１表面には結晶欠陥層を形成する。このため配線
用金属との間の接触抵抗が極めて大きくなったり、その
場所に形成されるトランジスタのｐ−ｎ接合に太きいリ
ーク電流を生じたり、また結晶自体のライフタイムが極
めて短くなる等の問題が生ずる。Further, due to the aforementioned Vdc, that is, the accelerating voltage reaching several hundred square meters, a crystal defect layer is formed on the S1 surface. As a result, the contact resistance between the wiring metal becomes extremely large, a large leakage current occurs in the p-n junction of the transistor formed at that location, and the lifetime of the crystal itself becomes extremely short. A problem arises.
この障害の除去には従来はフォーミングガス（Ｎ２＋Ｈ
２）を用いるアニールが有効であると言われていたが、
充分に上述の接触抵抗を低めるまでには至っていないの
が現状である。Conventionally, forming gas (N2+H
It was said that annealing using 2) is effective, but
At present, it has not been possible to sufficiently reduce the above-mentioned contact resistance.
ＫＯＨ溶液等を用いるウェットエツチングも欠陥除去対
策として試みられたが、１〜２μｍ角の微細領域のエツ
チングは制御か極めて厳しく実現が難しい。これに対し
バレルタイプのドライエツチング装置を用いてＣＦ４＋
０２で欠陥層のエツチングを行うことも試みられたが、
アンダーカットが入ってしまうという報告がある。Wet etching using a KOH solution or the like has also been attempted as a defect removal measure, but etching of a minute area of 1 to 2 μm square is extremely difficult to control and difficult to realize. On the other hand, using a barrel type dry etching device, CF4+
Etching of the defective layer was also attempted in 02, but
There have been reports of undercuts appearing.
（発明の目的）
本発明は、ドライエツチング後の欠陥層除去工程におい
て、アンダーカットを生ずることなく欠陥層をドライエ
ツチングする方法の提供を目的とする。(Object of the Invention) An object of the present invention is to provide a method for dry etching a defective layer without causing undercuts in a defect layer removal step after dry etching.
（発明の構成）
本発明は、平行平板型ドライエツチング装置を用いて、
被処理基板上の８１０２膜ないしＰＳＧ （Ｐのドープ
されたＳ＋０２）膜をドライエツチングする方法におい
て、該薄膜のエツチング後に、引続き弗化炭化水素のガ
スと０２ガスの混合ガス：こより該被処理基板をプラズ
マ処理するドライエツチング方法によって、前記目的を
達成したものである。(Structure of the Invention) The present invention uses a parallel plate type dry etching apparatus to
In a method of dry etching an 8102 film or a PSG (S+02 doped with P) film on a substrate to be processed, after etching the thin film, a mixed gas of fluorohydrocarbon gas and 02 gas is added to the substrate to be processed. The above object has been achieved by using a dry etching method in which plasma processing is performed.
前記混合ガスの０２濃度を、４０％ないし８０％の範囲
内にするとき一層の効果かえられろ。Further effects can be obtained when the O2 concentration of the mixed gas is within the range of 40% to 80%.
（作用）
前述の方法によれば、ＳｉＯ２膜やＰＳＧ膜のエツチン
グ後の欠陥層の除去において、サイドエツチングを防ぎ
ながら、制御性の良い低エツチング速度で、Ｓｉ基板に
ダメージを与えることなく欠陥層を除去出来、しかもエ
ツチング表面に炭化物皮膜を形成することもない。(Function) According to the above-mentioned method, when removing a defect layer after etching a SiO2 film or a PSG film, the defect layer can be removed without damaging the Si substrate at a low etching rate with good control while preventing side etching. can be removed without forming a carbide film on the etched surface.
（実施例） 以下、本発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.
第１図は、Ｓｉ基板１上のＳｉＯ２膜をフォトレジスト
パターンをマスクとしてＣＨＦ３；９０ｓｃｃｍ、
０２； １０ ｓ ｅ ｃｍで導入し、１．７ＲＷのＲ
ＩＥ （Ｖｄ ｃｍ６００Ｖ）方法でＳｉＯ２膜をエツ
チングしたときに、８１基板上に生ずる望ましくないＳ
ｉ欠陥層４を模式的に示したものである。FIG. 1 shows an SiO2 film on a Si substrate 1 using CHF3; 90 sccm using a photoresist pattern as a mask.
02; Introduced at 10 sec cm, R of 1.7 RW
Undesirable S generated on the 81 substrate when SiO2 film is etched by IE (Vd cm600V) method.
This is a schematic diagram of an i-defect layer 4.
３０％オーバーエツチングでエツチングした。Etching was performed with 30% overetching.
このＳ１欠陥層には先述のように、Ｃ，Ｆ４やＣ−Ｆ結
合膜が付着し、その下の層に結晶欠陥を生じている。As described above, C, F4, and C--F bonding films are attached to this S1 defect layer, and crystal defects are generated in the layer below.
この後、同じ反応容器内にＣＦ４；６０ｓｅｃｍ。After this, CF4; 60 sec was added to the same reaction vessel.
○２；４０ｓｅｃｍ、圧力が２０Ｐａになるよう導入し
、高周波電力３００Ｗのグロー放電により第１図のＳｉ
欠陥Ｎ４をエツチングし除去した。○2; 40sec, the pressure was 20Pa, and glow discharge with high frequency power of 300W caused the Si as shown in Figure 1 to be
Defect N4 was etched and removed.
このときのエツチング時間とエツチング深さの関係を第
２図ａに示す。The relationship between etching time and etching depth at this time is shown in FIG. 2a.
また第１図で示した試料を第２図す、 ｃで示したよ
うにＳｉのエッチレートを１００Ａ／ｍｉｎにコントロ
ールし、２ｍ１ｎエツチングしたときのコンタクト抵抗
の変化を第１表りこ示す。The first table shows the change in contact resistance when the sample shown in FIG. 1 is etched at 2 ml by controlling the Si etch rate to 100 A/min as shown in FIG. 2 (c).
（第１表）
従来に較べて抵抗はあきらかに減少し、かつ、ウェット
エツチング以上の効果が得られている。(Table 1) The resistance is clearly reduced compared to the conventional method, and an effect greater than wet etching is obtained.
この原因はＣ−Ｆ重合膜、Ｓｉ結晶欠陥層が除去される
と同時に、Ｖｄｃが１００以下の化学反応に支配される
傾向のエツチングなので、再びはＳｉ欠陥層を生じない
ためと考えられる。The reason for this is thought to be that while the C--F polymer film and Si crystal defect layer are removed, the etching tends to be dominated by a chemical reaction with a Vdc of 100 or less, so that no Si defect layer is generated again.
Ｓｉ欠陥層の除去には、上記のほか、Ｃ２Ｆ６゜Ｃ３Ｆ
Ｉｌ、ＣＨＦ３等の弗化炭化水素ガスと０２ガスの混合
ガスを用いても同様な効果が得られる。In addition to the above, C2F6°C3F can be used to remove the Si defect layer.
A similar effect can be obtained by using a mixed gas of a fluorinated hydrocarbon gas such as Il or CHF3 and 02 gas.
実験によってＯ２澗度が４０％以下ではＳｉのエツチン
グ速度が速過ぎて８１欠陥層除去の制御が難しく、また
０２ｓ度が８０％を越えるとＳｉのエツチングが進行し
なくなることが判明している。Experiments have shown that when the O2 degree is less than 40%, the etching rate of Si is too fast and it is difficult to control the removal of the 81 defect layer, and when the O2 degree is more than 80%, the Si etching does not proceed.
従ってＯ２濃度は４０％〜８０％の範囲が望ましい。Therefore, the O2 concentration is preferably in the range of 40% to 80%.
〈発明の効果）
本発明の方法によれば、ドライエツチング後の欠陥層除
去工程において、アンダーカットを生ずることなく欠陥
層をドライエツチングすることが出来る。<Effects of the Invention> According to the method of the present invention, a defective layer can be dry-etched without producing an undercut in the defect layer removal step after dry etching.
第１図は、本発明を説明するためのＳｉ基板の断面図。
第２図ａは、エツチング時間とエツチング深さの関係を
示す図。
第２図すは、高周波電力とＳｉ基板のエッチレートの関
係を示す図。
第２図Ｃは、０゜ガス濃度とＳｉ基板のエッチレートの
関係を示す図。FIG. 1 is a sectional view of a Si substrate for explaining the present invention. FIG. 2a is a diagram showing the relationship between etching time and etching depth. FIG. 2 is a diagram showing the relationship between high frequency power and etch rate of a Si substrate. FIG. 2C is a diagram showing the relationship between the 0° gas concentration and the etch rate of the Si substrate.
Claims (2)
理基板上のＳｉＯ＿２膜ないしＰＳＧ（Ｐのドープされ
たＳｉＯ＿２）膜をドライエッチングする方法において
、該薄膜のエッチング後に、引続き弗化炭化水素のガス
とＯ＿２ガスの混合ガスにより該被処理基板をプラズマ
処理することを特徴とするドライエッチング方法。(1) In a method of dry etching a SiO_2 film or a PSG (P-doped SiO_2) film on a substrate to be processed using a parallel plate type dry etching apparatus, after etching the thin film, A dry etching method characterized in that the substrate to be processed is subjected to plasma processing using a mixed gas of gas and O_2 gas.
％の範囲内にあることを特徴とする特許請求の範囲第１
項記載のドライエッチング方法。(2) The O_2 concentration of the mixed gas is between 40% and 80%.
Claim 1 characterized in that it is within the range of %.
Dry etching method described in section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19678486A JPS6353928A (en) | 1986-08-22 | 1986-08-22 | Dry etching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19678486A JPS6353928A (en) | 1986-08-22 | 1986-08-22 | Dry etching |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6353928A true JPS6353928A (en) | 1988-03-08 |
Family
ID=16363578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19678486A Pending JPS6353928A (en) | 1986-08-22 | 1986-08-22 | Dry etching |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6353928A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629302A (en) * | 1990-09-04 | 1994-02-04 | Samsung Electron Co Ltd | Manufacture of polysilicon-emitter bipolar transistor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57114235A (en) * | 1981-01-08 | 1982-07-16 | Toshiba Corp | Cleaning of semiconductor substrate |
-
1986
- 1986-08-22 JP JP19678486A patent/JPS6353928A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57114235A (en) * | 1981-01-08 | 1982-07-16 | Toshiba Corp | Cleaning of semiconductor substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629302A (en) * | 1990-09-04 | 1994-02-04 | Samsung Electron Co Ltd | Manufacture of polysilicon-emitter bipolar transistor |
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