JPS6343560Y2 - - Google Patents
Info
- Publication number
- JPS6343560Y2 JPS6343560Y2 JP18311782U JP18311782U JPS6343560Y2 JP S6343560 Y2 JPS6343560 Y2 JP S6343560Y2 JP 18311782 U JP18311782 U JP 18311782U JP 18311782 U JP18311782 U JP 18311782U JP S6343560 Y2 JPS6343560 Y2 JP S6343560Y2
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- clock
- bus
- watchdog timer
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000002159 abnormal effect Effects 0.000 claims description 5
- 238000012806 monitoring device Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 description 6
- 230000005856 abnormality Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Landscapes
- Measurement Of Unknown Time Intervals (AREA)
- Debugging And Monitoring (AREA)
Description
【考案の詳細な説明】
本考案はウオツチドツグタイマによりCPUの
異常を検出するCPU監視装置に関する。[Detailed Description of the Invention] The present invention relates to a CPU monitoring device that detects CPU abnormalities using a watchdog timer.
この種の従来のウオツチドツグタイマは、第１
図Ａ又はＢに示す方式のものがある。同図Ａに示
す方式はバス１上のメモリフエツチ信号でウオツ
チドツグタイマ２の計時リセツトをすることで、
タイマ２の設定時間内のメモリフエツチ信号検出
でCPU３を正常と判定し、設定時間を越えるま
でメモリフエツチ信号がないときにCPU３を異
常と判定する。この方式では、DMAによつてメ
モリ４と補助記憶装置等の入出力装置５間のデー
タ転送中にはバス１上に繰返しメモリフエツチ信
号が存在するためその期間にはCPU３が異常に
なつても検出できない。 This type of conventional watchdog timer
There are methods shown in Figures A and B. The method shown in Figure A resets the watchdog timer 2 using the memory fetch signal on the bus 1.
The CPU 3 is determined to be normal when the memory fetch signal is detected within the set time of the timer 2, and the CPU 3 is determined to be abnormal when there is no memory fetch signal until the set time is exceeded. In this method, a memory fetch signal is repeatedly present on the bus 1 during data transfer between the memory 4 and an input/output device 5 such as an auxiliary storage device by DMA, so even if the CPU 3 becomes abnormal during that period, it is detected. Can not.
第１図Ｂに示す方式はウオツチドツグタイマ２
に設定する時間内にCPU３から計時リセツト信
号を与えるようプログラムを構成しておき、設定
時間内にリセツト信号が与えられないことで
CPU３の異常と判定するソフトウエアアクセス
方式としている。この方式ではソフトウエアアク
セスを頻繁に行なうとCPU３の負荷が増大し、
リアルタイムシステムにおいてはソフトウエアア
クセスの頻度を下げざるを得ないため最大30秒間
もCPUの停止を検出できないこともある。 The method shown in Figure 1B is for watchdog timer 2.
The program is configured so that the clock reset signal is given from CPU3 within the time set in .If the reset signal is not given within the set time
A software access method is used to determine that CPU3 is abnormal. In this method, frequent software access increases the load on CPU3.
In real-time systems, it is necessary to reduce the frequency of software access, so it may not be possible to detect a CPU stoppage for up to 30 seconds.
本考案は時計から一定周期でバス占有の割込み
を起し、CPUからのバス占有許可信号をウオツ
チドツグタイマのリセツト信号とすることによ
り、従来の問題点を解消したCPU監視装置を提
供することを目的とする。 The present invention provides a CPU monitoring device that solves the conventional problems by generating bus occupancy interrupts from the clock at regular intervals and using the bus occupancy permission signal from the CPU as the watchdog timer reset signal. The purpose is to
第２図は本考案の一実施例を示す構成図であ
る。バス１に結合される内部時計６は一定周期で
CPU３にバス占有リクエスト信号を発生し、
CPU３はバス占有リクエスト信号に対して優先
順位判定装置３Ａが時計６の優先順位を判定し、
他の装置がバス占有リクエスト信号発生又はバス
占有状態にないときに時計６に対してバス占有許
可信号を与える。ウオツチドツグタイマ２は時計
６に与えられるバス占有許可信号を計時のリセツ
トとして検出してCPU３が正常に動作している
と判定する。 FIG. 2 is a block diagram showing an embodiment of the present invention. The internal clock 6 connected to the bus 1 has a constant cycle.
Generates a bus occupancy request signal to CPU3,
In the CPU 3, the priority determination device 3A determines the priority of the clock 6 in response to the bus occupancy request signal,
A bus occupancy permission signal is given to the clock 6 when no other device generates a bus occupancy request signal or is in a bus occupancy state. The watchdog timer 2 detects the bus occupancy permission signal given to the clock 6 as a timing reset and determines that the CPU 3 is operating normally.
こうした構成により、CPU３が停止すると優
先順位判定装置３Ａも停止するため、時計６から
のバス占有リクエスト信号に対してバス占有許可
信号が発生されないときにはCPU３の異常又は
他の優先順位の高い装置によるバス占有状態にあ
り、このバス占有状態は比較的短い時間内に解除
されることから時計６からの複数回のバス占有リ
クエストにバス占有許可信号が発生されないこと
を検出すればCPU３の異常と判定することがで
きる。 With this configuration, when the CPU 3 stops, the priority determination device 3A also stops, so if a bus occupancy permission signal is not generated in response to a bus occupancy request signal from the clock 6, it is due to an abnormality in the CPU 3 or because the bus is being used by another high priority device. Since the bus occupancy state is released within a relatively short time, if it is detected that no bus occupancy permission signal is generated in response to multiple bus occupancy requests from the clock 6, it is determined that the CPU 3 is abnormal. be able to.
例えば、メモリ４と入出力装置５間にDMAが
実行されているとき、時計６からのバス占有リク
エストに対してCPU３の優先順位判定装置３Ａ
はDMA中のためバス占有許可信号を発生しない
が、DMAは１ワード、１フレームの単位データ
の転送終了から次の単位データの転送開始までに
空き時間があり、この間に時計６からのバス占有
リクエスト信号にはバス占有許可信号の発生があ
つてウオツチドツグタイマ２によるCPU３の正
常，異常判定ができ、本考案では最大でも20ms
でCPUの動作判定が可能となる。 For example, when DMA is executed between the memory 4 and the input/output device 5, the CPU 3's priority determination device 3A responds to a bus occupation request from the clock 6.
does not generate a bus occupancy permission signal because it is in DMA, but DMA has an idle time between the end of transfer of one word, one frame of unit data and the start of transfer of the next unit of data, and during this time the bus occupancy permission signal from clock 6 is generated. The request signal includes the generation of a bus occupancy permission signal, which allows the watchdog timer 2 to determine whether the CPU 3 is normal or not.
It becomes possible to judge the operation of the CPU.
なお、時計６からのバス占有リクエスト信号発
生周期を短かくする頻度の高いリクエスト信号発
生にもCPU３の負荷が増えることは少ない。即
ち、従来のソフトウエアによるCPUのアクセス
に比べて、本考案のように時計６とCPU３の信
号授受は極めて短時間内に処理される。 Note that the load on the CPU 3 is unlikely to increase even when a request signal is generated frequently, which shortens the cycle of bus occupancy request signal generation from the clock 6. That is, compared to the CPU access by conventional software, the signal transmission and reception between the clock 6 and the CPU 3 is processed in an extremely short time according to the present invention.
以上のとおり、本考案によれば、ウオツチドツ
グタイマによるCPUの異常から検出までの時間
を大幅に短縮し、CPUの負担も軽減できる効果
がある。また、本考案では時計の割込みによる監
視のため、CPUの監視に加えて内部時計の異常
も検出できる効果がある。 As described above, the present invention has the effect of significantly shortening the time taken by the watchdog timer to detect an abnormality in the CPU and reducing the burden on the CPU. Furthermore, since the present invention uses clock interrupts for monitoring, it is effective in detecting abnormalities in the internal clock in addition to monitoring the CPU.
第１図は従来のウオツチドツグタイマによる
CPU監視装置を説明するための図、第２図は本
考案の一実施例を示す図である。
１……システムバス、２……ウオツチドツグタ
イマ、３……CPU、４……メモリ、５……入出
力装置、６……内部時計、３Ａ……優先順位判定
装置。
Figure 1 shows a conventional watchdog timer.
FIG. 2, which is a diagram for explaining the CPU monitoring device, is a diagram showing an embodiment of the present invention. 1... System bus, 2... Watchdog timer, 3... CPU, 4... Memory, 5... Input/output device, 6... Internal clock, 3A... Priority determining device.
Claims (1)
グタイマ、内部時計がバス結合されるコンピユー
タにおいて、上記時計はCPUに対して一定周期
でバス占有リクエスト信号を発生し、上記ウオツ
チドツグタイマはCPUから時計に与えるバス占
有許可信号を検出し、この信号が該タイマに設定
する時間内に検出されないときにCPUの異常と
判定することを特徴とするウオツチドツグタイマ
によるCPU監視装置。 In a computer in which the CPU, memory, input/output device, watchdog timer, and internal clock are connected to a bus, the clock generates a bus occupancy request signal to the CPU at regular intervals, and the watchdog timer 1. A CPU monitoring device using a watchdog timer, which detects a bus occupancy permission signal given to a clock from a clock, and determines that a CPU is abnormal when this signal is not detected within a time set in the timer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18311782U JPS5988749U (en) | 1982-12-02 | 1982-12-02 | CPU monitoring device using watchdog timer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18311782U JPS5988749U (en) | 1982-12-02 | 1982-12-02 | CPU monitoring device using watchdog timer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5988749U JPS5988749U (en) | 1984-06-15 |
| JPS6343560Y2 true JPS6343560Y2 (en) | 1988-11-14 |
Family
ID=30396395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18311782U Granted JPS5988749U (en) | 1982-12-02 | 1982-12-02 | CPU monitoring device using watchdog timer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5988749U (en) |
-
1982
- 1982-12-02 JP JP18311782U patent/JPS5988749U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5988749U (en) | 1984-06-15 |
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