JPS6341019A - Ion implatation method - Google Patents
Ion implatation methodInfo
- Publication number
- JPS6341019A JPS6341019A JP18551486A JP18551486A JPS6341019A JP S6341019 A JPS6341019 A JP S6341019A JP 18551486 A JP18551486 A JP 18551486A JP 18551486 A JP18551486 A JP 18551486A JP S6341019 A JPS6341019 A JP S6341019A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- pattern
- electrical characteristics
- ion
- vertical axis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 abstract description 15
- 150000002500 ions Chemical class 0.000 abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 238000009826 distribution Methods 0.000 abstract description 6
- 230000002146 bilateral effect Effects 0.000 abstract 1
- 238000002513 implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はイオン注入方法に関し、特に表面に段差部を有
する半導体基板に対するイオン注入方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an ion implantation method, and more particularly to an ion implantation method for a semiconductor substrate having a stepped portion on its surface.
従来の技術
一般に、第３図（ａ）に示すように、シリコンウェハ（
以下ウェハと称づ）１などの半導体基板にそのウェハ面
１ａに対して斜めからイオンビーム２を投射する場合、
ウェハ１は固定された状態でイオン注入されていた。図
はイオンビーム２の投射方向に直交する面に対してウェ
ハ面１ａを所定の角度α、たとえば４゛〜８゛傾けたも
のを示している。Conventional technology In general, as shown in FIG. 3(a), a silicon wafer (
When projecting an ion beam 2 onto a semiconductor substrate such as a wafer (hereinafter referred to as a wafer) 1 from an angle with respect to the wafer surface 1a,
Wafer 1 was implanted with ions in a fixed state. The figure shows the wafer surface 1a tilted at a predetermined angle α, for example 4° to 8°, with respect to a plane perpendicular to the projection direction of the ion beam 2.
発明が解決しようとする問題点
しかるに、ウェハ１の表面にパターン段差部３を有する
場合、イオン注入時にウェハ１を傾けると、第３図（ｂ
）に示すようにパターン段差部３の左右での不純物イオ
ン層４の分布が非対称となるため、この段差部３の左右
の電気的な特性も非対称となる不都合が生じていた。Problems to be Solved by the Invention However, when the surface of the wafer 1 has a pattern step portion 3, if the wafer 1 is tilted during ion implantation, the problem shown in FIG.
), the distribution of the impurity ion layer 4 on the left and right sides of the pattern step portion 3 is asymmetrical, resulting in a disadvantage that the electrical characteristics on the left and right sides of the step portion 3 are also asymmetrical.
本発明はこのような問題点を解決するもので、電気的特
性のパターン依存性を解消できるイオン注入方法を提供
することを目的とするものである。The present invention is intended to solve these problems, and it is an object of the present invention to provide an ion implantation method that can eliminate the pattern dependence of electrical characteristics.
問題点を解決するための手段
この問題点を解決するために本発明は、半導体基板の一
主面をイオンビームの投射方向に直交する面に対して所
定の角度傾斜させ、前記半導体基板を前記一主面を通る
垂直軸を中心に回転させるものである。Means for Solving the Problem In order to solve this problem, the present invention tilts one main surface of the semiconductor substrate at a predetermined angle with respect to a plane perpendicular to the projection direction of the ion beam, and It rotates around a vertical axis passing through one principal surface.
作用
上記溝成により、イオン注入時、半導体基板はイオンビ
ーム投射面を通る垂直軸を中心に回転されることから、
半導体基板表面のパターン段差部の左右に形成される不
純物イオン層の分布は同一となり、パターンの段差によ
る電気的な特性の差はなくなる。Effect: Due to the above-mentioned groove formation, the semiconductor substrate is rotated around the vertical axis passing through the ion beam projection surface during ion implantation.
The impurity ion layers formed on the left and right sides of the pattern step portion on the surface of the semiconductor substrate have the same distribution, and there is no difference in electrical characteristics due to the pattern step portion.
実施例 以下本発明の一実施例を図面にもとづいて説明する。Example An embodiment of the present invention will be described below based on the drawings.
第１図において、不純物イオン注入時に、イオンビーム
１２の投射方向に直交する面に対して所定の角度αだけ
傾斜させたシリコンウェハ１１は、ウェハ面１１ａを通
る垂直軸１５を中心に第１図（ａ）に示すように回転さ
れる。このとき、不純物イオン層１６は第１図（ｂ）に
示すようにパターン段差部１３の左右に対称に形成され
る。In FIG. 1, during impurity ion implantation, the silicon wafer 11 is tilted by a predetermined angle α with respect to a plane perpendicular to the projection direction of the ion beam 12. It is rotated as shown in (a). At this time, the impurity ion layer 16 is formed symmetrically to the left and right of the pattern step portion 13, as shown in FIG. 1(b).
次に第２図を用いて本発明によるＭＯＳトランジスタの
製造工程について説明する。第２図（ａ）に示すように
、公知の方法でシリコンウェハ２１上にＭＯＳトランジ
スタのゲート絶縁膜２７とゲート電極２８を形成する。Next, the manufacturing process of the MOS transistor according to the present invention will be explained using FIG. As shown in FIG. 2(a), a gate insulating film 27 and a gate electrode 28 of a MOS transistor are formed on a silicon wafer 21 by a known method.
その後、このゲート電極２８をマスクにしてイオン注入
により自己整合的にソース、ドレインをシリコンウェハ
２１に形成する。この際、第２図（ｂ）に示すように、
シリコンウェハ２１はイオンビーム２２の投射方向に直
交する面に対して所定の角度α、たとえば４°〜８゛傾
けて配置されるので、不純物イオンがウェハ表面のゲー
ト電極２８に対して左右非対称に注入される。したがっ
て、このままではゲート電極２８の左右に形成される不
純物イオン層２６ａの分布が非対称になるが、シリコン
ウェハ２１を第１図（ａ）に示したようにウェハ面１１
ａを通る！！！直軸１５を中心にして回転させて、第２
図（Ｃ）に示すように、ゲート電極２８に対して正反対
の方向からもイオンビーム２２の注入を行ない、ゲート
電極２８の左右に不純物イオン層２６ｂを形成させる。Thereafter, a source and a drain are formed in the silicon wafer 21 in a self-aligned manner by ion implantation using the gate electrode 28 as a mask. At this time, as shown in Figure 2(b),
Since the silicon wafer 21 is arranged at a predetermined angle α, for example, 4° to 8°, with respect to a plane perpendicular to the projection direction of the ion beam 22, the impurity ions are asymmetrically distributed with respect to the gate electrode 28 on the wafer surface. Injected. Therefore, if left as is, the distribution of the impurity ion layers 26a formed on the left and right sides of the gate electrode 28 will be asymmetrical, but if the silicon wafer 21 is
Pass through a! ! ! Rotate around the vertical axis 15 to
As shown in Figure (C), the ion beam 22 is implanted from the opposite direction to the gate electrode 28 to form impurity ion layers 26b on the left and right sides of the gate electrode 28.
この結果、第２図（ｄ）に示すように、ウェハ表面のゲ
ート電極２８の左右に形成される不純物イオン層２６は
その分布が同一となる。したがってＭＯＳトランジスタ
の電気的なトランジスタ特性はソース、ドレインを逆転
しても同一となる。As a result, as shown in FIG. 2(d), the impurity ion layers 26 formed on the left and right sides of the gate electrode 28 on the wafer surface have the same distribution. Therefore, the electrical characteristics of the MOS transistor remain the same even if the source and drain are reversed.
発明の効果
以上のように本発明によれば、半導体基板をその一主面
を通る垂直軸を中心に回転させてイオンビームを投射す
るようにしたので、半導体基板表面の段差パターンによ
る半導体基板内の不純物イオンの分布の非対称性を解消
でき、たとえばＭＯＳトランジスタのソース、ドレイン
を逆転してもトランジスタの電気的特性の変化が生じな
くなり、電気的特性のパターン依存性がなくなり、安定
化を図ることができる。Effects of the Invention As described above, according to the present invention, since the ion beam is projected by rotating the semiconductor substrate around the vertical axis passing through one main surface thereof, the inside of the semiconductor substrate due to the step pattern on the surface of the semiconductor substrate can be projected. It is possible to eliminate the asymmetry in the distribution of impurity ions, for example, even if the source and drain of a MOS transistor are reversed, the electrical characteristics of the transistor will not change, the pattern dependence of the electrical characteristics will be eliminated, and stability will be achieved. Can be done.
第１図（ａＨｂ）は本発明の一実施例によるイオン注入
方法の原理説明図および表面に段差のあるウェハへの不
純物イオンの注入を説明するための断面図、第２図（ａ
）〜（ｄ）はそれぞれ本発明のイオン注入方法を用いて
ＭＯＳトランジスタの製造工程を説明するための断面図
、第３図（ａＨｂ）は従来例の原理説明図および表面に
段差のあるウェハへの不純物イオンの注入を説明するた
めの断面図である。
１１、２１・・・シリコンウェハ（半導体基板） 、１
１ａ・・・シリコンウェハ面、１２．２２・・・イオン
ビーム、１３・・・パターン段差部、１５・・・シリコ
ン・ウェハ面を通る垂直軸、１６．２６・・・不純物イ
オン層、２７・・・ゲート絶縁膜、２８・・・ゲート電
極。
代理人 森 本 義 弘
第１図
１ｄ。
第３図
４・
第２図FIG. 1 (aHb) is a diagram for explaining the principle of an ion implantation method according to an embodiment of the present invention, a cross-sectional view for explaining the implantation of impurity ions into a wafer with a step on the surface, and FIG.
) to (d) are cross-sectional views for explaining the manufacturing process of a MOS transistor using the ion implantation method of the present invention, respectively, and FIG. FIG. 3 is a cross-sectional view for explaining the implantation of impurity ions. 11, 21... Silicon wafer (semiconductor substrate), 1
1a...Silicon wafer surface, 12.22...Ion beam, 13...Pattern step portion, 15...Vertical axis passing through the silicon wafer surface, 16.26...Impurity ion layer, 27. ...Gate insulating film, 28...Gate electrode. Agent Yoshihiro Morimoto Figure 1 1d. Figure 3 4・ Figure 2
Claims (1)
交する面に対して所定の角度傾斜させ、前記半導体基板
を前記一主面を通る垂直軸を中心に回転させるイオン注
入方法。1. An ion implantation method in which one main surface of a semiconductor substrate is tilted at a predetermined angle with respect to a plane perpendicular to the projection direction of an ion beam, and the semiconductor substrate is rotated about a vertical axis passing through the one main surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18551486A JPS6341019A (en) | 1986-08-07 | 1986-08-07 | Ion implatation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18551486A JPS6341019A (en) | 1986-08-07 | 1986-08-07 | Ion implatation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6341019A true JPS6341019A (en) | 1988-02-22 |
Family
ID=16172115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18551486A Pending JPS6341019A (en) | 1986-08-07 | 1986-08-07 | Ion implatation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6341019A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4921812A (en) * | 1988-02-05 | 1990-05-01 | Yamaha Corporation | Process of fabricating field effect transistor device |
| US5073514A (en) * | 1989-07-18 | 1991-12-17 | Sony Corporation | Method of manufacturing mis semiconductor device |
| US5270226A (en) * | 1989-04-03 | 1993-12-14 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method for LDDFETS using oblique ion implantion technique |
| US5963334A (en) * | 1997-03-07 | 1999-10-05 | Minolta Co., Ltd. | Apparatus and method for measuring color of a measurement object |
-
1986
- 1986-08-07 JP JP18551486A patent/JPS6341019A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4921812A (en) * | 1988-02-05 | 1990-05-01 | Yamaha Corporation | Process of fabricating field effect transistor device |
| US5270226A (en) * | 1989-04-03 | 1993-12-14 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method for LDDFETS using oblique ion implantion technique |
| US5073514A (en) * | 1989-07-18 | 1991-12-17 | Sony Corporation | Method of manufacturing mis semiconductor device |
| US5963334A (en) * | 1997-03-07 | 1999-10-05 | Minolta Co., Ltd. | Apparatus and method for measuring color of a measurement object |
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