JPS60733A - Semiconductor device and manufactur thereof - Google Patents
Semiconductor device and manufactur thereofInfo
- Publication number
- JPS60733A JPS60733A JP10866983A JP10866983A JPS60733A JP S60733 A JPS60733 A JP S60733A JP 10866983 A JP10866983 A JP 10866983A JP 10866983 A JP10866983 A JP 10866983A JP S60733 A JPS60733 A JP S60733A
- Authority
- JP
- Japan
- Prior art keywords
- plane
- ion implantation
- angle
- semiconductor device
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 21
- 239000013078 crystal Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 13
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 20
- 150000002500 ions Chemical class 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract description 18
- 239000000758 substrate Substances 0.000 abstract description 11
- 239000012535 impurity Substances 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 7
- 238000009826 distribution Methods 0.000 abstract description 6
- 230000005465 channeling Effects 0.000 abstract description 5
- 230000001771 impaired effect Effects 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 11
- 238000007796 conventional method Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置およびその製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same.
近年、シリコン(Si)の電す移BdlKの3〜5倍の
値をもつ砒化ガリ9ム(GaAs)を用いて、超高速集
積回路の開発が進められている。この集積回路(ic)
は一般に半絶縁性GaA s基板上にnおよびn 形S
*層を形成し、該尋竜層上に電界効果トランジスタ、ダ
イオード等の構成菓子を作り、集積化することによ#)
製作される。前記nおよびn+形導電層はGaAs中に
おいてn形不純物となシうるイオンを半絶縁性Ga人S
基板に注入した後アニールすること、すなわちイオン注
入によシ形成される。In recent years, the development of ultrahigh-speed integrated circuits has been progressing using gallium arsenide (GaAs), which has a current transfer value 3 to 5 times higher than that of silicon (Si), BdlK. This integrated circuit (ic)
are generally n- and n-type S on semi-insulating GaAs substrates.
*By forming a layer, and making and integrating field effect transistors, diodes, etc. on the layer)
Manufactured. The n- and n+-type conductive layers conduct semi-insulating Ga layers to conduct ions that can become n-type impurities in GaAs.
It is formed by implanting it into the substrate and then annealing it, that is, by ion implantation.
前記半絶縁性GaAs基板は一般にその(100)面が
用いられるが、イオン注入時のチャンネリング効果を防
ぐために、イオンが飛んでくる方向よ!り(100)面
を数度傾け、かつ面チャンネリングを防ぐためにそこで
10数度回転させてイオン注入を行なう。The (100) plane of the semi-insulating GaAs substrate is generally used, but in order to prevent the channeling effect during ion implantation, the direction in which the ions fly is oriented. The ion implantation is performed by tilting the (100) plane by several degrees and rotating it by more than 10 degrees to prevent surface channeling.
しかしながら(100)面を傾けたり必るいは回転させ
る角度によシ、半絶縁性Ga A s基板に注入された
不純物分布が異なるために、例えは電界効果トランジス
タのスレッショルド電圧(VT)が異なり、GaAs1
Cの特性の再現性が損なわれる。However, depending on the angle at which the (100) plane is tilted or rotated, the impurity distribution implanted into the semi-insulating GaAs substrate differs, for example, the threshold voltage (VT) of a field effect transistor differs. GaAs1
The reproducibility of the characteristics of C is impaired.
また従来の方法によるとマスクを用いたイオン注入工程
においてマスクによる影が生じる。第1図は従来のもの
のこのような半導体装置の製造方法のイオン注入工程の
一例の断面図を示し、n形G a A s層3上に形成
されたゲート電極2を榎うマスク材1をマスクとして、
電界効果トランジスタの寄生抵抗の低減のために層形G
aAs Jfn 4の形成を目的としてイオン注入する
際には、例えば(100)面より7度傾けてイオンを注
入するため、マスク材1の片側にはイオンが注入されな
い領域5がマスク材1の他の片側にはマスク材の下にも
多くイオン注入された領域6が形成される。従ってンー
ス電極、ドレイン電極を任意に配置したいGaAs I
Cにおいては、各電極間の宵生抵抗値にほらつきを生
じる。Further, according to the conventional method, a shadow due to the mask occurs in the ion implantation process using a mask. FIG. 1 shows a cross-sectional view of an example of an ion implantation step in a conventional method for manufacturing such a semiconductor device, in which a mask material 1 that covers a gate electrode 2 formed on an n-type GaAs layer 3 is shown. As a mask,
Layered G for reducing parasitic resistance of field effect transistors
When ion implantation is performed for the purpose of forming aAs Jfn 4, the ions are implanted at an angle of 7 degrees from the (100) plane, so there is a region 5 on one side of the mask material 1 where ions are not implanted. On one side of the mask material, a region 6 in which many ions are implanted is formed also under the mask material. Therefore, the GaAs I
In C, fluctuations occur in the resistance value between each electrode.
本発明は従来のもののこのような欠点を除去し、イオン
注入面に不純物イオンが入射する方向を固定することに
よシ、注入された不純物の分布が常に一定になるように
して、GaAs1Cの特性の再現性を計ろうとするもの
でるる。The present invention eliminates these drawbacks of the conventional method and fixes the direction in which impurity ions are incident on the ion-implanted surface so that the distribution of the implanted impurities is always constant, thereby improving the characteristics of GaAs1C. This is something that attempts to measure the reproducibility of.
本第1の発明によると半導体結晶より該半導体結晶の(
100)面より(110)方向に7°±3°ずれて切シ
出した面を注入面とすることを特徴とする半導体装置が
得られる。According to the first invention, the semiconductor crystal (
A semiconductor device is obtained in which a face cut out at a deviation of 7°±3° in the (110) direction from the 100) face is used as an injection face.
また本第2の発明によると半導体結晶よシ該半導体結晶
の(100)面よシ<110>方向に7°±3゜ずれて
切シ出した面にイオン注入する工程を含むことを特徴と
する半導体装置の製造方法が得られる。According to the second aspect of the present invention, the method includes the step of implanting ions into the cut plane of the semiconductor crystal with a deviation of 7°±3° in the <110> direction from the (100) plane of the semiconductor crystal. A method for manufacturing a semiconductor device is obtained.
すなわち、本発明は従来の半絶縁性Ga A s基板の
(100)面をイオン注入装置中で、例えば(110)
方向に7° 傾け、さらに15°回転させる方法にかわ
って、半絶縁性G a A s結晶インゴットから、あ
らかじめ(ioo)面から<110>方向に物本ば7°
#Aいた面が出るようにGaAs基板を切シ出し、核部
をイオン注入面として用いるものである。That is, in the present invention, the (100) plane of a conventional semi-insulating GaAs substrate is implanted in an ion implanter, for example, by (110) plane.
Instead of tilting the semi-insulating GaAs crystal ingot by 7 degrees and rotating it by 15 degrees, the semi-insulating GaAs crystal ingot is tilted by 7 degrees in the <110> direction from the (ioo) plane.
The GaAs substrate is cut out so that the #A surface is exposed, and the core portion is used as the ion implantation surface.
(100)面からの傾きの角度は、イオン注入時にチャ
ンネリング効果が起きない角度でめると共に、イオン注
入前に半絶縁性(jaAs基板の表面損傷を除去するた
めに、硫酸:過酸化水素水:水=3:1:1のエツチン
グ液で一般に半絶縁性GaAs基板表面を10〜30μ
mエツチングする。かかるGaAs基板のエツチングで
は(100)面からの傾きが10度をこえると、エツチ
ング後のQ a A S基板表面の平滑性がエツチング
液温に敏感になり、平滑性が損なわれることが多くなシ
安定したエツチングが出来にくくなる。従って(ioo
)面からの傾きの角度としてはチャンネリング効果のな
くなる3Kから10度の範囲が適当である。The angle of inclination from the (100) plane is determined at an angle that does not cause a channeling effect during ion implantation. Generally, the surface of a semi-insulating GaAs substrate is etched by 10 to 30 μm using an etching solution of water: water = 3:1:1.
m etching. In such etching of a GaAs substrate, if the inclination from the (100) plane exceeds 10 degrees, the smoothness of the surface of the Q A S substrate after etching becomes sensitive to the temperature of the etching solution, and the smoothness is often impaired. It becomes difficult to perform stable etching. Therefore (ioo
) The appropriate angle of inclination from the plane is in the range of 3K to 10 degrees, at which the channeling effect disappears.
本発明は注入した不純物分布が常に一定になるという利
点を有する他に、半纏体喪造装置の製造工程、すなわち
マスク全周いたイオン注入工程において、マスクによる
影を生じないイオン注入が可能になシ、例えはGaA
s I Cの構成素子の特性を均一にする利点を有する
。In addition to having the advantage that the implanted impurity distribution is always constant, the present invention also enables ion implantation that does not cause shadows caused by the mask in the manufacturing process of the semi-embroidered body mortuary device, that is, the ion implantation process that involves the entire circumference of the mask. For example, GaA
This has the advantage of making the characteristics of the constituent elements of the s I C uniform.
第2図は本発明半導体装置の製造方法のイオン注入工程
の一実施例の断面図を示し、第2図においてはn形Ga
As層3上に形成されたゲート電極2を覆うマスク材1
をマスクとしてGaAs基板に垂直方向よシイオン注入
されるため、n 形GaAs層4はマスク材1に接し、
且つマスク材の両側で等しく配置され、各電極間の寄生
抵抗値は等しくなる。この効果はマスク材1を用いずに
ゲート電極2をマスクとしてイオン注入する場合にはよ
り大きくなる。FIG. 2 shows a cross-sectional view of one embodiment of the ion implantation step of the method for manufacturing a semiconductor device of the present invention.
Mask material 1 covering gate electrode 2 formed on As layer 3
Since ions are implanted vertically into the GaAs substrate using the mask as a mask, the n-type GaAs layer 4 is in contact with the mask material 1,
In addition, the electrodes are arranged equally on both sides of the mask material, and the parasitic resistance value between each electrode is equal. This effect becomes greater when ions are implanted using the gate electrode 2 as a mask without using the mask material 1.
尚本発明は、GaAsと同じ結晶構造をもつ化の化合物
半導体においても適用しうる。The present invention can also be applied to a compound semiconductor having the same crystal structure as GaAs.
本発明によると、注入した不純物分布が一定になると共
に、マスクを用いたイオン注入工程において、マスクに
よる影を生じないイオン注入が可能となり、集積回路構
成素子の特性を均一とする効果を有する。According to the present invention, the implanted impurity distribution becomes constant, and in the ion implantation process using a mask, it becomes possible to perform ion implantation without causing shadows caused by the mask, which has the effect of making the characteristics of integrated circuit elements uniform.
第1図は従来の半導体装置の製造方法のイオン注入工程
の一例の断面図、第2図は本発明半導体装置の製造方法
におけるイオン注入工程の一実施例の断面図を示す。
1・・・・・・マスク材、2・・・・・・ゲート電極、
3・・・・・・n形Ga A s層、4・・・・・−n
形G a A s層、5・・・・・・マスク材の影に
71) n 形Q a A 5層でない領域、6・・・
−・・マスク材の下にも形成されたn 形GaA s層
。
代理人 弁理士 内 原 xe、7::’” ・“jl
、34、)
1−lゝノ
第 2 図FIG. 1 is a cross-sectional view of an example of an ion implantation step in a conventional method for manufacturing a semiconductor device, and FIG. 2 is a cross-sectional view of an example of an ion implantation step in a method for manufacturing a semiconductor device of the present invention. 1...Mask material, 2...Gate electrode,
3...n-type GaAs layer, 4...-n
Type G a A s layer, 5... In the shadow of the mask material 71) n Type Q a A 5 non-layer area, 6...
-... n-type GaAs layer also formed under the mask material. Agent Patent Attorney Uchihara xe, 7::'” ・“jl
, 34,) Figure 2 of 1-lゝ
Claims (4)
i(110)方向に7°±3°ずれて切シ出した面を注
入面とすることを特徴とする半導体装置。(1) From a semiconductor crystal, from the (100) plane of the semiconductor crystal, f
A semiconductor device characterized in that a cutout surface shifted by 7°±3° in the i (110) direction is an injection surface.
9 (110)方向に7°±3°ずれて切シ出した面に
イオン注入する工程を含むことを特徴とする半導体装置
の製造方法。(2) The (100) plane of the semiconducting crystal,
9. A method for manufacturing a semiconductor device, comprising the step of implanting ions into a cutout surface shifted by 7°±3° in the (110) direction.
とする特許請求の範囲第(1)項記載の半導体装置。(3) The semiconductor device according to claim (1), wherein the semiconductor crystal is a gallium arsenide crystal.
とする特許請求の範囲第(2)項記載の半導体装置の製
造方法。(4) The method for manufacturing a semiconductor device according to claim (2), wherein the semiconductor crystal is a gallium arsenide crystal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10866983A JPS60733A (en) | 1983-06-17 | 1983-06-17 | Semiconductor device and manufactur thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10866983A JPS60733A (en) | 1983-06-17 | 1983-06-17 | Semiconductor device and manufactur thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60733A true JPS60733A (en) | 1985-01-05 |
Family
ID=14490673
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10866983A Pending JPS60733A (en) | 1983-06-17 | 1983-06-17 | Semiconductor device and manufactur thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60733A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4570765A (en) * | 1982-08-31 | 1986-02-18 | Fuji Jukogyo Kabushiki Kaisha | Gearshift system for an automobile |
EP0195867A2 (en) * | 1985-03-27 | 1986-10-01 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device including an implantation step |
JPS6433924A (en) * | 1987-07-29 | 1989-02-03 | Sony Corp | Semiconductor wafer |
-
1983
- 1983-06-17 JP JP10866983A patent/JPS60733A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4570765A (en) * | 1982-08-31 | 1986-02-18 | Fuji Jukogyo Kabushiki Kaisha | Gearshift system for an automobile |
EP0195867A2 (en) * | 1985-03-27 | 1986-10-01 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device including an implantation step |
US4670968A (en) * | 1985-03-27 | 1987-06-09 | Kabushiki Kaisha Toshiba | Method of implanting uniform concentrations in solids having predetermined angular relationship with the ion-beam |
JPS6433924A (en) * | 1987-07-29 | 1989-02-03 | Sony Corp | Semiconductor wafer |
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