JPS6335155B2 - - Google Patents
Info
- Publication number
- JPS6335155B2 JPS6335155B2 JP9954580A JP9954580A JPS6335155B2 JP S6335155 B2 JPS6335155 B2 JP S6335155B2 JP 9954580 A JP9954580 A JP 9954580A JP 9954580 A JP9954580 A JP 9954580A JP S6335155 B2 JPS6335155 B2 JP S6335155B2
- Authority
- JP
- Japan
- Prior art keywords
- processors
- memory
- processor
- present
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/5455—Multi-processor, parallelism, distributed systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Exchange Systems With Centralized Control (AREA)
Description
【発明の詳細な説明】
本発明は複数プロセツサにより自動交換機の制
御回路を構成する自動交換機の分散制御方式に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a distributed control system for an automatic switching system in which a control circuit of the automatic switching system is configured by a plurality of processors.
従来のこの種の分散制御方式は多数のプロセツ
サ間の情報転送を可能にするために複雑な回路を
必要とし、従つて機器のコストが高くなり、少数
のプロセツサ間の情報転送手段としては不適当で
あつた。 Conventional distributed control systems of this type require complex circuits to enable information transfer between a large number of processors, resulting in high equipment costs and are unsuitable as a means of transferring information between a small number of processors. It was hot.
本発明の目的は上記の欠点を除き、安価でかつ
動作が安定し、しかもプロセツサ間の情報転送の
処理速度が増大する自動交換機の分散制御方式を
提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, provide a distributed control system for automatic switching equipment that is inexpensive, stable in operation, and increases the processing speed of information transfer between processors.
上記の本発明の目的を達成するため、本発明
は、複数のプロセツサ間を先入力先出力メモリを
介して接続し、この先入力先出力メモリを介して
複数のプロセツサ相互の情報転送が可能なように
し、固定記憶メモリ及び一時記憶メモリをそれぞ
れのプロセツサに対応して設け、半固定記憶メモ
リを切替回路を介して複数のプロセツサに共通に
設ける制御回路を備えることを特徴とする。 In order to achieve the above object of the present invention, the present invention connects a plurality of processors via a first-in/first-out memory so that information can be transferred between the plurality of processors via the first-in/first-out memory. The present invention is characterized in that a fixed memory memory and a temporary memory memory are provided corresponding to each processor, and a control circuit is provided in which a semi-fixed memory memory is provided in common to a plurality of processors via a switching circuit.
本発明のように複数のプロセツサ間を先入力先
出力メモリを介して接続し、この先入力先出力メ
モリを介して複数のプロセツサ相互の情報転送を
可能にすることにより、プロセツサ間の情報転送
の回路を簡素化することが可能になり、プロセツ
サ間の情報転送回路を安価にすることができる。
また、情報転送の制御動作が簡素化され処理速度
を増大することが可能になり、従つて情報転送の
速度を増大させることが可能になる。このように
情報転送回路が簡素化されることにより、小容量
の自動交換機の制御回路にも経済的に適用可能な
自動交換機の分散制御方式が得られる。 As in the present invention, by connecting a plurality of processors via a first-in first-out memory and making it possible to transfer information between the plurality of processors via the first-in first-out memory, a circuit for transferring information between processors is created. This makes it possible to simplify information transfer circuits between processors and reduce the cost of information transfer circuits between processors.
Furthermore, the control operation for information transfer is simplified, making it possible to increase the processing speed, and therefore making it possible to increase the speed of information transfer. By simplifying the information transfer circuit in this way, it is possible to obtain a distributed control system for automatic exchanges that can be economically applied to control circuits of small-capacity automatic exchanges.
以下本発明の実施例を図面を参照して詳細に説
明する。第１図は本発明の実施例のブロツク図で
ある。第１図において、１１，１２は通話路機
器、２１，２２はプロセツサである。通話路機器
１１はプロセツサ２１により制御される通話路機
器で、通話路機器１２はプロセツサ２２により制
御される通話路機器である。プロセツサ２１には
制御プログラムを記憶する固定記憶メモリ３１及
び処理過程において必要に応じて一時的な情報を
記憶する一時記憶メモリ４１が接続される。プロ
セツサ２２には制御プログラムを記憶する固定記
憶メモリ３２及び処理過程において必要に応じて
一時的な情報を記憶する一時記憶メモリ４２が接
続される。プロセツサ２１とプロセツサ２２との
間にはインタフエイス回路７が設けられ、このイ
ンタフエイス回路７を介してプロセツサ２１とプ
ロセツサ２２との間の情報転送を行なう。半固定
メモリ６は交換機の動作上必要となるシステムデ
ータ、局データを記憶する半固定メモリで、プロ
セツサ２１及びプロセツサ２２に切替回路５を介
して接続される。切替回路５は半固定メモリ６を
プロセツサ２１及びプロセツサ２２のいずれに接
続するかを決定する回路である。プロセツサ２１
が内部処理の過程において、プロセツサ２２の管
理下にある一時記憶メモリ４２のデータを識別す
る場合、一時記憶メモリ４２のデータを読出す場
合、一時記憶メモリ４２にデータを書込む場合、
通話路機器１２の制御する場合等はプロセツサ２
１からインタフエイス回路７を介してプロセツサ
２２にデータの転送を行なう。また、プロセツサ
２２からプロセツサ２１にも同様な目的でインタ
フエイス回路７を介してデータの転送を行なう。 Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the invention. In FIG. 1, 11 and 12 are communication path devices, and 21 and 22 are processors. The channel device 11 is a channel device controlled by a processor 21, and the channel device 12 is a channel device controlled by a processor 22. Connected to the processor 21 are a fixed memory 31 for storing control programs and a temporary memory 41 for storing temporary information as necessary during processing. Connected to the processor 22 are a fixed memory 32 for storing control programs and a temporary memory 42 for storing temporary information as needed during processing. An interface circuit 7 is provided between the processors 21 and 22, and information is transferred between the processors 21 and 22 via the interface circuit 7. The semi-permanent memory 6 is a semi-permanent memory that stores system data and station data necessary for the operation of the exchange, and is connected to the processors 21 and 22 via the switching circuit 5. The switching circuit 5 is a circuit that determines which of the processors 21 and 22 the semi-permanent memory 6 is connected to. Processor 21
In the process of internal processing, when identifying data in the temporary memory 42 under the control of the processor 22, when reading data from the temporary memory 42, when writing data to the temporary memory 42,
When controlling the communication path equipment 12, the processor 2
Data is transferred from the processor 1 to the processor 22 via the interface circuit 7. Further, data is transferred from the processor 22 to the processor 21 via the interface circuit 7 for the same purpose.
以上の本発明の実施例の説明は、プロセツサが
２つの場合についての説明であつたが、プロセツ
サが３つ以上の場合にも本発明を実施できること
は明らかである。また、本発明の実施例において
は、プログラムを記憶するメモリは固定記憶メモ
リであつたが、この固定記憶メモリの代りに半固
定記憶メモリを使用しても、或いは一時記憶メモ
リを使用しても交換制御動作は可能であり、本発
明を実施することは可能である。 Although the above embodiments of the present invention have been described for the case where there are two processors, it is clear that the present invention can also be practiced when there are three or more processors. Furthermore, in the embodiments of the present invention, the memory for storing programs is fixed memory, but semi-fixed memory or temporary memory may be used instead of fixed memory. Exchange control operations are possible and it is possible to implement the invention.
以上説明したように本発明は、自動交換機の制
御回路を簡素化しその処理速度を増大させ、動作
が安定したしかも経済的な自動交換機を提供する
ことを可能にする効果がある。 As explained above, the present invention has the effect of simplifying the control circuit of an automatic exchange, increasing its processing speed, and making it possible to provide an automatic exchange that is stable in operation and is economical.
第１図は本発明の実施例のブロツク図である。
１１，１２……通話路機器、２１，２２……プ
ロセツサ、３１，３２……固定記憶メモリ、４
１，４２……一時記憶メモリ、５……切替回路、
６……半固定記憶メモリ、７……インタフエイス
回路。
FIG. 1 is a block diagram of an embodiment of the invention. 11, 12...Call path equipment, 21, 22...Processor, 31, 32...Fixed storage memory, 4
1, 42...Temporary storage memory, 5...Switching circuit,
6...Semi-permanent storage memory, 7...Interface circuit.
Claims (1)
であつて先入力先出力メモリを介して相互に情報
転送をする相対向する２つのプロセツサと、これ
ら２つのプロセツサのそれぞれに対応して設けら
れるプログラム記憶メモリ及び一時記憶メモリ
と、切替回路を介してこれら２つのプロセツサに
共通に設けられる半固定メモリとを備えることを
特徴とする自動交換機の分散制御方式。1. Two processors among a plurality of processors that mutually transfer information via a first-in first-out memory, and a program storage memory provided corresponding to each of these two processors. 1. A distributed control system for an automatic switching system, comprising: a temporary storage memory; and a semi-permanent memory provided in common to these two processors via a switching circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9954580A JPS5724189A (en) | 1980-07-21 | 1980-07-21 | Scatter control system for automatic exchanger |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9954580A JPS5724189A (en) | 1980-07-21 | 1980-07-21 | Scatter control system for automatic exchanger |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5724189A JPS5724189A (en) | 1982-02-08 |
| JPS6335155B2 true JPS6335155B2 (en) | 1988-07-13 |
Family
ID=14250145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9954580A Granted JPS5724189A (en) | 1980-07-21 | 1980-07-21 | Scatter control system for automatic exchanger |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5724189A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5949855A (en) * | 1982-09-14 | 1984-03-22 | 太平洋セメント株式会社 | Shaft type mill |
| JPS62174681U (en) * | 1986-04-28 | 1987-11-06 | ||
| JPS62174682U (en) * | 1986-04-28 | 1987-11-06 | ||
| KR100414923B1 (en) * | 1995-12-30 | 2004-04-03 | 삼성전자주식회사 | Apparatus for communication matching between processors, and method therefor |
| WO2007097042A1 (en) | 2006-02-24 | 2007-08-30 | Taiheiyo Cement Corporation | Centrifugal air classifier |
-
1980
- 1980-07-21 JP JP9954580A patent/JPS5724189A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5724189A (en) | 1982-02-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS54129942A (en) | Direct transfer system between sub-systems | |
| JPS6335155B2 (en) | ||
| JPS6053901B2 (en) | Inter-processor information transfer method | |
| JPS5768948A (en) | Data transfer system between central processors | |
| JPS5640391A (en) | Multiprocessor control system | |
| JPS5219008A (en) | Memory switch system | |
| JPS56137754A (en) | Control system of information transferring | |
| JPS57103530A (en) | Channel controlling system | |
| JPS58206296A (en) | Common memory controlling system | |
| JP2674003B2 (en) | Time division switch control memory copy method | |
| KR960008424B1 (en) | Broadcasting loading method for file reference counter | |
| JPS59125193A (en) | Conflict preventing system | |
| JPS5759220A (en) | Data transfer system | |
| JPS57207943A (en) | Input-output controller equipped with built-in buffer memory | |
| JPS57136241A (en) | Data transfer system | |
| JPS55153021A (en) | Data transfer system of multiprocessor system | |
| JPS6217879Y2 (en) | ||
| JPS5622157A (en) | Process system multiplexing system | |
| JPS57101929A (en) | Common memory access system from data channel device | |
| JPS60153556A (en) | Common memory device | |
| JPS56157521A (en) | Command chaining control system | |
| JPS56107689A (en) | Connection control system of automatic exchange | |
| JPS55127790A (en) | Duplex system of exchange processing unit | |
| JPS5787649A (en) | Telegraphic message storage and exchange system | |
| JPS59144296A (en) | Office data control system of electronic exchange |