JPS5768948A - Data transfer system between central processors - Google Patents
Data transfer system between central processorsInfo
- Publication number
- JPS5768948A JPS5768948A JP55144893A JP14489380A JPS5768948A JP S5768948 A JPS5768948 A JP S5768948A JP 55144893 A JP55144893 A JP 55144893A JP 14489380 A JP14489380 A JP 14489380A JP S5768948 A JPS5768948 A JP S5768948A
- Authority
- JP
- Japan
- Prior art keywords
- data transfer
- transmission
- ccua
- lines
- exchange processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Small-Scale Networks (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To make an effective use of a device, by making data transfer between CPUs, by using a part of vacant state of a channel control memory for transmission, in exchange processing between lines. CONSTITUTION:Communication controllers CCUa, CCUb respectively control lines La, Lb in timne division, and exchange processing can be made for the CCUa with control information from the CPUa and for the CCUa with the control information from the CPUb. A channel control memory CCM for transmission and reception is used for the exchange processing between lines La, Lb and CPUa, CPUb, and write-in/readout for reception control information ICW and transmission control information OCW are made. For the exchange processing between the lines La, Lb located respectively to the CCUa, CCUb, the channel control memory CCM for the transmission is vacant, then when data transfer is made from the CPUa to the CPUb, the channel control memory CCM for transmission in vacant state is used. Thus, the communication controller can be used effectively without provision of the device exclusively used for the data transfer between CPUs, allowing to make data transfer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55144893A JPS5768948A (en) | 1980-10-16 | 1980-10-16 | Data transfer system between central processors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55144893A JPS5768948A (en) | 1980-10-16 | 1980-10-16 | Data transfer system between central processors |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5768948A true JPS5768948A (en) | 1982-04-27 |
Family
ID=15372787
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55144893A Pending JPS5768948A (en) | 1980-10-16 | 1980-10-16 | Data transfer system between central processors |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5768948A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01183940A (en) * | 1988-01-18 | 1989-07-21 | Nec Corp | Data concentrating distributing system |
-
1980
- 1980-10-16 JP JP55144893A patent/JPS5768948A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01183940A (en) * | 1988-01-18 | 1989-07-21 | Nec Corp | Data concentrating distributing system |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS57197642A (en) | Information transmitting system | |
JPS5768948A (en) | Data transfer system between central processors | |
JPS54152406A (en) | Information transfer control system of time-division multiple network | |
JPS5723166A (en) | Parallel data processing system driven by tree structure data | |
JPS6335155B2 (en) | ||
JPS578828A (en) | Communication system between computer systems | |
JPS6478359A (en) | Dual microprocessor control system | |
JPS5730012A (en) | Program loading system | |
JPS57136241A (en) | Data transfer system | |
JPS54159104A (en) | Communication control unit | |
JPS56135261A (en) | Interprocessor information transfer system | |
GB1482659A (en) | Device for selective exchange of information | |
JPS5464436A (en) | Communication control system | |
JPS56135260A (en) | Inter-processor information transfer system | |
JPS5339022A (en) | Information process unit | |
JPS5643850A (en) | Intermultiplexer communication control system | |
JPS52144934A (en) | Sending out information intercepting unit | |
JPS5798062A (en) | Communication system between processors | |
JPS5787649A (en) | Telegraphic message storage and exchange system | |
JPS57207943A (en) | Input-output controller equipped with built-in buffer memory | |
JPS53130907A (en) | Electronic exchanger system using decentralized control | |
JPS5336110A (en) | Data transfer system | |
JPS5783838A (en) | Controller for communication between processors | |
JPS5487140A (en) | Data transfer control system | |
JPS57133735A (en) | Data transmission device |