JPS6334940A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6334940A JPS6334940A JP61179678A JP17967886A JPS6334940A JP S6334940 A JPS6334940 A JP S6334940A JP 61179678 A JP61179678 A JP 61179678A JP 17967886 A JP17967886 A JP 17967886A JP S6334940 A JPS6334940 A JP S6334940A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- electrode
- electrodes
- bonding jig
- thermocompression bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 13
- 230000006378 damage Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000002184 metal Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はバンプ型半導体装置の組立方法に関し、特に半
導体基板外部引き出し電極としての金属バンプを極とリ
ードフレームと称する外部電極とを熱圧着して組立てる
製造方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for assembling a bump-type semiconductor device, and in particular, a method for assembling a bump-type semiconductor device, in particular, a method for bonding metal bumps as external lead electrodes of a semiconductor substrate to external electrodes called lead frames by thermocompression. The present invention relates to a manufacturing method for assembling.
従来、バンプ型半導体装置における金属バンプ電極と外
部！極との組立方法は半導体基板周辺に配置された多数
の金属バンプ電極とこれと対をなす多数の外部電極とを
位置合せの後、一度の熱圧着にて同時に接続して組立て
られていた。最近では半導体素子の大型化に伴なって、
同時接続する電極数も１００〜２００という例がある。Conventionally, metal bump electrodes and external parts in bump-type semiconductor devices! The method for assembling the electrodes was to align a large number of metal bump electrodes arranged around the semiconductor substrate and a large number of paired external electrodes, and then connect them simultaneously in a single thermocompression bonding process. Recently, as semiconductor devices have become larger,
There are examples in which the number of electrodes connected simultaneously is 100 to 200.
上記のようなバンプ型半導体装置のバンプ電極と外部電
極との接続方法について第３図を用いて説明する。同図
（ａ）は平面図、同図（ｂ）は平面図Ａ −Ａ’での断
面図である。同図において３１は熱拡散層を含むシリコ
ン基板、３２は熱酸化膜および窒化膜等より成る絶縁膜
である。内部金属配線は省略した。半導体素子周辺には
引き出しＭ極としての多数のバンプ電極３３が配置され
ている。A method of connecting the bump electrodes and external electrodes of the bump-type semiconductor device as described above will be explained with reference to FIG. FIG. 5(a) is a plan view, and FIG. 2(b) is a sectional view taken along the plane view A-A'. In the figure, 31 is a silicon substrate including a thermal diffusion layer, and 32 is an insulating film made of a thermal oxide film, a nitride film, or the like. Internal metal wiring has been omitted. A large number of bump electrodes 33 as lead-out M poles are arranged around the semiconductor element.
これらのバンプ電極３３とこれらと対をなす外部電極３
４とがそれぞれ位置合せされて後、熱と荷重を負荷され
た熱圧着治具３５による一度の熱圧着によって同時に接
続される。These bump electrodes 33 and the external electrodes 3 paired with these bump electrodes 33
4 are aligned, and then they are simultaneously connected by one-time thermocompression bonding using a thermocompression bonding jig 35 loaded with heat and load.
上述した従来の製造方法では以下のような欠点を生ずる
。すなわちバンプ電極と外部電極との接続時に印加する
熱と圧力は強大であシ、この時ストレスはバンプ電極を
含めた半導体素子の絶縁膜およびシリコン基板にまで加
わる。他方、半導体装置は年々大型化されておシ数百に
のぼる接続を一度で同時に行なうことになシ、かつ−電
極（１接続点）当りの接続に必要な印加荷重は同じであ
ることから大型化と共に熱圧着治具に必要な荷重は接続
数に比例して大きくなってきている。したがって大型化
に伴なう熱圧着時の荷重の増大によって以下の欠点が顕
著化している。すなわち外部電極の製造上の′Ｎ１度（
特に厚さのバラツキ）および熱圧着治具や接続装置の精
度（特に傾き又は平行度）などの不備から接続時に数例
のバンプ１啄にのみ瞬間的に荷重が集中して強大なスト
レスを受けてバング１極下方の絶縁膜やシリコン基板に
破壊（クラック）を生じ、シリコン基板またＦｉ絶縁膜
とバンブ７極界面での剥′ａ（ハガレ）による接続強度
の低下や半導体素子そのものを破壊するに至る。そして
印加力が大きい（大型化される）程顕著化して、その信
頼度を著しく低下させている。The conventional manufacturing method described above has the following drawbacks. That is, the heat and pressure applied when connecting the bump electrode and the external electrode are intense, and at this time stress is applied to the insulating film of the semiconductor element including the bump electrode and the silicon substrate. On the other hand, semiconductor devices are becoming larger year by year, requiring hundreds of connections to be made at the same time, and the applied load required for each connection per electrode (one connection point) is the same. As the number of connections increases, the load required for thermocompression jigs increases in proportion to the number of connections. Therefore, due to the increase in load during thermocompression bonding as the size increases, the following drawbacks have become more prominent. That is, 'N1 degrees (
Due to deficiencies such as (particularly variations in thickness) and accuracy (particularly inclination or parallelism) of the thermocompression bonding jig and connecting device, the load is momentarily concentrated on just a few bumps during connection, resulting in enormous stress. Destruction (cracks) occur in the insulating film and silicon substrate below the bump 1 pole, and peeling occurs at the interface between the silicon substrate or the Fi insulating film and the bump 7 pole, reducing the connection strength and destroying the semiconductor element itself. leading to. The larger the applied force (the larger the size), the more pronounced the problem becomes, significantly lowering its reliability.
上述した従来の製造方法によればバンプ電極と外部電極
の接続を一度の熱圧着で同時に行なうがゆえに、特に素
子の大型化に伴なう接続数の増加＝熱圧着治具への印加
荷重の増加による前述した接続強度の低下や素子の破壊
（クラック）を生ずる問題があり１バンプ電極および外
部電極の特に厚さ方向の精度向上や熱圧着治具（装置を
含む）の特に平行度（傾き）に対する精度向上の対策は
大型化と共に困難となっている。これに対し本発明は印
加荷重の分散、すなわち分割化して接続することによっ
て、素子の大型化＝接続数の増加による熱圧着治具への
印加荷重の増加を排除して接続強度を維持し、素子の破
壊（クラック）を防止する。According to the conventional manufacturing method described above, the bump electrodes and external electrodes are connected at the same time in one thermocompression bonding process. Therefore, as the size of the device increases, the number of connections increases, which increases the load applied to the thermocompression jig. There is a problem with the above-mentioned reduction in connection strength and element destruction (cracks) due to increase in the number of bumps, and it is important to improve the accuracy of the bump electrodes and external electrodes, especially in the thickness direction, and to improve the parallelism (inclination) of the thermocompression bonding jig (including equipment). ) measures to improve accuracy are becoming more difficult as the size increases. In contrast, the present invention maintains connection strength by dispersing the applied load, that is, by dividing it into parts and connecting them, thereby eliminating the increase in the applied load to the thermocompression bonding jig due to an increase in the size of the element = increase in the number of connections, and maintaining the connection strength. Prevents element destruction (cracks).
本発明の製造方法は、ＩＣチップを搭載した基板に配設
された複数個のバンプ１極と前記バンプ電極の各々と一
対一に対応する複数個の外部電極とを接続する半導体装
置の製造方法において、 ｆｆ＋１記複数個のバンプ電
極と％ｔｉ記複数個の外部電極との接続を複数回に分割
して熱圧着する熱圧着治具を具備して実現される。The manufacturing method of the present invention is a method of manufacturing a semiconductor device in which one pole of a plurality of bumps arranged on a substrate on which an IC chip is mounted is connected to a plurality of external electrodes in one-to-one correspondence with each of the bump electrodes. In this embodiment, a thermocompression bonding jig is provided to divide and thermocompress the connection between the ff+1 plurality of bump electrodes and the %ti plurality of external electrodes in a plurality of times.
次に、本発明の製造方法について図面を参照して説明す
る。Next, the manufacturing method of the present invention will be explained with reference to the drawings.
第１図は本発明の第一の実施例であシ、同図（ａ）は平
面図、同図（ｂ）は平面図Ａ −Ａ／での縦断面図であ
る。同図において１１は熱拡散層を含むシリコン基板、
１２は熱酸化膜および窒化膜等より成る絶縁膜であシ、
内部金属配線は省略した。FIG. 1 shows a first embodiment of the present invention, in which FIG. 1(a) is a plan view and FIG. 1(b) is a longitudinal sectional view taken along the plane A-A/. In the figure, 11 is a silicon substrate including a heat diffusion layer;
12 is an insulating film made of a thermal oxide film, a nitride film, etc.;
Internal metal wiring has been omitted.
半導体素子周辺には引き出し電極としての多数のバンプ
電極１３が配置されている。このバンプ電極１３と対を
なす外部電極１４が上記のバンプ電極１３と位置合せさ
れて後、熱圧着治具１５にて半導体素子の一辺のバンプ
１極１３と該当する外部電極１４とを接続する。その後
熱圧着治具の位置と向きを変えて半導体素子の各辺に有
るバンプ電極１３と外部電極１４とを順次接続する。本
実施例では熱圧着治具１５は４個所の接続を同時に行な
うので、４回の処理で全ての接続を完了する。A large number of bump electrodes 13 as lead electrodes are arranged around the semiconductor element. After the external electrode 14 that pairs with this bump electrode 13 is aligned with the bump electrode 13 described above, one bump pole 13 on one side of the semiconductor element is connected to the corresponding external electrode 14 using a thermocompression bonding jig 15. . Thereafter, the position and direction of the thermocompression bonding jig are changed to sequentially connect the bump electrodes 13 and external electrodes 14 on each side of the semiconductor element. In this embodiment, the thermocompression bonding jig 15 connects four locations at the same time, so all connections are completed in four processes.
第２図は本発明の第二の実施例であり、同図（ａ）は平
面図、同図（ｂ）は平面図Ａ −Ａ’での縦断面図であ
る。同図において２１け熱拡散層を含むシリコン基板、
２２け絶縁膜であシ、通常の内部金属配線は省略した。FIG. 2 shows a second embodiment of the present invention, in which FIG. 2(a) is a plan view and FIG. 2(b) is a longitudinal cross-sectional view taken along the plane view A-A'. In the figure, a silicon substrate including 21 heat diffusion layers,
A 22-layer insulating film is used, and normal internal metal wiring is omitted.
半導体素子の周辺には、バンプ電極２３が配置されてい
る。このバンプ電極２３上にこれと対をなす外部電極２
４が位置合せされて後、熱圧着治具２５にて半導体素子
のバンプ電極で左右対称な位置関係にある部分（第２図
（ａ）の左上と右下部分）のバンプ電極と外部Ｗ、Ｍと
を同時に接続する。その後熱圧着治具を９０’回転させ
、残りの対称位置関係（同図（ａ）の左下と右上部分）
のバンプ電極と外部電極とを接続する。本実施例では２
回の処理で全ての接ｔＰ９を完了する。Bump electrodes 23 are arranged around the semiconductor element. A pair of external electrodes 2 are placed on this bump electrode 23.
4 are aligned, the thermocompression bonding jig 25 is used to bond the bump electrodes of the bump electrodes of the semiconductor element in the symmetrical positions (upper left and lower right portions in FIG. 2(a)) and the external W, Connect M at the same time. After that, the thermocompression bonding jig was rotated 90', and the remaining symmetrical positional relationship (lower left and upper right portions of the same figure (a))
Connect the bump electrode and the external electrode. In this example, 2
All contact tP9 is completed in one process.
なお上記では熱圧着治具を移動または回転させているが
、本発明は上記に限らずシリコン基板とリードフレーム
を移動または回転させてもよい。Although the thermocompression bonding jig is moved or rotated in the above example, the present invention is not limited to the above, and the silicon substrate and the lead frame may be moved or rotated.
さらに熱圧着治具の形状もバンブ電極の配置に合せて最
適に変更することができる。Furthermore, the shape of the thermocompression bonding jig can be optimally changed according to the arrangement of the bump electrodes.
以上説明した様に本発明は、バンプ型半導体装置のバン
ブ電極とリードフレームとの接続を数回に分けて行なう
ことＫよシ、以下のような顕著な効果を有している。As explained above, the present invention has the following remarkable effects in spite of the fact that the bump electrode of the bump type semiconductor device and the lead frame are connected in several steps.
一電極（−接続点）当シの接続に必要な荷重は同じであ
ることから全１極を一度に接続する場合と０回に分ける
場合の熱圧着治具に必要な荷重は後者が前者の概略１／
（分割回数）で済むので、熱圧着治具の荷重は軽減され
る。したがってパンツ電極および外部電極の製造上の精
度と熱圧着治具（装置を含む）の精度の不備によって接
続時に数個のバンブ電極に荷重が集中することがあって
も、数回に分けて接続する分だけバンブ電極とその下方
の絶縁膜とシリコン基板に加わるストレスは軽減される
。特に大型化され接続点が多数（１００〜２００ケ所）
となって一度に接続する場合の熱圧着治具に必要な荷重
は増大の一途となっているので、上述の効果は顕著であ
る。すなわち従来の製造方法での欠点を除去し、接続時
の歩留と接続強度を著しく向上することができ、さらに
バンプ型半導体装置の信頼度を著しく向上させる事がで
きる。Since the load required to connect one electrode (- connection point) is the same, the load required for the thermocompression jig when connecting all 1 pole at once and when connecting 0 times is lower than the former. Outline 1/
(number of divisions), the load on the thermocompression jig is reduced. Therefore, even if the load is concentrated on several bump electrodes during connection due to imperfections in the manufacturing precision of the pants electrode and external electrode and the precision of the thermocompression bonding jig (including the device), the connection can be made in several steps. The stress applied to the bump electrode, the insulating film below it, and the silicon substrate is reduced accordingly. Particularly large and has many connection points (100 to 200 locations)
The above-mentioned effect is significant because the load required for a thermocompression bonding jig when making connections at once is increasing. That is, it is possible to eliminate the drawbacks of the conventional manufacturing method, to significantly improve the yield and connection strength during connection, and to significantly improve the reliability of the bump type semiconductor device.
第１図（ａ）および（ｂ）は本発明による第一の実施例
の平面図および縦断面図、第２図（ａ）および（ｂ）ｆ
ｆ第二の実施例の平面図および縦断面図、第３図（ａ）
および（ｂ）は従来の製造方法を示す平面図および縦断
面図である。
１１・・・・・・シリコン基板、１２・・・・・・絶縁
膜、１３・・・・・・バンブ電極、１４・・・・・・外
部電極、１５・・・・・・熱圧着治具。
代理人 弁理士 内 原 晋
第１区
（久）
第２図FIGS. 1(a) and (b) are a plan view and a longitudinal cross-sectional view of a first embodiment of the present invention, and FIGS. 2(a) and (b)f
f Plan view and vertical sectional view of the second embodiment, FIG. 3(a)
and (b) are a plan view and a longitudinal sectional view showing a conventional manufacturing method. 11...Silicon substrate, 12...Insulating film, 13...Bump electrode, 14...External electrode, 15...Thermocompression bonding Ingredients. Agent Patent Attorney Susumu Uchihara 1st Ward (Kyu) Figure 2
Claims (1)
電極と前記バンプ電極の各々と一対一に対応する複数個
の外部電極とを接続する半導体装置の製造方法において
、前記複数個のバンプ電極と前記複数個の外部電極との
接続を複数回に分割して熱圧着する熱圧着治具を具備し
たことを特徴とする半導体装置の製造方法。In a method for manufacturing a semiconductor device, in which a plurality of bump electrodes arranged on a substrate on which an IC chip is mounted are connected to a plurality of external electrodes in one-to-one correspondence with each of the bump electrodes, the plurality of bump electrodes are connected to each other. A method of manufacturing a semiconductor device, comprising: a thermocompression bonding jig for thermocompression bonding the connection between the external electrode and the plurality of external electrodes in multiple steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61179678A JPS6334940A (en) | 1986-07-29 | 1986-07-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61179678A JPS6334940A (en) | 1986-07-29 | 1986-07-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6334940A true JPS6334940A (en) | 1988-02-15 |
Family
ID=16069959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61179678A Pending JPS6334940A (en) | 1986-07-29 | 1986-07-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6334940A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03148146A (en) * | 1989-11-02 | 1991-06-24 | Nec Corp | Manufacture of film carrier semiconductor device |
| JP2003007773A (en) * | 2001-06-25 | 2003-01-10 | Nec Corp | Bonding tool and bonding method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62158339A (en) * | 1985-12-28 | 1987-07-14 | Tanaka Denshi Kogyo Kk | Adhesion method of bonding leads to ic chip in semiconductor device |
-
1986
- 1986-07-29 JP JP61179678A patent/JPS6334940A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62158339A (en) * | 1985-12-28 | 1987-07-14 | Tanaka Denshi Kogyo Kk | Adhesion method of bonding leads to ic chip in semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03148146A (en) * | 1989-11-02 | 1991-06-24 | Nec Corp | Manufacture of film carrier semiconductor device |
| JP2003007773A (en) * | 2001-06-25 | 2003-01-10 | Nec Corp | Bonding tool and bonding method |
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