JPS63316477A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS63316477A JPS63316477A JP15223787A JP15223787A JPS63316477A JP S63316477 A JPS63316477 A JP S63316477A JP 15223787 A JP15223787 A JP 15223787A JP 15223787 A JP15223787 A JP 15223787A JP S63316477 A JPS63316477 A JP S63316477A
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- film
- nitride film
- wiring
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 49
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 14
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 10
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000011733 molybdenum Substances 0.000 claims abstract description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000010937 tungsten Substances 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 30
- 238000002844 melting Methods 0.000 claims description 27
- 230000008018 melting Effects 0.000 claims description 23
- 238000010030 laminating Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 230000001590 oxidative effect Effects 0.000 abstract description 6
- 238000000206 photolithography Methods 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 238000000034 method Methods 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical group Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000036417 physical growth Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、高融点金属ゲートおよび配線を有する半導
体装置とその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a high melting point metal gate and wiring, and a method for manufacturing the same.
この発明は、酸化特性に劣るモリブデンおよびタングス
テン等の高融点金属ゲートおよび配線を有する半導体装
置およびその製造方法に関するも ゛ので、シリコ
ン等の半導体表面にシリコン酸化膜等のゲート絶縁膜を
形成し、さらにモリブテンまたはタングステン等の高融
点金属膜とＣＶＤ法により生成されたシリコンナイトラ
イド膜を順次形成する。次にフォトリソグラフィー等の
方法を用いてシリコンナイトライド膜および高融点金属
を１頌次選択的にエツチングし所望の形状を有するゲ−
ト電極および配線を形成する。次に再度シリコンナイト
ライド膜を形成し半導体全面を異方性の強いエツチング
を行い高融点金属および配線の側面と上面をシリコンナ
イトライド膜で被う。The present invention relates to a semiconductor device having a gate and wiring made of a high melting point metal such as molybdenum and tungsten which have poor oxidation properties, and a method for manufacturing the same. Furthermore, a film of a high melting point metal such as molybdenum or tungsten and a silicon nitride film produced by a CVD method are sequentially formed. Next, the silicon nitride film and the high melting point metal are selectively etched using a method such as photolithography to form a gate having the desired shape.
Form electrodes and wiring. Next, a silicon nitride film is formed again, and the entire surface of the semiconductor is etched with strong anisotropy to cover the sides and top surface of the high melting point metal and wiring with the silicon nitride film.
以上の工程を含む半導体装置の製造方法であり、酸化等
の熱処理によるゲート電極配線の変質の問題がなくなり
安定した半導体装置を提供できるようにしたものである
。This is a method of manufacturing a semiconductor device including the above steps, and it is possible to provide a stable semiconductor device without the problem of deterioration of gate electrode wiring due to heat treatment such as oxidation.
従来から金属・絶縁膜・半導体の構造を有するＭＩＳ型
半導体において、ゲート電極および配線に°は多結晶シ
リコンが使用されていたが、近年のＩＣの高集積化に従
い配線の遅延が深刻な問題となりつつある。その対策と
してゲート電極および配線材料を多結晶シリコンより抵
抗の低い、モリブデン（ＭＯ）やタングステン（Ｗ）等
の高融点金属が採用されつつある。第２図（ａｌは高融
点金属１３をゲート電極および配線としてパターニング
し、ソース・ドレイン１５を形成した後のＭＩＳ型半導
体装置の断面模式図である。第２図（ａｌにおいて、高
融点金属１３のエツチングあるいはイオン注入によるソ
ース・ドレイン１５を形成する工程で、Ｔｇ、極周辺の
ＳｉＯ□が損傷を受ける。この損傷を受けた絶縁膜１４
を回復させるために、第２１Ｄ（ｂ＋に示す様に熱処理
を酸化雰囲気中で行い再酸化させていた。Conventionally, polycrystalline silicon has been used for gate electrodes and wiring in MIS semiconductors that have a structure of metal, insulating film, and semiconductor, but as ICs have become more highly integrated in recent years, wiring delays have become a serious problem. It's coming. As a countermeasure, high melting point metals such as molybdenum (MO) and tungsten (W), which have lower resistance than polycrystalline silicon, are being used for gate electrodes and wiring materials. FIG. 2 (al is a schematic cross-sectional view of the MIS type semiconductor device after patterning the high melting point metal 13 as a gate electrode and wiring and forming the source/drain 15. In the step of forming the source/drain 15 by etching or ion implantation, the Tg and SiO□ around the pole are damaged.
In order to recover the properties, heat treatment was performed in an oxidizing atmosphere as shown in No. 21D (b+) to reoxidize.
ところがＭｏやＷ等の高融点金属の酸化膜１７は不安定
であり、その後の素子特性の不安定性の一因となってい
た。However, the oxide film 17 made of a high-melting point metal such as Mo or W is unstable, which is one of the causes of subsequent instability in device characteristics.
第２図伽）におけるＭｏやＷ等の高融点金属の酸化膜１
７は不安定であり、その後の素子特性の不安定性の一因
となっていた。特に酸化膜１７は昇華性を有しており、
熱処理条件を厳密に管理せねばならいないので第２図に
示す方法により形成した素子の歩留りは非常に低かった
。Oxide film 1 of high melting point metal such as Mo and W in Figure 2)
No. 7 was unstable and contributed to the subsequent instability of device characteristics. In particular, the oxide film 17 has sublimation property,
Since the heat treatment conditions must be strictly controlled, the yield of devices formed by the method shown in FIG. 2 was extremely low.
この発明は、高融点金属をゲート電極および配線材料に
用いた半導体装置の特性安定化を図ることを目的とする
ものである。The object of the present invention is to stabilize the characteristics of a semiconductor device using a high melting point metal as a gate electrode and wiring material.
上記問題点を解決するためにこの発明は、ＭＯやＷ等の
高融点金属の上面および側面をシリコンナイトライド膜
で被ってから、エツチングあるいはイオン注入により損
傷を受けた絶縁膜１４を回復するために酸化性雰囲気中
で行い再酸化する。In order to solve the above problems, the present invention covers the top and side surfaces of a high-melting point metal such as MO or W with a silicon nitride film, and then recovers the insulating film 14 that has been damaged by etching or ion implantation. Re-oxidize in an oxidizing atmosphere.
シリコンナイトライド膜（ＳｉＮｘ膜）は酸化性雰囲気
に対し耐性を持つので、シリコンナイトライド膜で被わ
れた高融点金属膜は、損傷回復用の酸化を行っても酸化
されないため、ゲート電極・配線の特性を損なう事がな
い。Silicon nitride film (SiNx film) is resistant to oxidizing atmosphere, so the high-melting point metal film covered with silicon nitride film will not be oxidized even if oxidation is performed for damage recovery, so gate electrodes and wiring It does not impair its characteristics.
また、シリコンナイトライド膜自体は良好な絶縁特性を
持つため配線間の眉間絶縁膜にも適用できる。Furthermore, since the silicon nitride film itself has good insulating properties, it can also be applied as an insulating film between the eyebrows between wiring lines.
本発明の基本構成は、ゲート電極・配線がＭ。 The basic configuration of the present invention is that the gate electrode and wiring are M.
やＷ等の高融点金属であるＭＩＳ型半導体装置において
、高融点金属の上面および側面等をシリコンナイトライ
ド（ＳｉＮｘ膜）で被う事にある。この様にする事によ
りその後のプロセスで酸化性雰囲気にて黙想・理を行っ
ても高融点金属は酸化性雰囲気にさらされないために変
質する事がなく安定した高融点金属ゲートを有するＭＩ
Ｓ型半導体装置を形成できる。高融点金属の上面および
側面等をシリコンナイトライド膜で被う方法に関して以
下に実施例を示す。In an MIS type semiconductor device using a high melting point metal such as or W, the top surface and side surfaces of the high melting point metal are covered with silicon nitride (SiNx film). By doing this, even if meditation or theory is performed in an oxidizing atmosphere in the subsequent process, the high melting point metal will not be exposed to the oxidizing atmosphere, so it will not change in quality, and the MI will have a stable high melting point metal gate.
An S-type semiconductor device can be formed. An example will be shown below regarding a method of covering the top and side surfaces of a high melting point metal with a silicon nitride film.
第１図は本発明の実施例の工程順断面図である。FIG. 1 is a step-by-step sectional view of an embodiment of the present invention.
まずシリコンＭＩＳ型半導体装置に関し説明する。First, a silicon MIS type semiconductor device will be explained.
第１図１ａｌに示すようにシリコン基板１の上にゲート
絶縁膜２を積層し、さらにＭＯやＷ等の高融点金属膜３
およびシリコンナイトライド膜４を順次積層する。ゲー
ト絶縁膜２は一般には酸化法で形成されたシリコン酸化
膜であるが、他の絶縁膜、例えばＣＶＤによるシリコン
酸化膜やシリコン酸化膜以外の絶縁膜であっても良い、
ＭｏやＷ等の高融点金属膜３はスパッター法等の物理的
成長法（ＰＶＤ法）あるいは化学気相成長法（ＣＶＤ法
）によって積層される。また、この高融点金属膜３は純
粋な単一金属でなくとも良い０例えばＭｏおよびタンタ
ル（Ｔａ）の合金あるいはＷとチタン（Ｔｉ）の合金あ
るいはシリコン（Ｓｉ）等の元素が相当量入ったもので
も良い。シリコンナイトライド膜４は化学式でＳｉＮｘ
と記される。このシリコンナイトライド膜４はたとえば
ＣＶＤ法により形成される。その一つの例として、ジク
ロルシラン（ＳｉＨ□Ｃｊ！、）とアンモニア（ＮＨｚ
）の２種類のガスをＣＶＤ装置を用い、７００℃〜１０
００℃の範囲の温度で化学反応させてシリコンナイトラ
イド膜を形成できる。As shown in FIG. 1al, a gate insulating film 2 is laminated on a silicon substrate 1, and a high melting point metal film 3 such as MO or W is further layered.
and silicon nitride film 4 are sequentially laminated. The gate insulating film 2 is generally a silicon oxide film formed by an oxidation method, but it may also be another insulating film, such as a silicon oxide film formed by CVD or an insulating film other than a silicon oxide film.
The high melting point metal film 3 such as Mo or W is laminated by a physical growth method (PVD method) such as a sputtering method or a chemical vapor deposition method (CVD method). The high melting point metal film 3 does not have to be a pure single metal; for example, it may contain a considerable amount of elements such as an alloy of Mo and tantalum (Ta), an alloy of W and titanium (Ti), or silicon (Si). Anything is fine. The chemical formula of the silicon nitride film 4 is SiNx
It is written as This silicon nitride film 4 is formed by, for example, a CVD method. One example is dichlorosilane (SiH□Cj!) and ammonia (NHz
) using a CVD device at 700°C to 10°C.
A silicon nitride film can be formed by chemical reaction at a temperature in the range of 0.000C.
また別の例として、シラン（ＳｉＨ４）とＮ）１３の２
種類のガスをプラズマＣＶＤ装置を用い、６００℃〜９
００℃の範囲の温度で化学反応させてシリコンナイトラ
イド膜を形成できる。さらにまた別の例として、Ｓ：Ｈ
ａとＮｕｓの２種類のガスをプラズマＣＶＤ装置または
光ＣＶＤ装置を用い、θ℃〜５００℃の温度で化学反応
させてシリコンナイトライド膜を形成できる。シリコン
ナイトライド膜４はＰＣＤ法を用いても形成できる０例
えばシリコンナイトライドそのものをターゲットにして
スパッター法で形成できる。As another example, silane (SiH4) and N) 13 2
Using plasma CVD equipment, various gases are heated at 600°C to 9°C.
A silicon nitride film can be formed by chemical reaction at a temperature in the range of 0.000C. As yet another example, S:H
A silicon nitride film can be formed by chemically reacting two types of gases, a and Nus, using a plasma CVD device or a photo-CVD device at a temperature of θ° C. to 500° C. The silicon nitride film 4 can also be formed using the PCD method, and for example, it can be formed by a sputtering method using silicon nitride itself as a target.
次に第１図（ｂｌに示す様にフォトリソグラフィー等の
方法を用いてシリコンナイトライド膜４およびＭＯやＷ
等の高融点金属の電極・配線を順次選択的にエツチング
除去し、所望の電極配線を形成する。このエツチング工
程の時にシリコンナイトライド膜４はゲート電極・配線
３より寸法が小さくならないようにする。エツチングは
シリコンナイトライドＷｉ４とゲート電極・配線３と等
寸法の大きさになるように異方性エツチング法を用い垂
直にエツチングする事が望ましい。エツチング終了後は
フォトレジスト５を除去する。Next, as shown in FIG. 1 (bl), the silicon nitride film 4 and MO or W
The electrodes/wirings made of high-melting point metals are sequentially and selectively etched away to form desired electrode wirings. During this etching step, the size of the silicon nitride film 4 should not be made smaller than that of the gate electrode/wiring 3. It is preferable that the etching be performed vertically using an anisotropic etching method so that the silicon nitride Wi 4 and the gate electrode/wiring 3 have the same size. After etching is completed, the photoresist 5 is removed.
次に第１図（Ｃ１に示す様に第２のシリコンナイトライ
ド膜６を積層する。この第２のシリコンナイトライド膜
６は第１のシリコンナイトライド族と同様の方法で形成
される。第２のシリコンナイトライド膜６は第１のシリ
コンナイトライド膜４の上だけでなく、ゲート電極３の
側面にも積層する。Next, as shown in FIG. 1 (C1), a second silicon nitride film 6 is laminated. This second silicon nitride film 6 is formed by the same method as the first silicon nitride group. The second silicon nitride film 6 is laminated not only on the first silicon nitride film 4 but also on the side surfaces of the gate electrode 3.
次に第１図Ｔｄｌに示す様に、第１図＋ｃ＋のウェハ全
面を異方性エツチングし、ゲート電極・配線３の側面の
第２のシリコンナイトライド膜の厚みが厚い為、側面の
第２のシリコンナイトライド膜６を残し、他の領域の第
２のシリコンナイトライド膜６を除去する。この時第１
のシリコンナイトライドＭ４もエツチングされるが、充
分な厚みを積層しておけば、その後のプロセスに支障が
ない程度に第１のシリコンナイトライド膜が残る。この
ようにしてＷまたはＭｏ等の高融点金属の上面および側
面がシリコンナイトライド膜で被われ構造を作る事がで
きる。第１図には示していないが、ソースおよびドレイ
ンを形成するためのイオン注入は第１図（ｂｌから第１
図＋ｄ＋までの工程の間に行う事が可能である。Ｍｏや
Ｗ等の高融点金属膜は柱状晶の結晶構造を持つため、単
独で配線として金属膜を用いる場合にも応用できること
は言うまでもな゛ い、さらにゲート電極・配線が高
融点金属の場合以外にも酸化等の熱処理により変化させ
たくないものに関して本発明を用いることは容易である
。Next, as shown in FIG. 1 Tdl, the entire surface of the wafer +c+ in FIG. 1 is anisotropically etched. The second silicon nitride film 6 in other areas is removed, leaving the second silicon nitride film 6 in the second area. At this time the first
The first silicon nitride film M4 is also etched, but if the first silicon nitride film is laminated to a sufficient thickness, the first silicon nitride film remains to the extent that it does not interfere with subsequent processes. In this way, a structure can be created in which the top and side surfaces of a high melting point metal such as W or Mo are covered with a silicon nitride film. Although not shown in FIG. 1, ion implantation for forming the source and drain is shown in FIG.
This can be done during the steps up to Figure +d+. Since high melting point metal films such as Mo and W have a columnar crystal structure, it goes without saying that they can be applied to cases where the metal film is used alone as wiring, and furthermore, it can be used in cases other than cases where the gate electrode and wiring are made of high melting point metals. The present invention can also be easily applied to materials that should not be changed by heat treatment such as oxidation.
上記の説明ではシリコン半導体を中心に説明したが他の
半導体装置にも応用できる。たとえば、ＧａＡｓ等の化
学物半導体のゲート電極・配線に高融点金属を用いる場
合にも同様に適用できる。Although the above description has focused on silicon semiconductors, it can also be applied to other semiconductor devices. For example, the present invention can be similarly applied to the case where a high melting point metal is used for the gate electrode/wiring of a chemical semiconductor such as GaAs.
また、本発明の目的はシリコンナイトライド膜で被った
ものを保護する事ができることであるから、熱処理等に
耐えるくらいの充分な厚みと屈折率（膜質）を有するだ
けで良い、従ってシリコンナイトライド膜が厚み方向に
１部だけあるもの、例えばＳｉｎ、とシリコンナイトラ
イド膜とを組合わせた構造でも良い、またシリコンナイ
トライド膜とシリコンオキシナイトライド膜とを組合わ
せた構造でも良い、さらにまた、シリコンナイトライド
膜とシリコンオキシナイトライドＧ（ＳｉＮｘＯｙｌｌ
ｉ）と５ｉＯｚ膜とを組合わせた構造でも良い。Furthermore, since the purpose of the present invention is to be able to protect objects covered with a silicon nitride film, it is only necessary to have sufficient thickness and refractive index (film quality) to withstand heat treatment, etc. A structure in which only one part of the film is present in the thickness direction, for example, a combination of a Sin film and a silicon nitride film, or a structure in which a silicon nitride film and a silicon oxynitride film are combined, may also be used. , silicon nitride film and silicon oxynitride G (SiNxOyll)
A structure combining i) and a 5iOz film may also be used.
この発明は以上説明した様に、ゲート電極・配線の上面
および側面をシリコンナイトライド膜で被うので、酸化
等の熱処理によるゲート電極・配線の変質等の問題がな
（なり、安定した半導体装置を形成できる。As explained above, in this invention, since the top and side surfaces of the gate electrode and interconnect are covered with a silicon nitride film, there are no problems such as deterioration of the gate electrode or interconnect due to heat treatment such as oxidation (this results in stable semiconductor devices). can be formed.
第１図＋ａｌ〜（ｅｌはこの発明の半導体装置の製造方
法の工程順を示す断面図、第２図（ａｌ〜ｆｂｌは従来
の半導体装置の製造方法の工程順を示す断面図である。
１．１１・・・シリコン基板
２．１２・ ・ ・ゲート寒色縁膜
３．１３・・・ゲート電極・配線
４・・・・・第１のシリコンナイトライド膜５・・・・
・フォトレジスト
６・・・・・第２のシリコンナイトライド膜１４・・・
・・損傷を受けた絶縁膜
１５・・・・・ソース・ドレイン
１６・・・・・シリコン酸化膜
１７・・・・・高融点金属膜の酸化膜
以上
出願人 セイコー電子工業株式会社
（ａ）（ｄ）FIG. 1+al~(el is a cross-sectional view showing the process order of the semiconductor device manufacturing method of the present invention, FIG. 2 (al~fbl is a cross-sectional view showing the process order of the conventional semiconductor device manufacturing method. .11...Silicon substrate 2.12...Gate cold color film 3.13...Gate electrode/wiring 4...First silicon nitride film 5...
・Photoresist 6...Second silicon nitride film 14...
...Damaged insulating film 15...Source/drain 16...Silicon oxide film 17...Oxide film of high melting point metal film and above Applicant Seiko Electronics Co., Ltd. (a) (d)
Claims (4)
ンナイトライド膜で被う事を特徴とする半導体装置。(1) A semiconductor device characterized in that the top and side surfaces of the gate electrode and wiring are covered with a silicon nitride film.
ブデン等の高融点金属である特許請求の範囲第１項記載
の半導体装置。(2) The semiconductor device according to claim 1, wherein the gate electrode and the wiring are made of a high melting point metal such as tungsten or molybdenum.
成した膜である特許請求の範囲第１項記載の半導体装置
。(3) The semiconductor device according to claim 1, wherein the silicon nitride film is a film formed by chemical vapor deposition.
と、第１のシリコンナイトライド膜を形成する工程と、
前記第１のシリコンナイトライド膜とゲート電極および
配線層となる膜とを所望の形状に加工しゲート電極およ
び配線層を形成する工程と、第２のシリコンナイトライ
ド膜を積層する工程と、異方性エッチングを用いシリコ
ンナイトライドをエッチングしゲート電極および配線層
の側面に第２のシリコンナイトライド膜を形成する工程
とを含む事を特徴とする半導体装置の製造方法。(4) a step of forming a film that will become a gate electrode and a wiring layer; a step of forming a first silicon nitride film;
The step of processing the first silicon nitride film and the film that will become the gate electrode and wiring layer into a desired shape to form the gate electrode and the wiring layer, and the step of laminating the second silicon nitride film are different. 1. A method of manufacturing a semiconductor device, comprising the step of etching silicon nitride using directional etching to form a second silicon nitride film on the side surfaces of a gate electrode and a wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15223787A JPS63316477A (en) | 1987-06-18 | 1987-06-18 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15223787A JPS63316477A (en) | 1987-06-18 | 1987-06-18 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63316477A true JPS63316477A (en) | 1988-12-23 |
Family
ID=15536083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15223787A Pending JPS63316477A (en) | 1987-06-18 | 1987-06-18 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63316477A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6399960B1 (en) | 1998-07-16 | 2002-06-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with semiconductor circuit comprising semiconductor units, and method for fabricating it |
| US6608357B1 (en) | 1998-07-16 | 2003-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device equipped with semiconductor circuits composed of semiconductor elements and process for production thereof |
| US6707120B1 (en) * | 1996-11-20 | 2004-03-16 | Intel Corporation | Field effect transistor |
| JP2007281469A (en) * | 2007-04-03 | 2007-10-25 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
-
1987
- 1987-06-18 JP JP15223787A patent/JPS63316477A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6707120B1 (en) * | 1996-11-20 | 2004-03-16 | Intel Corporation | Field effect transistor |
| US6399960B1 (en) | 1998-07-16 | 2002-06-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with semiconductor circuit comprising semiconductor units, and method for fabricating it |
| US6586766B2 (en) | 1998-07-16 | 2003-07-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with semiconductor circuit comprising semiconductor units, and method of fabricating it |
| US6608357B1 (en) | 1998-07-16 | 2003-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device equipped with semiconductor circuits composed of semiconductor elements and process for production thereof |
| US6822293B2 (en) | 1998-07-16 | 2004-11-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device equipped with semiconductor circuits composed of semiconductor elements and process for production thereof |
| US7078768B2 (en) | 1998-07-16 | 2006-07-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device equipped with semiconductor circuits composed of semiconductor elements and process for production thereof |
| US7371623B2 (en) | 1998-07-16 | 2008-05-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with semiconductor circuit comprising semiconductor units, and method for fabricating it |
| US7709844B2 (en) | 1998-07-16 | 2010-05-04 | Semiconductor Energy Laboratory Co., Ltd | Semiconductor device equipped with semiconductor circuits composed of semiconductor elements and processes for production thereof |
| JP2007281469A (en) * | 2007-04-03 | 2007-10-25 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
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