JPS63310123A - Silicon semiconductor substrate - Google Patents
Silicon semiconductor substrateInfo
- Publication number
- JPS63310123A JPS63310123A JP14630987A JP14630987A JPS63310123A JP S63310123 A JPS63310123 A JP S63310123A JP 14630987 A JP14630987 A JP 14630987A JP 14630987 A JP14630987 A JP 14630987A JP S63310123 A JPS63310123 A JP S63310123A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon
- semiconductor substrate
- substrate
- silicon semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 40
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 40
- 239000010703 silicon Substances 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 9
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 7
- 239000011856 silicon-based particle Substances 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 8
- 238000005247 gettering Methods 0.000 abstract description 5
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract 1
- 230000006378 damage Effects 0.000 description 12
- 239000002245 particle Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000013078 crystal Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005422 blasting Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006355 external stress Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、半導体素子製造のためのシリコン半導体基板
に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a silicon semiconductor substrate for manufacturing semiconductor devices.
(従来の技術)
半導体素子の製造工程において、シリコン半導体基板の
表面が不純物によって汚染されていると、半導体素子の
特性が著しく劣化し歩留りか低下する。その対策として
、シリコン半導体結晶内部の結晶欠陥またはシリコン基
板の裏面に形成した歪層に不純物を吸着させる方法が実
施されている。以下、この方法による効果をゲッタリン
グ効果と呼ぶ。(Prior Art) In the manufacturing process of a semiconductor device, if the surface of a silicon semiconductor substrate is contaminated with impurities, the characteristics of the semiconductor device will be significantly deteriorated and the yield will be reduced. As a countermeasure against this problem, a method has been implemented in which impurities are adsorbed to crystal defects inside a silicon semiconductor crystal or to a strained layer formed on the back surface of a silicon substrate. Hereinafter, the effect achieved by this method will be referred to as the gettering effect.
上記したシリコン基板の裏面に歪層を形成させる方法と
しては、機械的に部分破壊または加工するショツトブラ
スト法、研磨等の方法やレーザー等を使用した部分的に
熱的破壊を与える方法が知られている。以下、これらの
方法による処理をバックダメージ処理と呼ぶことにする
。As methods for forming a strained layer on the back surface of the silicon substrate mentioned above, there are known methods such as shot blasting, which involves mechanical partial destruction or processing, methods such as polishing, and methods in which partial thermal destruction is applied using a laser or the like. ing. Hereinafter, processing using these methods will be referred to as back damage processing.
(発151か解決しようとする聞届点)しかし上記ハッ
クダメージ処理を採用した場合、ハックダメージ処理を
行う時にシリコン半導体基板の破壊されたシリコン粒子
か、基板から剥離、脱落するか、この時に脱落しなかっ
たシリコン粒子も、半導体素子の製造工程において、振
動等による外部応力や熱処理による熱応力あるいはエツ
チング工程等てさらに基板裏面から剥離、脱落し、その
シリコン粒子がシリコン基板表面に付着し、半導体素子
製造の歩留りか低下してしまうという問題点がある。(Issuance 151 or the point to be solved) However, if the above hack damage treatment is adopted, the destroyed silicon particles of the silicon semiconductor substrate will peel off or fall off from the substrate during the hack damage treatment, or will fall off at this time. During the manufacturing process of semiconductor devices, the silicon particles that did not peel off or fall off from the back surface of the substrate due to external stress due to vibrations, thermal stress due to heat treatment, etching process, etc., and the silicon particles adhere to the surface of the silicon substrate, causing the semiconductor There is a problem in that the yield of device manufacturing decreases.
(問題点を解決するための手段)
本発明は、上記問題点を解決する目的でなされたものて
、下記技術手段を採用する。(Means for Solving the Problems) The present invention has been made for the purpose of solving the above problems, and employs the following technical means.
すなわち半導体素子製造に用いるシリコン半導体基板で
あって、前記シリコン半導体の一面に機械的または熱的
に部分的破壊層が形成され、該部分的破壊層の表面にシ
リコン層または窒化シリコン層が形成されていることを
、その特徴とする。That is, a silicon semiconductor substrate used for manufacturing semiconductor devices, in which a partially broken layer is mechanically or thermally formed on one surface of the silicon semiconductor, and a silicon layer or a silicon nitride layer is formed on the surface of the partially broken layer. Its characteristic is that it is
(作用)
バックダメージ処理によって部分的破壊層を形成された
シリコン半導体基板の表面には、半導体素子製造工程に
おいて振動等による外部応力、熱処理による熱応力ある
いはエツチング工程等で剥離、脱落し、半導体素子の歩
留りを低下させるシリコン粒子か付着しているか、本発
明によれば、これらの不安定なシリコン粒子は、上記シ
リコン層または窒化膜層によって覆われ、ゲッタリング
効果を維持しつつ、半導体素子製造工程においてシリコ
ン粒子の剥離、脱落が防止できることになる。(Function) On the surface of a silicon semiconductor substrate on which a partially destroyed layer has been formed by back damage treatment, it may peel or fall off due to external stress due to vibration etc. in the semiconductor device manufacturing process, thermal stress due to heat treatment, etching process, etc. According to the present invention, these unstable silicon particles are covered by the silicon layer or nitride film layer, thereby improving semiconductor device manufacturing while maintaining the gettering effect. This means that peeling and falling off of silicon particles can be prevented during the process.
(実施例) 以下、図面に基いて本発明をさらに詳述する。(Example) Hereinafter, the present invention will be explained in further detail based on the drawings.
第1図は本発明に係るシリコン半導体基板の断面の模式
図を示す。第1図において、lはシリコン基板で、基板
1の一面にバックダメージ処理によって4の部分的破壊
層を形成する。3は、部分的破壊層4によって形成され
た歪層である。5はPVD法またはCVD法によって付
着されたシリコン層または窒化シリコン層である。FIG. 1 shows a schematic cross-sectional view of a silicon semiconductor substrate according to the present invention. In FIG. 1, l is a silicon substrate, and a partially destroyed layer 4 is formed on one surface of the substrate 1 by back damage treatment. 3 is a strained layer formed by the partially destroyed layer 4; 5 is a silicon layer or a silicon nitride layer deposited by PVD or CVD.
更に具体的には、本発明に係る半導体基板1の一面(以
下、「裏面」と称する)に、機械的または熱的に部分的
破壊層を形成した後、裏面に蒸着法、スパッタ法等のP
VD法(フィジカルベイパーデポシション:物理的気相
成長法)またはCVD法(ケミカルベイパーデポジショ
ン:化学的気相成長法)てシリコン層または窒化シリコ
ン層5を付着させ、部分的破壊層4の表面を覆っている
。More specifically, after forming a partially destroyed layer mechanically or thermally on one surface (hereinafter referred to as "back surface") of the semiconductor substrate 1 according to the present invention, the back surface is subjected to a vapor deposition method, a sputtering method, etc. P
A silicon layer or silicon nitride layer 5 is deposited using a VD method (physical vapor deposition method) or a CVD method (chemical vapor deposition method), and the surface of the partially destroyed layer 4 is is covered.
なお、図面において、2は無欠陥層、3は歪層を示す。In the drawings, 2 indicates a defect-free layer and 3 indicates a strained layer.
本発明者は、まずC7法によって製造された結晶方位(
100)面のシリコン半導体基板を用意し、該基板の裏
面にバックダメージ法の一種であるショットブラスト法
によって部分的破壊層を形成し、前記部分的破壊層を形
成した該基板の裏面に、CVD法によって、多結晶シリ
コン層を0.5延a 、1pm 、1.5終1覆った。The present inventor first investigated the crystal orientation (
A silicon semiconductor substrate with a surface of 100) is prepared, a partially destroyed layer is formed on the back side of the substrate by shot blasting, which is a type of back damage method, and a CVD process is applied to the back side of the substrate on which the partially broken layer is formed. A polycrystalline silicon layer of 0.5 mm thick, 1 pm thick, and 1.5 mm thick was covered by the method.
次に、上記方法によって作成したシリコン半導体基板を
フッ酸に浸漬し、引上げ、基板表面の汚染状態を観察し
た。その結果を第2図に示す。縦軸は表面検査装置によ
り測定した粒径0.25 絡m以上の粒子の個数を示し
、横軸は処理の有無及び処理種を示す。Next, the silicon semiconductor substrate produced by the above method was immersed in hydrofluoric acid, pulled up, and the contamination state of the substrate surface was observed. The results are shown in FIG. The vertical axis indicates the number of particles with a particle size of 0.25 mm or more measured by a surface inspection device, and the horizontal axis indicates the presence or absence of treatment and the type of treatment.
第2図より明らかな如く、ハックダメージ処理を施して
いない基板表面の粒子数か3×10個程度なのに比較し
、バックダメージ処理を裏面に施した基板は3x 10
”個の粒子が付着していた。しかし、CVD法によって
多結晶シリコン層をハックダメージ層の上に覆った基板
の場合、多結晶シリコン層の厚さが0.5μm、1μ重
、1.s、LL11のものではそれぞれ102個、5X
lO個、4xlO個の粒子数になった。つまり、バック
ダメージ処理をしたシリコン半導体基板の裏面を、CV
D法により多結晶シリコン層で覆うことによって、ゲッ
タリンク効果を維持しつつ裏面の部分的破壊層がらのシ
リコン粒子の剥離、脱落を防ぎ、基板表面への粒子の付
着を防止することか回走であることを確認した。As is clear from Figure 2, the number of particles on the surface of the substrate without hack damage treatment is about 3 x 10, compared to 3 x 10 on the substrate with back damage treatment on the back side.
However, in the case of a substrate in which a polycrystalline silicon layer was covered with a hack damage layer using the CVD method, the thickness of the polycrystalline silicon layer was 0.5 μm, 1 μm thick, and 1.s , 102 pieces each for LL11, 5X
The number of particles was 10, 4x10. In other words, CV
By covering with a polycrystalline silicon layer using the D method, it is possible to prevent silicon particles from peeling off or falling off from the partially destroyed layer on the back side while maintaining the getterlink effect, and to prevent particles from adhering to the substrate surface. It was confirmed that
なお本発明の実施例では、シリコン半導体装置の裏面を
覆うのは、CVD法による多結晶シリコン層としたか、
CVD法の代わりにPVD法でも良いし、多結晶シリコ
ン層の代わりに、単結晶シリコン、アモルファスシリコ
ン、窒化シリコン層でも良い。In the embodiment of the present invention, the back surface of the silicon semiconductor device is covered with a polycrystalline silicon layer formed by CVD method, or
A PVD method may be used instead of a CVD method, and a single crystal silicon, amorphous silicon, or silicon nitride layer may be used instead of a polycrystalline silicon layer.
(発明の効果)
本発明は、以ト説明したように、半導体素子製造に用い
るシリコン半導体基板の一面に、機械的または熱的に部
分的破壊層を形成し、該部分的破壊層の表面にシリコン
層または窒化シリコン層を形成して構成され、ゲッタリ
ング効果を維持しつつ、シリコン粒子の剥離、脱落が妨
げられるのて、半導体素子製造工程での基板表面への粒
子の付着を抑制でき、この結果、半導体素子製造の歩留
りが向上するという効果を奏する。(Effects of the Invention) As explained below, the present invention forms a partially destroyed layer mechanically or thermally on one surface of a silicon semiconductor substrate used for semiconductor device manufacturing, and forms a partially destroyed layer on the surface of the partially destroyed layer. It is constructed by forming a silicon layer or a silicon nitride layer, and while maintaining the gettering effect, it prevents silicon particles from peeling off or falling off, so it can suppress the adhesion of particles to the substrate surface during the semiconductor device manufacturing process. As a result, the yield of semiconductor device manufacturing is improved.
第1図は、本発明によるシリコン半導体基板の断面の模
式図、第2図は、シリコン半導体基板の裏面の処理方法
と、表面汚染粒子との関係図である。
l・・・シリコン半導体基板
4・・・バックタメーシ処理による部分的破壊層5・・
・シリコン層または窒化シリコン層特許出願人 九州電
子金属株式会社
特許出願人 大阪チタニウム製造株式会社代 理 人
弁理士 森 正 製筒1図
1・・・シリコン半導体基板
4・・・バックタメーシ処理による部分的破壊層5・・
・シリコン層または窒化シリコン層第2図FIG. 1 is a schematic cross-sectional view of a silicon semiconductor substrate according to the present invention, and FIG. 2 is a diagram showing the relationship between a method for treating the back surface of a silicon semiconductor substrate and surface contamination particles. l...Silicon semiconductor substrate 4...Partially destroyed layer 5 due to backtaming treatment...
・Silicon layer or silicon nitride layer Patent applicant: Kyushu Electronic Metals Co., Ltd. Patent applicant: Osaka Titanium Manufacturing Co., Ltd. Representative: Patent attorney Tadashi Mori Manufacturing tube 1 Figure 1...Silicon semiconductor substrate 4...Partially due to backtaming treatment Destruction layer 5...
・Silicon layer or silicon nitride layer Figure 2
Claims (3)
って、前記シリコン半導体基板の一面に、機械的または
熱的に部分的破壊層が形成され、該部分的破壊層の表面
にシリコン層または窒化シリコン層が形成されているこ
とを特徴とするシリコン半導体基板。(1) A silicon semiconductor substrate used for manufacturing semiconductor devices, in which a partially destroyed layer is mechanically or thermally formed on one surface of the silicon semiconductor substrate, and a silicon layer or silicon nitride is formed on the surface of the partially destroyed layer. A silicon semiconductor substrate characterized in that a layer is formed.
ミカルベイパーデボジション;化学的気相成長)法で形
成されている特許請求の範囲第(1)項記載のシリコン
半導体基板。(2) The silicon semiconductor substrate according to claim (1), wherein the silicon layer or the silicon nitride layer is formed by a CVD (chemical vapor deposition) method.
ィジカルベイパーデポジション;物理的気相成長)法で
形成される特許請求の範囲第(1)項記載のシリコン半
導体基板。(4)シリコン層が多結晶質である特許請求
の範囲第(1)項記載のシリコン半導体基板。(3) The silicon semiconductor substrate according to claim (1), wherein the silicon layer or the silicon nitride layer is formed by a PVD (physical vapor deposition) method. (4) The silicon semiconductor substrate according to claim (1), wherein the silicon layer is polycrystalline.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14630987A JPS63310123A (en) | 1987-06-12 | 1987-06-12 | Silicon semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14630987A JPS63310123A (en) | 1987-06-12 | 1987-06-12 | Silicon semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63310123A true JPS63310123A (en) | 1988-12-19 |
Family
ID=15404760
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14630987A Pending JPS63310123A (en) | 1987-06-12 | 1987-06-12 | Silicon semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63310123A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03235333A (en) * | 1990-02-13 | 1991-10-21 | Mitsubishi Electric Corp | Semiconductor substrate having improved getter effect, semiconductor device using the substrate and manufacture thereof |
US5389551A (en) * | 1991-02-21 | 1995-02-14 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor substrate |
US5892292A (en) * | 1994-06-03 | 1999-04-06 | Lucent Technologies Inc. | Getterer for multi-layer wafers and method for making same |
-
1987
- 1987-06-12 JP JP14630987A patent/JPS63310123A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03235333A (en) * | 1990-02-13 | 1991-10-21 | Mitsubishi Electric Corp | Semiconductor substrate having improved getter effect, semiconductor device using the substrate and manufacture thereof |
US5389551A (en) * | 1991-02-21 | 1995-02-14 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor substrate |
US5892292A (en) * | 1994-06-03 | 1999-04-06 | Lucent Technologies Inc. | Getterer for multi-layer wafers and method for making same |
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