JPS63307511A - Overcurrent preventing circuit - Google Patents
Overcurrent preventing circuitInfo
- Publication number
- JPS63307511A JPS63307511A JP14362587A JP14362587A JPS63307511A JP S63307511 A JPS63307511 A JP S63307511A JP 14362587 A JP14362587 A JP 14362587A JP 14362587 A JP14362587 A JP 14362587A JP S63307511 A JPS63307511 A JP S63307511A
- Authority
- JP
- Japan
- Prior art keywords
- overcurrent
- transistor
- output
- trq2
- bipolar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 13
- 230000002265 prevention Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、電子機器等の電源として用いる定電圧発生
装置の過電流防止回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an overcurrent prevention circuit for a constant voltage generator used as a power source for electronic equipment and the like.
この発明は、定電圧発生装置において、出力の短絡等に
より過大な電流が流れた場合に、その出力電流を制限し
、過電流による素子の破壊を防止するものである。This invention limits the output current in a constant voltage generator when an excessive current flows due to an output short circuit or the like, thereby preventing destruction of elements due to the overcurrent.
従来、ＭＯＳトランジスタで構成された定電圧発生装置
では、過電流検出トランジスタがＭＯＳトランジスタで
形成されていた。Conventionally, in a constant voltage generating device configured with MOS transistors, an overcurrent detection transistor has been formed with a MOS transistor.
しかし、ＭＯＳトランジスタのしきい値電圧は、通常の
プロセスでは狙い値に対して±０．２Ｖ程度はバラツク
ため、過電流の検出精度が悪いという欠点があった。However, in a normal process, the threshold voltage of a MOS transistor varies by about ±0.2 V from a target value, so there is a drawback that overcurrent detection accuracy is poor.
そこで、この発明は、従来の欠点を解決し、検出精度の
良い過電流防止回路を実現することを目的とする゛。Therefore, it is an object of the present invention to solve the conventional drawbacks and realize an overcurrent prevention circuit with good detection accuracy.
上記問題点を解決するために、この発明では、過電流検
出用トランジスタにバイポーラ（Ｂ ｉ ｐ）トランジ
スタを用いる。In order to solve the above problems, the present invention uses a bipolar (B i p) transistor as the overcurrent detection transistor.
Ｂｉｐミルトランジスタ■は、ベース領域の不純物濃度
によりほぼ決定され、−ａ的に、ＭＯＳトランジスタの
しきい値電圧のバラツキに比べ、ベース・エミッタ間電
圧Ｖ０のバラツキの方が小さい。従って、ＶｌＫのバラ
ツキの小さいＢｉｐミルトランジスタが、過電流の検出
精度が高くなる。The Bip mill transistor (2) is almost determined by the impurity concentration of the base region, and -a-wise, the variation in the base-emitter voltage V0 is smaller than the variation in the threshold voltage of the MOS transistor. Therefore, the Bip mill transistor with small variation in VlK has high overcurrent detection accuracy.
又、この発明では、通電７Ｎ検出用のＢｔｐｔ−ランジ
スタをＭＯＳトランジスタと同一工程で作ることも特徴
としている。Another feature of the present invention is that the Btpt-transistor for detecting 7N current is made in the same process as the MOS transistor.
以下に、この発明の実施例を、図面にもとすいて説明す
る。Embodiments of the present invention will be described below with reference to the drawings.
第１図に定電圧発生回路を示すが、１はコンパレータで
２で発生させる基準電圧と抵抗Ｒ１，Ｒ，により分圧さ
れた出力電圧とを比較し、出力電圧が常に一定の値とな
るように、出力トランジスタＱ４のゲート電圧を与える
ｅＱＩは過電流検出トランジスタＱ２がオンしたときに
出力トランジスタＱ４のゲート電圧をＶＩＮレベルに引
き上げ、Ｑ４の過電流を防止する。又、Ｒ，は通常動作
時Ｑ、のゲート電圧としてＶＩＮを与え、Ｑ、をオフさ
せるための抵抗である。Figure 1 shows a constant voltage generation circuit. Comparator 1 compares the reference voltage generated by 2 with the output voltage divided by resistors R1 and R, so that the output voltage always remains at a constant value. Furthermore, eQI, which provides the gate voltage of the output transistor Q4, raises the gate voltage of the output transistor Q4 to the VIN level when the overcurrent detection transistor Q2 is turned on, thereby preventing overcurrent of the output transistor Q4. Further, R is a resistor for applying VIN as the gate voltage of Q during normal operation and turning off Q.
Ｑ３． ＲｘはＱ２と供に、この発明の主構成要素で過
電流検出回路を形成し、次の様に動作する。Ｑ、は出力
トランジスタＱ４と並列にＶＩＮ−Ｖ。Ｕ７間に接続さ
れたトランジスタで、Ｑ４に比べ１０分の１程度の電流
駆動能力を持つ、ここで、ＶＯＵアが何らかの原因でＧ
ＮＤに短絡されると、出力トランジスタＱ９に過大な電
流が流れ破壊する危険性がある。Q3. Rx and Q2 are the main components of the present invention and form an overcurrent detection circuit, which operates as follows. Q, is VIN-V in parallel with output transistor Q4. The transistor connected between U7 has a current driving capacity of about one-tenth that of Q4.
If it is short-circuited to ND, there is a risk that an excessive current will flow through the output transistor Q9 and cause it to be destroyed.
この時、出力トランジスタＱ４と並列接続された０゜の
電流も増加し、抵抗Ｒ，の電圧降下がＢｉｐトランジス
タＱ２のＶ□より大きくなりＱ２がオンする。At this time, the 0° current connected in parallel with the output transistor Q4 also increases, and the voltage drop across the resistor R becomes larger than V□ of the Bip transistor Q2, turning on Q2.
その結果、Ｑｌがオンとなり、出力トランジスタΩ。As a result, Ql turns on and the output transistor Ω.
のゲート電圧をＶＩＮに引き上げ、Ｑ、をオフさせる。The gate voltage of Q is raised to VIN, and Q is turned off.
この様にして、出力の過電流が流れるのを防止するが、
Ｑ！のオンレベルのバラツキが過電流の検出精度に影響
を与える。従来、ＭＯ３Ｉ−ランジスクを用いた定電圧
発生装置では、Ｑ２にもＭＯＳトランジスタを用いてい
たため過電流の検出精度が悪かった。この発明では、Ｑ
、にＢｉｐトランジスタを用いることにより、従来より
も２倍以上の過電流の検出精度を高めることが可能とな
る。In this way, the output overcurrent is prevented from flowing, but
Q! Variations in the on-level of the circuit affect the overcurrent detection accuracy. Conventionally, in a constant voltage generator using MO3I-RANDISC, a MOS transistor was also used for Q2, so the overcurrent detection accuracy was poor. In this invention, Q
By using Bip transistors in , it is possible to increase the overcurrent detection accuracy by more than twice that of the conventional method.
第２図に、この発明に用いたＱ８の断面構造を示すが、
ベースのＰ−領域はＮＭＯ５のＰ ｗａｔｔと又、エ
ミッタ及びコレクタのＮ′領領域同じくＮＭＯ３のソー
ス及びドレインのＮｏ と同時に作ることができ、通常
のＣＭＯＳプロセスでＢｉｐトランジスタを実現できる
。Figure 2 shows the cross-sectional structure of Q8 used in this invention.
The base P- region can be formed at the same time as the Pwatt of NMO5 and the source and drain No of NMO3 as well as the emitter and collector N' regions, and a Bip transistor can be realized by a normal CMOS process.
この発明は、以上説明したように、過電流検出トランジ
スタにバラツキの小さいＢｔｐトランジスタを用いるこ
とにより、過電流の検出精度を高くすると同時に、前記
Ｂｉｐミルトランジスタ常のＣＭＯＳプロセスで容易に
実現できるという効果がある。As explained above, the present invention has the advantage that, by using a Btp transistor with small variations as an overcurrent detection transistor, the overcurrent detection accuracy is increased, and at the same time, the Bip mill transistor can be easily realized using the usual CMOS process. There is.
第１図は本発明の過電流防止回路図で、第２図はバイポ
ーラトランジスタ０□の断面図である。
ｌ・・・・・・コンパレータ
２・・・・・・基準電圧発生部
ＱＩ、Ｑ３＋ Ｑａ・・ＭＯＳ トラフ’；ス９Ｑ８
・・・・・ＢｉｐトランジスタＲ１−４・・・・・抵
抗
以上FIG. 1 is a diagram of an overcurrent prevention circuit according to the present invention, and FIG. 2 is a cross-sectional view of a bipolar transistor 0□. l...Comparator 2...Reference voltage generation section QI, Q3+ Qa...MOS trough';S9Q8
...Bip transistor R1-4...Resistance or more
Claims (2)
、前記定電圧発生装置を保護するために設けられた出力
電流制限回路において、過電流検出にバイポーラトラン
ジスタを用いたことを特徴とする過電流防止回路。(1) A bipolar transistor is used for overcurrent detection in an output current limiting circuit provided to protect the constant voltage generator when an excessive current flows through the output of the constant voltage generator. Overcurrent prevention circuit.
スタ以外のトランジスタをＭＯＳトランジスタで構成し
た特許請求の範囲第１項記載の過電流防止回路。(2) The overcurrent prevention circuit according to claim 1, wherein transistors other than the bipolar transistor in the constant voltage generator are constructed with MOS transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14362587A JPS63307511A (en) | 1987-06-09 | 1987-06-09 | Overcurrent preventing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14362587A JPS63307511A (en) | 1987-06-09 | 1987-06-09 | Overcurrent preventing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63307511A true JPS63307511A (en) | 1988-12-15 |
Family
ID=15343104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14362587A Pending JPS63307511A (en) | 1987-06-09 | 1987-06-09 | Overcurrent preventing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63307511A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02189608A (en) * | 1989-01-18 | 1990-07-25 | Seiko Instr Inc | Voltage control circuit |
| JP2002318625A (en) * | 2001-04-19 | 2002-10-31 | Seiko Instruments Inc | Voltage control circuit |
-
1987
- 1987-06-09 JP JP14362587A patent/JPS63307511A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02189608A (en) * | 1989-01-18 | 1990-07-25 | Seiko Instr Inc | Voltage control circuit |
| JPH0774976B2 (en) * | 1989-01-18 | 1995-08-09 | セイコー電子工業株式会社 | Voltage control circuit |
| JP2002318625A (en) * | 2001-04-19 | 2002-10-31 | Seiko Instruments Inc | Voltage control circuit |
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