JPS63305594A - Manufacture of multilayer printed circuit board - Google Patents
Manufacture of multilayer printed circuit boardInfo
- Publication number
- JPS63305594A JPS63305594A JP13988587A JP13988587A JPS63305594A JP S63305594 A JPS63305594 A JP S63305594A JP 13988587 A JP13988587 A JP 13988587A JP 13988587 A JP13988587 A JP 13988587A JP S63305594 A JPS63305594 A JP S63305594A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- circuit board
- printed circuit
- circuit
- weld
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 238000003466 welding Methods 0.000 claims abstract description 17
- 239000011888 foil Substances 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 6
- 238000000465 moulding Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 12
- 239000011889 copper foil Substances 0.000 abstract description 11
- 239000010410 layer Substances 0.000 abstract 7
- 239000011229 interlayer Substances 0.000 abstract 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 7
- 229910000906 Bronze Inorganic materials 0.000 description 6
- 239000010974 bronze Substances 0.000 description 6
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 6
- 238000003825 pressing Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229920001342 Bakelite® Polymers 0.000 description 1
- 240000001548 Camellia japonica Species 0.000 description 1
- 235000018597 common camellia Nutrition 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229920003217 poly(methylsilsesquioxane) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 235000011962 puddings Nutrition 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層プリント回路板を製造する方法に５層以上
の多層プリント回路板を生産性よく多層成形プレスする
方法を提供しようとするものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention aims to provide a method for manufacturing multilayer printed circuit boards, in which a multilayer printed circuit board having five or more layers is formed and pressed with high productivity. be.
従来多層プリント回路板を製造する方法では各層基板を
プレス時に成形治具とガイドビンを用いて位置を合わせ
て多層プレスする方法と、多層プレスをした後に座ぐっ
てガイドマークを露出せしめる方法の２通りがある。Conventionally, there are two methods for manufacturing multilayer printed circuit boards: one is to align each layer board using a forming jig and guide bins during pressing, and the other is to sit down after multilayer pressing and expose the guide marks. There is.
前者の方法では、多層プレス時に樹脂フローとプレス圧
力で内層材の孔が変形し、層ずれが発生する欠点がある
。The former method has the disadvantage that the holes in the inner layer material are deformed by the resin flow and press pressure during multilayer pressing, resulting in layer displacement.
後者の方法では、五層以上のプリン）Ｗではプレスが２
回以上行なわなければならず、それだけ工数がかかり生
産性が低（なっている。In the latter method, if the pudding has five or more layers)
It has to be done more than once, which takes more man-hours and lowers productivity.
これらの欠点を改良した方法として、複数の同市
路層間を位置ケ１し、はんだ等の低融点金属で高周６１
誘導加熱などにより）容接して固定し、その後１才
多−プレスする方法がある。この方法緬溶接は容易であ
るが、多層プレス時微小な位置ずれが生じ最近の高密度
化に十分対応できなくなっている。As a method to improve these shortcomings, the position between multiple same road layers is 1, and a high circumference 61 is used with low melting point metal such as solder.
There is a method of contacting and fixing (by induction heating, etc.) and then pressing for a while. Although this method of welding is easy, minute positional deviations occur during multilayer pressing, making it unable to adequately cope with the recent increase in density.
本発明は各回路層間の位置ずれを防止すると共に、作業
性、生産性の向上を図りうる方法を提供するものである
。The present invention provides a method that can prevent misalignment between circuit layers and improve workability and productivity.
〔発明の構成］
本発明は、多層プリント板材料を、多層成形前に各回路
層間を位置合わせし、回路金属箔と溶接可能な金属（Ａ
）で各回路層間を溶接させた後、多層プレスする多層プ
リント回路板の製造方法において、前記各回路層間に前
記金属（Ａ）を配置し、一方の回路層周辺に設けた穴を
通して、前記金属（Ａ） と他方の回路層の金属箔＜
Ｃ＞ とを溶接し、また、他方の回路層に設けた穴を通
して、前記金属 （Ａ） と前記一方の回路層の金属箔
（Ｂ） とを溶接することにより、前記各回路層間を
溶接することを特徴とする多層プリント回路板の製造方
法、を要旨とするものである。[Structure of the Invention] The present invention aligns each circuit layer of a multilayer printed board material before multilayer molding, and prepares a metal (A) that can be welded to a circuit metal foil.
), in which the metal (A) is placed between each circuit layer, and the metal (A) is inserted through a hole provided around one of the circuit layers, and the metal (A) and the metal foil of the other circuit layer
C> and also weld the metal (A) and the metal foil (B) of the one circuit layer through a hole provided in the other circuit layer, thereby welding the respective circuit layers. The gist of the present invention is a method for manufacturing a multilayer printed circuit board characterized by the following.
回路用の金属箔は主として銅が使用されているが、銅箔
同士の溶接は困難である。また、溶接される回路板は両
面に銅箔を張った構造となっているため、この回路板を
２枚重ねた場合、内側の銅箔同士の溶接は電極を取付け
ることも困難である。Copper is mainly used as metal foil for circuits, but it is difficult to weld copper foils together. Further, since the circuit board to be welded has a structure in which copper foil is applied on both sides, when two circuit boards are stacked, it is difficult to weld the inner copper foils together and attach electrodes.
このため、２枚の回路板の内側の銅箔の間に、銅箔と溶
接可能な金属箔をはさみ、電気溶接を行う。For this purpose, a metal foil that can be welded to the copper foil is sandwiched between the copper foils on the inside of the two circuit boards, and electric welding is performed.
ところが、この電気溶接は回路板の絶縁層のためそのま
までは行うことができない。However, this electric welding cannot be performed as is because of the insulating layer of the circuit board.
そこで、溶接部で、一方の回路板に貫通穴を設けておき
、その穴を通して、他方の回路板の銅箔と溶接用金属箔
とを溶接する。同様にして前記他方の回路板に設けた貫
通穴を通して前記一方の回′ｉａＩ板と溶接用金属とを
溶接する。Therefore, a through hole is provided in one circuit board at the welding part, and the copper foil of the other circuit board and the welding metal foil are welded through the hole. Similarly, the one circuit board and the welding metal are welded through the through hole provided in the other circuit board.
このようにして、溶接用金属を介して両回路基板が接合
固定される。In this way, both circuit boards are joined and fixed via the welding metal.
銅箔の溶接においては、溶接用金属として椿リン青銅が
好ましくは使用され、その厚さは回路板間に使用される
プリプレグの成形後の厚さと同じにするのが好ましい。In welding copper foil, camellia phosphor bronze is preferably used as the welding metal, and its thickness is preferably the same as the formed thickness of the prepreg used between the circuit boards.
以下、本発明を図面に基いて具体的に説明する。Hereinafter, the present invention will be specifically explained based on the drawings.
第１図に示すように、位置合わせ用の孔を有する２枚の
ガラス・エポキシ樹脂両面プリント回路板（＋）、 （
２）の間にプリプレグ（３）と溶接用リン青銅箔（Ａ）
をはさみ、位置合わせ治具０ωにセットする。As shown in Figure 1, two glass/epoxy resin double-sided printed circuit boards (+) with holes for alignment,
Between 2) prepreg (3) and phosphor bronze foil for welding (A)
Scissor and set the positioning jig to 0ω.
両面プリント回路板（１）、 （２）は第２図に示すよ
うに、リン青銅ＦＭ（Ａ） と溶接する部分に対向す
る部分に穴（５１，（６１を設けておく。As shown in FIG. 2, the double-sided printed circuit boards (1) and (2) are provided with holes (51 and 61) in the portions opposite to the portions to be welded to the phosphor bronze FM (A).
次に、第３図のように、この穴（５）を通して、スポッ
ト溶接機（Ｓ）によりりん青銅箔（Ａ） と穴と反対
側の回路板（２）の銅箔（Ｃ） とをスポット溶接す
る。更に、同様にして穴（６）を通して、リン青ｍ７ｒ
３（Ａ） ト回１？８板（１）＜７１１１１！ｆ３（
Ｂ） トヲスホｙ トた４層のプリント回路板（］）
、 （２１を接合固定することができる。Next, as shown in Figure 3, through this hole (5), spot the phosphor bronze foil (A) and the copper foil (C) of the circuit board (2) on the opposite side of the hole using a spot welder (S). Weld. Furthermore, in the same way, pass through the hole (6) and add phosphor blue m7r.
3(A) To times 1?8 boards (1) <71111! f3(
B) Four-layer printed circuit board (])
, (21 can be joined and fixed.
次いで位置合わせ治具ＱＯ）からこの仮止めされた４層
プリント回路板をはずし、第４図の様に上下にプリプレ
グ（３）とｆＲｆｔｓ （７） （８）を重ねて加熱、
加圧して６層プリント回路ＦＪ、（８）が得られる（第
５図）、。Next, remove this temporarily fixed four-layer printed circuit board from the positioning jig (QO), stack the prepreg (3) and fRfts (7) (8) on top and bottom as shown in Figure 4, and heat them.
By applying pressure, a six-layer printed circuit FJ (8) is obtained (FIG. 5).
この実施例では、６層プリント回路板の例を示したが、
７層以上の多層プリント回路板の場合もスポット溶接の
ための穴の位置を調整すれば、６層プリント回路板と同
様に製造することができる。In this example, an example of a 6-layer printed circuit board was shown, but
A multilayer printed circuit board with seven or more layers can be manufactured in the same way as a six-layer printed circuit board by adjusting the positions of the holes for spot welding.
〔実施例］
第１図〜第３図に示すように、厚さ０．４間の両面プリ
ント回路板（＋）１２）の間に硬化後の厚さが７０μｍ
のプリプレグ（３）と厚さ７０μ国のリン青銅箔（Ａ）
をはさみ、２枚の両面プリント回路板とリン青銅とをス
ポット溶接により固定した。以下、第４図のようにして
６層プリント回路板を成形した。[Example] As shown in FIGS. 1 to 3, the thickness after curing is 70 μm between the double-sided printed circuit board (+) 12) with a thickness of 0.4 μm.
prepreg (3) and 70μ thick phosphor bronze foil (A)
The two double-sided printed circuit boards and the phosphor bronze were fixed by spot welding. Thereafter, a six-layer printed circuit board was molded as shown in FIG.
比較例として、溶接金属としてはんだを用い、高周波加
熱により溶接をし、その他は実梅例と同様にして６層プ
リント回路板を得た。As a comparative example, a 6-layer printed circuit board was obtained using solder as the welding metal and welding by high-frequency heating, but in the same manner as in the actual example.
得られた６Ｎプリント回路板の内層回路の位置ずれを測
定し結果を示す。The positional deviation of the inner layer circuit of the obtained 6N printed circuit board was measured and the results are shown.
以上のように、本発明により得られた多層プリント回Ｉ
Ｂ板は内層の眉間位Ｗ精度が極めて優れており、多層化
成形において今成形性等も従来の方法と同等以上である
。As described above, the multilayer printing cycle I obtained by the present invention
Board B has extremely excellent glabella position W accuracy of the inner layer, and its moldability in multilayer molding is also at least equivalent to conventional methods.
各図は本発明乃多層プリント回路板を製造する工程の一
例を示すものである。
第１図は各素材を位置合わせ治具にセ・７トした状態の
断面図、第２図は第１図のＸ−Ｘ断面図、第３図は第２
図においてスポット溶接した状態の断面図、第４図は多
層化成形する前の状態の断面図、第５図は得られた６Ｎ
プリント回路板の断面図である。
特許出願人 住友ベークライト株式会社第３図
第゛５図Each figure shows an example of a process for manufacturing a multilayer printed circuit board according to the present invention. Figure 1 is a cross-sectional view of each material set in the positioning jig, Figure 2 is a cross-sectional view taken along line XX in Figure 1, and Figure 3 is a cross-sectional view of the
In the figure, a cross-sectional view of the spot welded state, Fig. 4 is a cross-sectional view of the state before multilayer molding, and Fig. 5 is a cross-sectional view of the obtained 6N.
FIG. 3 is a cross-sectional view of a printed circuit board. Patent applicant Sumitomo Bakelite Co., Ltd. Figure 3 Figure 5
Claims (1)
合わせし、回路金属箔と溶接可能な金属（Ａ）で各回路
層間を溶接させた後、多層プレスする多層プリント回路
板の製造方法において、前記各回路層間に前記金属（Ａ
）を配置し、一方の回路層周辺に設けた穴を通して、前
記金属（Ａ）と他方の回路層の金属箔（Ｃ）とを溶接し
、また、他方の回路層に設けた穴を通して、前記金属（
Ａ）と前記一方の回路層の金属箔（Ｂ）とを溶接するこ
とにより、前記各回路層間を溶接することを特徴とする
多層プリン回路板の製造方法。In a method for manufacturing a multilayer printed circuit board, in which a multilayer printed circuit board material is aligned between each circuit layer before multilayer molding, welded between each circuit layer with a circuit metal foil and a weldable metal (A), and then multilayer pressed. , the metal (A
), the metal (A) and the metal foil (C) of the other circuit layer are welded through the hole provided around one circuit layer, and the metal foil (C) of the other circuit layer is welded through the hole provided around the other circuit layer. metal(
A method for manufacturing a multilayer printed circuit board, characterized in that the circuit layers are welded by welding the metal foil (B) of the one circuit layer and the metal foil (B) of the one circuit layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13988587A JPS63305594A (en) | 1987-06-05 | 1987-06-05 | Manufacture of multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13988587A JPS63305594A (en) | 1987-06-05 | 1987-06-05 | Manufacture of multilayer printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63305594A true JPS63305594A (en) | 1988-12-13 |
Family
ID=15255857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13988587A Pending JPS63305594A (en) | 1987-06-05 | 1987-06-05 | Manufacture of multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63305594A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04225298A (en) * | 1990-12-26 | 1992-08-14 | Risho Kogyo Co Ltd | Manufacture of board for multilayer printed-circuit |
| US5542175A (en) * | 1994-12-20 | 1996-08-06 | International Business Machines Corporation | Method of laminating and circuitizing substrates having openings therein |
| US5557843A (en) * | 1993-08-23 | 1996-09-24 | Parlex Corporation | Method of making a circuit board or layer thereof including semi-curing a second adhesive coated on a cured first adhesive |
| US6017410A (en) * | 1991-09-30 | 2000-01-25 | Baccini; Gisulfo | Method to anchor foils for green-tape circuits |
-
1987
- 1987-06-05 JP JP13988587A patent/JPS63305594A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04225298A (en) * | 1990-12-26 | 1992-08-14 | Risho Kogyo Co Ltd | Manufacture of board for multilayer printed-circuit |
| US6017410A (en) * | 1991-09-30 | 2000-01-25 | Baccini; Gisulfo | Method to anchor foils for green-tape circuits |
| US5557843A (en) * | 1993-08-23 | 1996-09-24 | Parlex Corporation | Method of making a circuit board or layer thereof including semi-curing a second adhesive coated on a cured first adhesive |
| US5542175A (en) * | 1994-12-20 | 1996-08-06 | International Business Machines Corporation | Method of laminating and circuitizing substrates having openings therein |
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