JPS6328341B2 - - Google Patents
Info
- Publication number
- JPS6328341B2 JPS6328341B2 JP55182148A JP18214880A JPS6328341B2 JP S6328341 B2 JPS6328341 B2 JP S6328341B2 JP 55182148 A JP55182148 A JP 55182148A JP 18214880 A JP18214880 A JP 18214880A JP S6328341 B2 JPS6328341 B2 JP S6328341B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- insulating film
- resistance element
- film
- silicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 239000012535 impurity Substances 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims 1
- 239000013078 crystal Substances 0.000 description 16
- 150000002500 ions Chemical class 0.000 description 13
- 239000000758 substrate Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法に関し、特に
半導体集積回路素子における抵抗素子の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a resistive element in a semiconductor integrated circuit element.
従来、半導体集積回路素子において、多結晶シ
リコンの高抵抗素子を形成する方法は、以下のよ
うなものであつた。即ち、基板上に酸化シリコン
膜を形成し、その上に、減圧CVD法により、多
結晶シリコン層を形成する。次に、この多結晶シ
リコン層に、As+などの不純物イオンを打込み、
不純物ドープを行なう。次に、イオン打込みによ
つて、結晶欠陥の生じた多結晶シリコンを回復さ
せるとともに注入されたイオンを活性化するため
に熱処理によるアニールを行なう。このような多
結晶シリコン層を用いて基板上に抵抗素子を形成
する。 Conventionally, methods for forming high resistance elements of polycrystalline silicon in semiconductor integrated circuit devices have been as follows. That is, a silicon oxide film is formed on a substrate, and a polycrystalline silicon layer is formed thereon by low pressure CVD. Next, impurity ions such as As + are implanted into this polycrystalline silicon layer.
Perform impurity doping. Next, ion implantation is performed to recover the polycrystalline silicon in which crystal defects have occurred, and annealing is performed by heat treatment in order to activate the implanted ions. A resistance element is formed on a substrate using such a polycrystalline silicon layer.
以上のような従来方法でシート抵抗値が10〜数
10（ＧΩ／□）の高抵抗素子を形成する場合抵抗
値を精密に制御することは、非常に困難であり、
その再現性が悪いという問題があつた。例えば、
第１図に示すようにシート抵抗値の目的値10〜数
10（ＧΩ／□）に対し、単位面積に同一のイオン
注入量で、製造した４ロツトの集積回路素子間で
その最終的な高抵抗素子のシート抵抗値を比較す
ると、同一ロツト内では±20〜30％のバラツキだ
が、異なるロツトとの間では、最大で３桁ものバ
ラツキが生じていた。このような状態では、量産
化する際に製造ロツトが異なることによつて、素
子のシート抵抗値が、大きく変化してしまうこと
になり、一定の性能を持つ製品を、安定供給でき
ないという問題がある。 With the conventional method as above, the sheet resistance value can be reduced from 10 to several
When forming a high resistance element of 10 (GΩ/□), it is extremely difficult to precisely control the resistance value.
There was a problem with poor reproducibility. for example,
As shown in Figure 1, the objective value of the sheet resistance value is 10 to a number.
10 (GΩ/□), when comparing the sheet resistance value of the final high-resistance element among four lots of integrated circuit elements manufactured with the same ion implantation amount per unit area, it is ±20 within the same lot. Although the variation was ~30%, there was a variation of up to three orders of magnitude between different lots. In such a situation, the sheet resistance value of the element will vary greatly due to differences in manufacturing lots during mass production, resulting in the problem of not being able to stably supply products with constant performance. be.
本発明は、以上のような従来技術の問題点を改
善し抵抗値の制御が精度よく行なえて、その再現
性のよい高抵抗素子を形成する方法を提供するこ
とを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a high resistance element that can improve the problems of the prior art as described above, and can control the resistance value with high accuracy and has good reproducibility.
本発明では、基板上に、絶縁膜を形成し、その
絶縁膜上に減圧CVD法で多結晶シリコン膜を被
着させる。その後、その多結晶シリコン膜をまず
熱処理してアニールを行なつた後に、不純物イオ
ン注入を行なう。次に、多結晶シリコンの格子欠
陥回復と、不純物イオンの活性化のために再び熱
処理してアニールを行なう。このような構成の製
造工程をとることにより、制御し易く、再現性の
よい抵抗値を持つ高抵抗素子が、絶縁膜上に形成
できる。 In the present invention, an insulating film is formed on a substrate, and a polycrystalline silicon film is deposited on the insulating film by low pressure CVD. Thereafter, the polycrystalline silicon film is first heat-treated and annealed, and then impurity ions are implanted. Next, heat treatment is performed again to recover lattice defects in polycrystalline silicon and to activate impurity ions. By employing a manufacturing process with such a configuration, a high resistance element that is easy to control and has a resistance value with good reproducibility can be formed on the insulating film.
それは、以下のような考察に基づくものであ
る。即ち第２図に示すように、多結晶シリコン中
の結晶粒径は不純物イオン注入のドーズ量特に
1013（ions／cm2）台においてほとんど変化せず1015
（ions／cm2）以上において顕著に粒径の変化があ
らわれる。 This is based on the following considerations. That is, as shown in Figure 2, the crystal grain size in polycrystalline silicon depends on the dose of impurity ion implantation, especially
10 13 (ions/cm 2 ) level with almost no change 10 15
(ions/cm 2 ) or more, a remarkable change in particle size appears.
また、絶縁膜上に多結晶シリコン膜を形成する
際には従来、一般に減圧CVD法を用いる。この
時、素子が置かれた気相成長装置内ではモノシラ
ンガスの流量や、温度や、真空度などを制御して
いる。しかし装置内の汚れや、大気の微少リーク
などの原因で条件が微妙に変化し、その都度推積
される平均的な結晶粒径にも変化を生じ、結局、
製造ロツトの違いによつて、平均的な結晶粒径の
バラツキが発生することになる。このバラツキを
制御することは、非常に困難である。しかも、こ
の製造ロツト間での平均的な結晶粒径のバラツキ
が、最終的な抵抗値のバラツキの主要な原因にな
つていると考えられる。すなわち、多結晶シリコ
ン膜に、打ち込まれた不純物イオンは、その後の
熱処理によつて結晶粒が成長すると同時にSi原子
と置換して、活性化されるが、多結晶シリコンの
結晶境界面の形状によつて活性化の程度が大きく
影響されるし、結晶粒の成長が同時に起こるため
不安定な状況におかれる。したがつて、結晶粒径
が異なると、結晶境界面の構造も異なり、結局、
抵抗値にも影響を与えることになる。しかし、不
純物を注入する前に、あらかじめ熱処理をしてお
くと、この際に、結晶粒が、成長してしまい全体
として結晶粒径がそろつてくる。その後で不純物
イオンを打込んで、再びアニールすれば、結晶境
界面の構造も単純化されておりもはや結晶粒の成
長も起こらないため安全な状態で不純物イオンの
活性化ができる。このようにドープされた不純物
が常に安定して活性化できれば、抵抗値の制御が
容易であり、再現性のよい高抵抗素子が得られる
ことになる。 Furthermore, when forming a polycrystalline silicon film on an insulating film, conventionally, a low pressure CVD method is generally used. At this time, the flow rate of monosilane gas, temperature, degree of vacuum, etc. are controlled in the vapor phase growth apparatus in which the element is placed. However, the conditions change slightly due to dirt in the equipment, minute leaks in the atmosphere, etc., and the estimated average crystal grain size changes each time.
Due to differences in production lots, variations in average crystal grain size occur. Controlling this variation is extremely difficult. Moreover, this variation in average crystal grain size between production lots is considered to be the main cause of variation in final resistance value. In other words, the impurity ions implanted into the polycrystalline silicon film are activated by replacing Si atoms at the same time as the crystal grains grow through subsequent heat treatment, but the shape of the crystal boundary surface of the polycrystalline silicon changes. As a result, the degree of activation is greatly affected, and crystal grain growth occurs simultaneously, resulting in an unstable situation. Therefore, when the crystal grain size differs, the structure of the crystal boundary surface also differs, and in the end,
This will also affect the resistance value. However, if heat treatment is performed before implanting impurities, the crystal grains will grow and the crystal grain size will become uniform as a whole. If impurity ions are then implanted and annealed again, the impurity ions can be activated in a safe state because the crystal boundary structure is simplified and crystal grains no longer grow. If the doped impurities can be activated in a stable manner at all times, the resistance value can be easily controlled and a high resistance element with good reproducibility can be obtained.
次に、本発明の一実施例を、図面を用いて詳細
に説明する。まず第３図ａのように一部にトラン
ジスタなどの機能素子が形成された半導体基板１
上に例えば熱酸化法により7500Å程度の熱酸化シ
リコン膜などからなる絶縁膜２を形成する。次
に、この絶縁膜２上に、例えば減圧CVD法を用
いて、モノシランガス中で約620℃で多結晶シリ
コン膜３を、3000Å程度に一様に堆積させる。次
に、この多結晶シリコン層３上に、例えばCVD
法によつて、酸化シリコン膜４を約3000Å被着さ
せる。そして900℃で10分間、多結晶シリコン膜
３を熱処理して、プリアニールを行なう。このプ
リアニールによつて、前述したように、結晶粒を
成長させ、粒径をそろえる。酸化シリコン膜４
は、このプリアニールの際に、ふん囲気として用
いる不活性ガスのN2や、周囲の不純物などが多
結晶シリコン膜３中に拡散されて抵抗値が変化す
るのを防止するために被着させてある。プリアニ
ールの温度や時間は、シリコン基板１に形成され
たトランジスターなどの機能素子で、ソース、ド
レーンの再拡散が起こらないようにするために、
900℃、10分が最適である。次に、酸化シリコン
膜４を、フツ化アンモン中で除去し、多結晶シリ
コン膜３の表面を露出してから、その表面に、
100KV、３×1013（ions／cm2）のAsイオンを注入
する。シート抵抗値の目的値は２〜５×109（Ω／
□）である。その後、写真蝕刻法によつて多結晶
シリコン層３の不必要な部分を硝酸などを用いて
エツチングして除去し、所定の形状にする。こう
して第３図ｂに示すように高抵抗素子部５を形成
する。ここで、全面に再びCVD法によつて、酸
化シリコン膜からなる絶縁膜６を被着させる。次
に、、N2などの不活性ガス中で900℃10分間で再
びアニールを行なう。この時、不純物イオンが活
性化され、結晶欠陥も回復する。しかし、結晶粒
の成長は再び起こらない。またこの際、絶縁膜６
は、基板表面の絶縁膜２と一体化する。 Next, one embodiment of the present invention will be described in detail using the drawings. First, as shown in FIG. 3a, a semiconductor substrate 1 has functional elements such as transistors formed in a part thereof.
An insulating film 2 made of a thermally oxidized silicon film or the like having a thickness of about 7500 Å is formed thereon by, for example, a thermal oxidation method. Next, on this insulating film 2, a polycrystalline silicon film 3 is uniformly deposited to a thickness of about 3000 Å in monosilane gas at about 620° C. using, for example, a low pressure CVD method. Next, on this polycrystalline silicon layer 3, for example, a CVD
A silicon oxide film 4 having a thickness of about 3000 Å is deposited by a method. Then, the polycrystalline silicon film 3 is heat-treated at 900° C. for 10 minutes to perform pre-annealing. By this pre-annealing, as described above, crystal grains are grown and the grain sizes are made uniform. Silicon oxide film 4
is deposited to prevent the inert gas N2 used as an atmosphere and surrounding impurities from diffusing into the polycrystalline silicon film 3 and changing the resistance value during this pre-annealing. . The temperature and time of pre-annealing are determined to prevent re-diffusion of sources and drains in functional elements such as transistors formed on the silicon substrate 1.
900℃, 10 minutes is optimal. Next, the silicon oxide film 4 is removed in ammonium fluoride to expose the surface of the polycrystalline silicon film 3.
As ions are implanted at 100 KV and 3×10 13 (ions/cm 2 ). The target value of sheet resistance value is 2 to 5×10 9 (Ω/
□). Then, by photolithography, unnecessary portions of the polycrystalline silicon layer 3 are removed by etching using nitric acid or the like to form a predetermined shape. In this way, the high resistance element portion 5 is formed as shown in FIG. 3b. Here, an insulating film 6 made of a silicon oxide film is deposited over the entire surface again by the CVD method. Next, annealing is performed again at 900°C for 10 minutes in an inert gas such as N2. At this time, impurity ions are activated and crystal defects are also recovered. However, grain growth does not occur again. Also, at this time, the insulating film 6
is integrated with the insulating film 2 on the surface of the substrate.
次に、第３図ｃに示すように高抵抗素子部５の
両端の絶縁膜６にエツチングによつてコンタクト
ホール７をあける。この部分にオーミツクコンタ
クト用にAsを高濃度に拡散して拡散層８を形成
する。次にAlを被着させ電極９を形成する。前
述したコンタクトホールへの拡散は、Al電極９
と高抵抗素子部５との電気的な接続をよくするた
めである。高抵抗素子部５は、Al電極９から、
基板上の他の素子部分と結合されている。 Next, as shown in FIG. 3c, contact holes 7 are formed in the insulating film 6 at both ends of the high resistance element section 5 by etching. In this portion, a diffusion layer 8 is formed by diffusing As at a high concentration for ohmic contact. Next, electrode 9 is formed by depositing Al. The above-mentioned diffusion into the contact hole is caused by the Al electrode 9
This is to improve the electrical connection between the high-resistance element section 5 and the high-resistance element section 5. The high resistance element section 5 is connected to the Al electrode 9,
It is connected to other element parts on the substrate.
以上のような工程で高抵抗素子を有する集積回
路素子を４ロツトにわたつて製造し、そのシート
抵抗値（Ω／□）を比較した結果第４図に示すよ
うに抵抗値は、１×109〜５×109（Ω／□）であ
り、従来の３桁のバラツキを、大巾に減少し、１
桁以内にすることが可能となつた。このように本
発明の製造方法によつて、抵抗値の制御性、再現
性のよい高抵抗体が形成できる。しかも工程は単
純であるから、量産化する際にも適しており、効
果も大きい。 Four lots of integrated circuit devices having high resistance elements were manufactured using the above process, and the sheet resistance values (Ω/□) were compared. As shown in Figure 4, the resistance value was 1×10 9 to 5×10 9 (Ω/□), which greatly reduces the conventional 3-digit variation to 1
It is now possible to reduce the number to within an order of magnitude. As described above, by the manufacturing method of the present invention, a high-resistance element with good controllability and reproducibility of resistance value can be formed. Moreover, since the process is simple, it is suitable for mass production and has great effects.
尚、上記実施例では、プリアニールを900℃10
分間行なつたが、これに限定されるものではな
く、ポストアニールが1000℃であれば、プリアニ
ールは1000゜が好ましい。 In the above example, pre-annealing was performed at 900℃10
Although the temperature is not limited to this, if the post-annealing temperature is 1000°C, the pre-annealing temperature is preferably 1000°C.
また、本実施例で用いた、シリコン基板は、絶
縁基板でもよく、SOS技術にも適用できる。ま
た、高抵抗素子と他の機能素子との接続は、高濃
度に不純物をドープした多結晶シリコンを用いて
もよい。この場合、多結晶シリコン層から、高抵
抗素子にする部分と接続部とを同時に形成し、ま
ず、接続部をSiO2などで被覆して前述したよう
な手順で高抵抗素子を形成した後、この高抵抗素
子部分をSiO2膜などで覆つて接続部に不純物イ
オンを高濃度に注入する。このようにすれば、
Al電極は不用であり、オーミツクコンタクト用
の拡散も必要ない。また、プリアニールする多結
晶シリコン層は、高抵抗体を製造する目的に限ら
ず、抵抗値の低い接続部分を形成する際にも用い
ることができ、この場合抵抗値の制御を精度よく
行なうことができる。 Further, the silicon substrate used in this example may be an insulating substrate, and can also be applied to SOS technology. Further, polycrystalline silicon doped with impurities at a high concentration may be used for connection between the high resistance element and other functional elements. In this case, the part to be made into a high resistance element and the connection part are simultaneously formed from the polycrystalline silicon layer, and the connection part is first coated with SiO 2 etc. to form the high resistance element using the procedure described above. This high-resistance element portion is covered with a SiO 2 film or the like, and impurity ions are implanted at a high concentration into the connection portion. If you do this,
No Al electrodes are required, and no diffusion is required for ohmic contact. Furthermore, pre-annealed polycrystalline silicon layers can be used not only for the purpose of manufacturing high-resistance elements, but also for forming low-resistance connecting parts, and in this case, it is possible to control the resistance value with high precision. can.
第１図は従来のドーズ量とシート抵抗値の関係
を示す図、第２図は、ドーズ量とグレインサイズ
の関係を示す図、第３図ａ〜ｃは本発明とするた
めの一実施例の製造工程の断面概略図、第４図は
本発明によるドーズ量とシート抵抗値の関係を示
す図である。図において、
１……半導体基板、２，４，６……絶縁膜、３
……多結晶シリコン膜、５……高抵抗素子部、７
……コンタクトホール、８……拡散層、９……電
極。
FIG. 1 is a diagram showing the conventional relationship between dose amount and sheet resistance value, FIG. 2 is a diagram showing the relationship between dose amount and grain size, and FIGS. 3 a to c are an example of the present invention. FIG. 4 is a schematic cross-sectional view of the manufacturing process of FIG. 4, and is a diagram showing the relationship between dose amount and sheet resistance value according to the present invention. In the figure, 1... semiconductor substrate, 2, 4, 6... insulating film, 3
...Polycrystalline silicon film, 5...High resistance element section, 7
...Contact hole, 8...Diffusion layer, 9...Electrode.
Claims (1)
程と、この多結晶シリコン膜上に絶縁膜を被着す
る工程と、前記多結晶シリコン膜を前記絶縁膜で
被覆された状態でプリアニールする工程と、前記
絶縁膜を除去し前記多結晶シリコン膜に所定の不
純物をドープする工程と、この不純物がドープさ
れた多結晶シリコン膜をアニールする工程とを具
備したことを特徴とする半導体抵抗素子の製造方
法。 ２ 多結晶シリコン膜に所定の不純物をドープす
る際に、抵抗素子を形成する部分以外を第２の絶
縁膜で被覆し、この第２の絶縁膜をマスクにして
前記不純物を低濃度にドープし、この第２の絶縁
膜を除去した後前記抵抗素子を形成する部分上に
第３の絶縁膜を形成し、この第３の絶縁膜をマス
クにして接続配線を形成する部分に前記不純物を
高濃度にドープしたことを特徴とする特許請求の
範囲第１項記載の半導体抵抗素子の製造方法。[Claims] 1. A step of forming a polycrystalline silicon film on an insulating material, a step of depositing an insulating film on the polycrystalline silicon film, and a step of covering the polycrystalline silicon film with the insulating film. The present invention is characterized by comprising the steps of: pre-annealing the polycrystalline silicon film in a pre-annealed state; removing the insulating film and doping the polycrystalline silicon film with a predetermined impurity; and annealing the polycrystalline silicon film doped with the impurity. A method for manufacturing a semiconductor resistance element. 2. When doping a polycrystalline silicon film with a predetermined impurity, cover the area other than the part where the resistance element is to be formed with a second insulating film, and use this second insulating film as a mask to dope the impurity at a low concentration. After removing this second insulating film, a third insulating film is formed on the part where the resistor element is to be formed, and using this third insulating film as a mask, the impurity is highly concentrated in the part where the connection wiring is to be formed. 2. The method of manufacturing a semiconductor resistance element according to claim 1, wherein the semiconductor resistance element is doped at a high concentration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55182148A JPS57106101A (en) | 1980-12-24 | 1980-12-24 | Method of producing semiconductor resistance element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55182148A JPS57106101A (en) | 1980-12-24 | 1980-12-24 | Method of producing semiconductor resistance element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57106101A JPS57106101A (en) | 1982-07-01 |
| JPS6328341B2 true JPS6328341B2 (en) | 1988-06-08 |
Family
ID=16113193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55182148A Granted JPS57106101A (en) | 1980-12-24 | 1980-12-24 | Method of producing semiconductor resistance element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57106101A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60116160A (en) * | 1983-11-29 | 1985-06-22 | Sony Corp | Manufacture of semiconductor device |
| EP2435120B1 (en) | 2009-05-29 | 2019-08-21 | ResMed Pty Ltd | Nasal mask system |
-
1980
- 1980-12-24 JP JP55182148A patent/JPS57106101A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57106101A (en) | 1982-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0145926B1 (en) | Polysilicon resistors compensated with double ion-implantation | |
| US4879253A (en) | Method for fabricating a semiconductor device using a BPSG layer containing high concentrations of phosphorus and boron | |
| JPS5922380B2 (en) | Handout Taisoshino Seizouhouhou | |
| JPS6328341B2 (en) | ||
| US5382549A (en) | Method of manufacturing polycrystalline silicon having columnar orientation | |
| JP2953396B2 (en) | Method for manufacturing silicon thin film conductive element | |
| JPS6125209B2 (en) | ||
| JP2830720B2 (en) | Method for manufacturing semiconductor device | |
| JPS5891670A (en) | Manufacture of semiconductor device | |
| JP2669611B2 (en) | Method for manufacturing semiconductor device | |
| KR910006088B1 (en) | Manufacturing method of semiconductor with high resistance film | |
| JPH088205A (en) | Manufacture of semiconductor element | |
| JP2747919B2 (en) | Method for manufacturing semiconductor integrated circuit having buried diffusion layer | |
| JPH0127581B2 (en) | ||
| JPH0587992B2 (en) | ||
| JPH01268047A (en) | Formation of polysilicon resistor | |
| JP2876414B2 (en) | Manufacturing method of diffusion resistance element | |
| JP3147930B2 (en) | Method for manufacturing polycrystalline silicon high resistance element | |
| JPH0682787B2 (en) | Method for manufacturing semiconductor device | |
| JP2002043523A (en) | Semiconductor device and its manufacturing method | |
| JPH025298B2 (en) | ||
| JPS63151064A (en) | Manufacture of semiconductor device | |
| JPS6311785B2 (en) | ||
| JPH01165156A (en) | Semiconductor device | |
| JPS6218021A (en) | Manufacture of semiconductor device |