JPS6325950A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6325950A JPS6325950A JP16910886A JP16910886A JPS6325950A JP S6325950 A JPS6325950 A JP S6325950A JP 16910886 A JP16910886 A JP 16910886A JP 16910886 A JP16910886 A JP 16910886A JP S6325950 A JPS6325950 A JP S6325950A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- metal
- insulating film
- forming
- electroless plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000007772 electroless plating Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000007747 plating Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 abstract description 22
- 239000011229 interlayer Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 abstract 5
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
Landscapes
- Chemically Coating (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に半導体装置
における配線層なかんずく多層配線の形成方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming wiring layers, particularly multilayer wiring, in a semiconductor device.
半導体装置とくに集積回路（ＩＣ）においは能動素子の
間を電気的に結合するために多層配線が必要である。多
層配線は下層（第１層目）の配線。Semiconductor devices, particularly integrated circuits (ICs), require multilayer wiring to electrically connect active elements. Multilayer wiring is the lower layer (first layer) wiring.
電極を形成したあと層間絶縁膜を被着せしめ、所定の場
所に貫通孔（スルーホール）を形成し、上層に第２層配
線線を形成すると同時にスルーホールを金属で埋め、第
１層、第２層の電気的結合を達成するものである。多層
配線の歩留りはＩＣの歩留りを大きく左右するものであ
るが、その為の技術的ポイントとしては、（イ）スルー
ホール部での電気的結合の完全化と（ロ）配線切れ、特
に第２層配線の断線の防止である。このような観点から
言うと従来の多層配線技術は必ずしも完全とは言えない
。第２図は、従来の最も一般的な多層配線技術を説明す
、る為の半導体チップの断面図であり、第１層目の電極
１１．下層配線１２上に眉間絶縁膜１３が形成され、所
定の場所にスルーホール１４が設けられたあと、全面に
（スルーホール部も含む）金属を被着し、加工すること
により上層配線１５が形成されている。この方法では、
スルーホール部での金属の段差被覆性（ステップカバレ
ジ）の悪さにより、当該部での断線が生じ易い点である
。これを防ぐ方法としては、第３図（ａ）に示すように
、ホトレジストパターン１６をマスクにしてスルーホー
ルを開口し、次に第３図（ｂ）に示すように金属膜１７
を被着したのち不要の金属をリフトオフして、第３図に
示すようにスルーホール部に埋込金属を形成する方法が
有るが、この場合には、スルーホール開口時の層間絶縁
膜１３のサイドエツチングのため、埋込金属とスルーホ
ール側面の間に隙２０が生じ、その箇所で断線が起り易
い。After forming the electrodes, an interlayer insulating film is deposited, through holes are formed at predetermined locations, and the second layer wiring is formed on the upper layer. At the same time, the through holes are filled with metal, and the first layer and This achieves electrical coupling between the two layers. The yield of multilayer wiring greatly influences the yield of ICs, and the technical points for this are (a) perfecting the electrical connection at the through-hole section, and (b) preventing wire breakage, especially in the second This is to prevent disconnection of layer wiring. From this point of view, conventional multilayer wiring technology cannot necessarily be said to be perfect. FIG. 2 is a cross-sectional view of a semiconductor chip for explaining the most common conventional multilayer wiring technology. After forming the glabella insulating film 13 on the lower layer wiring 12 and providing through holes 14 at predetermined locations, the upper layer wiring 15 is formed by coating the entire surface (including the through hole portion) with metal and processing. has been done. in this way,
Due to the poor step coverage of the metal at the through-hole section, wire breakage is likely to occur at that section. To prevent this, as shown in FIG. 3(a), a through hole is opened using the photoresist pattern 16 as a mask, and then as shown in FIG. 3(b), a through hole is opened in the metal film 17.
There is a method of depositing the metal and then lifting off the unnecessary metal to form a buried metal in the through-hole part as shown in FIG. Due to the side etching, a gap 20 is created between the embedded metal and the side surface of the through hole, and disconnection is likely to occur at that location.
上述した従来の半導体装置の製造方法は、リフトオフ法
により絶縁膜に設けられたスルーホールを金属で埋込む
ため、埋込金属とスルーホール側面間に隙が生じ断線を
生じ易い欠点がある６本発明の目的は、スルーホール部
における断線の生じない半導体装置の製造方法を提供す
ることにある。In the conventional semiconductor device manufacturing method described above, the through-hole provided in the insulating film is filled with metal by the lift-off method, which has the disadvantage that a gap is created between the embedded metal and the side surface of the through-hole, which easily causes disconnection. SUMMARY OF THE INVENTION An object of the invention is to provide a method for manufacturing a semiconductor device that does not cause disconnection in a through-hole portion.
本発明の半導体装置の製造方法は、所定の導電領域を備
えた基板に絶縁膜を形成したのち前記絶縁膜を選択的に
除去して前記導電領域を露出させる貫通孔を設ける工程
と、前記導電領域の露出部に無電界めっき法により金属
をめっきして前記貫通孔を埋める金属充填部を形成する
工程と、前記金属充填部に接続された導電層を前記絶縁
股上に形成する工程を含むものである。The method for manufacturing a semiconductor device of the present invention includes the steps of forming an insulating film on a substrate having a predetermined conductive region, and then selectively removing the insulating film to provide a through hole to expose the conductive region; The method includes the steps of plating metal on the exposed portion of the region by electroless plating to form a metal filling portion that fills the through hole, and forming a conductive layer connected to the metal filling portion on the insulating crotch. .
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例の工程順に配
列した半導体チップの断面図である。FIGS. 1A to 1D are cross-sectional views of semiconductor chips arranged in the order of steps according to an embodiment of the present invention.
まず、第１図（ａ）に示すように、シリコンウェーハに
５ｉ０２膜（図示しない）をマスクにして所定の拡散を
行った状態の半導体基板１０の前述のＳ ｉ ０２膜上
に形成されたオーム性のＴ ｉ −Ａｕを表面に有する
電極１１及び下層配線１２を導電領域として形成したの
ち化学的気相成長法により厚か５０００人の５ｉ０２膜
を被着して層間絶縁膜１３を形成する。First, as shown in FIG. 1(a), an ohm film is formed on the aforementioned Si02 film of the semiconductor substrate 10 in which a predetermined diffusion is performed using a 5i02 film (not shown) as a mask on a silicon wafer. After forming an electrode 11 and a lower wiring 12 having a Ti-Au surface as a conductive region, an interlayer insulating film 13 is formed by depositing a 5000-thick 5i02 film by chemical vapor deposition.
次に、第１図（ｂ）に示すように、所定のホトレジスト
パターン１６を層間絶縁膜１３上に形成して、それをマ
スクとして、スルーホール（貫通孔）１４を形成する。Next, as shown in FIG. 1(b), a predetermined photoresist pattern 16 is formed on the interlayer insulating film 13, and using this as a mask, a through hole 14 is formed.
次に不要となったホトレジストを除去した後、第１図（
ｃ）に示すように、無電界Ｎｉメッキ液で、スルーホー
ル１４内の電極１１．下層配線１２に無電界メッキを施
し、スルーホール内をＮｉにより埋戻して金属充填部１
つを形成する。次に、第１図（ｄ）に示すようにＴｉ−
Ａｕから成る第２層配線金属を全面に被着せしめ、加工
することにより上層配線１５を形成すると、多層配線が
完成する。なお、この実施例においては、スルーホール
部に無電界Ｎｉめつきを施したが、実際には必ずしもＮ
ｉめつきである必要はなく、Ａｕ、Ａｇ等の無電界めっ
きであってもよい。また導電領域としてはＴｉ−Ａｕの
場合につき示したが、ＷＳｉ等の高融点金属でも、また
Ａ２でもよい。但し、その表面にＡｕ膜が被着されたＷ
Ｓ １−Ａｕ、ＡＪ？−Ａすとする方が、無電界めっき
の被着性に富み好しい。Next, after removing the unnecessary photoresist, as shown in Figure 1 (
As shown in c), the electrode 11. in the through hole 14 is coated with an electroless Ni plating solution. Electroless plating is applied to the lower layer wiring 12, and the inside of the through hole is backfilled with Ni to form the metal filling part 1.
form one. Next, as shown in FIG. 1(d), Ti-
When the upper layer wiring 15 is formed by depositing and processing a second layer wiring metal made of Au over the entire surface, the multilayer wiring is completed. In this example, the through-hole portions were plated with electroless Ni, but in reality, Ni plating is not necessarily required.
It is not necessary to use i-plating, and electroless plating of Au, Ag, etc. may be used. Further, although the case of Ti-Au is shown as the conductive region, it may be a high melting point metal such as WSi or A2. However, W with an Au film deposited on its surface
S1-Au, AJ? -A is preferable because it provides better adhesion for electroless plating.
また多層配線における眉間配線に限らず、半導体基板の
不純物領域にオーム電極を形成する場合に本発明を適用
してもよい。Further, the present invention is not limited to the glabella wiring in multilayer wiring, but may be applied to forming an ohmic electrode in an impurity region of a semiconductor substrate.
以上説明したように本発明は、無電界めっき法により貫
通孔を埋め戻して金属充填部を形成するので、容易に段
差部をなくし段差による断線をなくすことができ、半導
体装置の歩留り及び信頼性の向上がもたらされる。As explained above, the present invention uses electroless plating to backfill the through hole to form a metal-filled portion, so it is possible to easily eliminate the stepped portion and eliminate disconnections due to the stepped portion, thereby improving the yield and reliability of semiconductor devices. This results in an improvement in
第１図（ａ）〜（ｄ）は本発明の一実施例の工程順に配
列した半導体チップの断面図、第２図は従来の一般的な
多層配線技術を説明するための半導体チップの断面図、
第３図（ａ）〜（ｃ）は従来例であるリフトオフ法を説
明するための工程順に配列した半導体チップの断面図で
ある。
１０・・・半導体基板、１１・・・電極、１２・・・下
層配線、１３・・・層間絶縁膜、１４・・・スルーホー
ル、１５・・・上層配線、１６・・・ホトレジストパタ
ーン、１７・・・金属膜、１８・・・埋込金属、１９・
・・金属充填部、第１図FIGS. 1(a) to (d) are cross-sectional views of semiconductor chips arranged in the order of steps according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor chip for explaining conventional general multilayer wiring technology. ,
FIGS. 3(a) to 3(c) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the conventional lift-off method. DESCRIPTION OF SYMBOLS 10... Semiconductor substrate, 11... Electrode, 12... Lower layer wiring, 13... Interlayer insulating film, 14... Through hole, 15... Upper layer wiring, 16... Photoresist pattern, 17 ... Metal film, 18... Embedded metal, 19.
・・Metal filling part, Fig. 1
Claims (1)
前記絶縁膜を選択的に除去して前記導電領域を露出させ
る貫通孔を設ける工程と、前記導電領域の露出部に無電
界めっき法により金属をめっきして前記貫通孔を埋める
金属充填部を形成する工程と、前記金属充填部に接続さ
れた導電層を前記絶縁膜上に形成する工程を含むことを
特徴とする半導体装置の製造方法。A step of forming an insulating film on a substrate having a predetermined conductive region, and then selectively removing the insulating film to provide a through hole to expose the conductive region, and plating the exposed portion of the conductive region by electroless plating. A method for manufacturing a semiconductor device, comprising: forming a metal filling part to fill the through hole by plating metal; and forming a conductive layer connected to the metal filling part on the insulating film. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16910886A JPS6325950A (en) | 1986-07-17 | 1986-07-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16910886A JPS6325950A (en) | 1986-07-17 | 1986-07-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6325950A true JPS6325950A (en) | 1988-02-03 |
Family
ID=15880449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16910886A Pending JPS6325950A (en) | 1986-07-17 | 1986-07-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6325950A (en) |
-
1986
- 1986-07-17 JP JP16910886A patent/JPS6325950A/en active Pending
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