JPS63256001A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS63256001A JPS63256001A JP62089719A JP8971987A JPS63256001A JP S63256001 A JPS63256001 A JP S63256001A JP 62089719 A JP62089719 A JP 62089719A JP 8971987 A JP8971987 A JP 8971987A JP S63256001 A JPS63256001 A JP S63256001A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- bonding pad
- chip
- integrated circuit
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 claims description 7
- 239000010408 film Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910001120 nichrome Inorganic materials 0.000 claims 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 7
- 230000000644 propagated effect Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Junction Field-Effect Transistors (AREA)
- Non-Reversible Transmitting Devices (AREA)
- Logic Circuits (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
この発明は、ＧａＡｓ ＩＣの実装に係り、信号配線の
終端抵抗構成法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to the mounting of a GaAs IC, and relates to a method of configuring a termination resistor for signal wiring.
（従来の技術）
近年、情報処理機器の核となる集積回路は集積度の著し
い向上ばかりでなく、処理速度についてもＧａＡｓ Ｉ
Ｃ等の超高速素子の出現より高速化が図られつつある。(Prior art) In recent years, the integrated circuits that form the core of information processing equipment have not only significantly improved the degree of integration, but also have improved processing speed.
With the advent of ultra-high-speed elements such as C, speeds are being increased.
しかし、 ＧａＡｓ ＩＣのような超高速の論理集積回
路チップは、従来一般の集積回路チップと同様のパッケ
ージに実装すると誤動作を起こす、この誤動作の原因は
実装基板上の伝送線路と、集積回路チップの入力端子と
のインピーダンスの不整合によって生じる信号パルスの
多重反射の影響によるものである。However, when ultra-high-speed logic integrated circuit chips such as GaAs ICs are mounted in the same package as conventional integrated circuit chips, they malfunction.This malfunction is caused by the transmission lines on the mounting board and the integrated circuit chip. This is due to the effect of multiple reflections of signal pulses caused by impedance mismatch with the input terminal.
そこで、このような超高速動作の集積回路チップの実装
に際しては、第２図に示すように特性インピーダンス２
゜の伝送線路２１の端部、すなわち集積回路チップによ
り構成される論理回路２０の信号入力端子の直前にＩＺ
ｆｌｌ＝Ｒなる一端接地との終端抵抗２２を装荷してイ
ンピーダンス整合をとり、多重反射を防ぐ方法がとられ
ている。第３図はこのような終端抵抗を装荷した集積回
路実装基板の従来技術に基づく構成例である。Therefore, when mounting such an ultra-high-speed integrated circuit chip, the characteristic impedance 2 is required as shown in Figure 2.
IZ at the end of the transmission line 21 at
A method has been adopted in which impedance matching is achieved by loading a terminating resistor 22 with one end grounded, fll=R, to prevent multiple reflections. FIG. 3 shows an example of the configuration of an integrated circuit mounting board loaded with such a terminating resistor based on the prior art.
すなわち、絶縁性基体ｌｌ上に集積回路チップ１２をダ
イポンディングパッド１３を介して搭載し、基体１１上
に形成された配線パターン１５の一端に設けられたワイ
ヤポンディングパッド１４と集積回路チップ１２上の電
極パッドとをワイヤ１６により接続すると共に、第２図
の終端抵抗２２となる抵抗体１７を集積回路チップ１２
の実装位置に近接して形成している。ここで、抵抗体１
７は例えばダイポンディングパッド１３、ワイヤポンデ
ィングパッド１４および配線パターン１５の形成機、ス
パッタ法により所定の金属薄膜を被着せしめ、フォトリ
ソグラフィ技術を用いてパターンニングすることにより
形成される。この場合、抵抗体１７の一端は集積回路チ
ップ１２の所定の電極端子、すなわち信号入力端子に接
続されたワイヤポンディングパッド１４′ に接続され
、他端は別のワイヤポンディングパッド１８に接続され
る。抵抗体１７の抵抗値は５０Ω程゛度であ机この抵抗
体１７の形成後、ワイヤポンディングパッド１８とダイ
ポンディングパッド１３とをワイヤ１９により接続し、
抵抗体１７の接地をとる。しかしながら、第３図に示し
たような構造では、抵抗体１７およびワイヤ・ポンディ
ングパッド１８の配置のためのスペースが余分に必要と
なるため、実装効率が悪いという問題があった。That is, the integrated circuit chip 12 is mounted on the insulating substrate 11 via the die bonding pad 13, and the wire bonding pad 14 provided at one end of the wiring pattern 15 formed on the substrate 11 and the integrated circuit chip 12 are mounted on the insulating substrate 11 through the die bonding pad 13. A resistor 17 serving as the terminating resistor 22 in FIG.
It is formed close to the mounting position. Here, resistor 1
7 is formed, for example, by using a machine for forming die bonding pads 13, wire bonding pads 14, and wiring patterns 15, depositing a predetermined metal thin film by sputtering, and patterning using photolithography. In this case, one end of the resistor 17 is connected to a wire bonding pad 14' connected to a predetermined electrode terminal of the integrated circuit chip 12, that is, a signal input terminal, and the other end is connected to another wire bonding pad 18. Ru. The resistance value of the resistor 17 is about 50Ω. After forming the resistor 17, the wire bonding pad 18 and the die bonding pad 13 are connected by a wire 19.
The resistor 17 is grounded. However, the structure shown in FIG. 3 requires additional space for arranging the resistor 17 and the wire bonding pad 18, resulting in a problem of poor mounting efficiency.
また、終端抵抗はチップのポンディングパッドにできる
だけ近い所に形成することが電気特性上望ましいが、従
来はスペースの関係上、実装基板上のボンディング・パ
ッドからかなりはなれた所に形成せざるをえなかった。Additionally, it is desirable to form the terminating resistor as close as possible to the bonding pad of the chip in terms of electrical characteristics, but conventionally, due to space constraints, it had to be formed quite far away from the bonding pad on the mounting board. There wasn't.
（発明が解決しようとする問題点）
本発明は、上述した従来技術の問題点に鑑みなされたも
ので、実装効率の良い超高速素子の実装に適した集積回
路装置を提供することを目的とする。(Problems to be Solved by the Invention) The present invention has been made in view of the problems of the prior art described above, and an object of the present invention is to provide an integrated circuit device suitable for mounting ultra-high-speed elements with high mounting efficiency. do.
（問題点を解決するための手段）
本発明は、上記したような問題点を解決するため、実装
基板内の配線インピーダンスと整合した微細な終端抵抗
をＧａＡｇ ＩＣの信号が入力されるボンディング・パ
ッドとＩＣ内の一定電位を有する電源パターンの間に形
成し片方の端子はボンディング・パッドと、他方の端子
は電源パターンと接続せしめた構造を特徴とするもので
ある。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention installs a fine termination resistor that matches the wiring impedance in the mounting board at the bonding pad where the GaAg IC signal is input. It is characterized by a structure in which one terminal is connected to a bonding pad, and the other terminal is connected to a power supply pattern.
（作 用）
このように終端抵抗をＧａＡ＋ ＩＣチップ上に形成か
ることにより、実装基板上に抵抗体を形成するスペース
が不必要になり、実装密度が向上し、また、チップのボ
ンディング・パッドの最も近い所に抵抗体を形成できる
ため、電気的特性の向上も図ることができる。(Function) By forming the termination resistor on the GaA+ IC chip in this way, there is no need for space for forming the resistor on the mounting board, the packaging density is improved, and the bonding pad of the chip is Since the resistor can be formed at the closest location, electrical characteristics can also be improved.
（実施例）
以下１本発明の詳細について図面を用いて説明する。第
１図は１本発明の一実施例である６図に示すように、ア
ルミナ・セラミック、ガラス等からなる絶縁性基体（１
１）上にＧａＡｓ ＩＣチップ■がダイポンディングパ
ッド■を介して搭載されている。(Example) The details of the present invention will be explained below with reference to the drawings. Figure 1 shows one embodiment of the present invention. As shown in Figure 6, an insulating substrate (1) made of alumina, ceramic, glass, etc.
1) A GaAs IC chip (■) is mounted on the top via a die bonding pad (■).
また、ダイ・ボンディング・パッド■の周囲にワイヤ・
ボンディング・パッドに）が形成されている。Also, place wires around the die bonding pad.
) are formed on the bonding pads.
ワイヤ・ボンディング・パッド（へ）はワイヤ■により
ＧａＡｓ ＩＣチップ上の電極端子と接続されている。The wire bonding pads (to) are connected to electrode terminals on the GaAs IC chip by wires.
ＧａＡｇ ＩＣチップ■上には終端抵抗となるべき抵抗
体０が形成され、片方の電極は、チップ上の電極端子■
へ接続され、他方の電極は、一定電位を有する電源パタ
ーン■に接続されている。この抵抗０は、信号入力端子
四′にのみ形成され、実装基板の配線上を伝搬してきた
信号の反射を防止したため、インピーダンス不整合によ
る多重反射をなくすることができ、誤動作のない信頼性
の高い装置が得られる。A resistor 0, which should serve as a terminating resistor, is formed on the GaAg IC chip, and one electrode is connected to the electrode terminal on the chip.
The other electrode is connected to a power supply pattern (2) having a constant potential. This resistor 0 is formed only at the signal input terminal 4' and prevents the reflection of signals propagated on the wiring of the mounting board, eliminating multiple reflections due to impedance mismatch and ensuring reliability without malfunction. An expensive device can be obtained.
次に、この構成を得るためのプロセスについて説明する
。Next, a process for obtaining this configuration will be described.
ＧａＡｓウェハー上に、素子、配線、ボンディング・パ
ッドを形成した後、リフト・オフ法により、所望の形状
の抵抗を真空蒸着法もしくはスバッタ法で着膜形成する
。その後、抵抗体を各電極に接続するため、リフト・オ
フ法により配線（Ｔｌ／Ｐｔ／Ａｕ）を形成する。After forming elements, wiring, and bonding pads on a GaAs wafer, a lift-off method is used to deposit a resistor in a desired shape using a vacuum evaporation method or a sputtering method. Thereafter, wiring (Tl/Pt/Au) is formed by a lift-off method in order to connect the resistor to each electrode.
次に、抵抗体の保護膜（酸化シリコン、窒化シリコンな
ど）をスパッタ法、ＣＶＤ法等で形成し、フォト・リソ
・グラフィー技術により、抵抗体膜が全てカバーされる
ようバターニングする。パターニング後、抵抗体の安定
化のため２００℃〜３００℃でアニールする。Next, a protective film (silicon oxide, silicon nitride, etc.) for the resistor is formed by sputtering, CVD, etc., and patterned by photolithography so that the resistor film is completely covered. After patterning, annealing is performed at 200° C. to 300° C. to stabilize the resistor.
このような工程により、終端抵抗を形成することができ
る。Through such a process, a terminating resistor can be formed.
以上述べたように１本発明によれば、実装基板上に終端
抵抗を形成しないため、実装効率が著しく向上し、さら
に、抵抗体をチップの電極の最も近い所に形成できるた
め、電気的特性の向上も図ることができ、超高速素子の
実装方法として非常に有効である。As described above, according to the present invention, since no terminating resistor is formed on the mounting board, the mounting efficiency is significantly improved.Furthermore, since the resistor can be formed closest to the electrode of the chip, the electrical characteristics This method is also very effective as a method for mounting ultra-high-speed devices.
第１図は本発明の一実施例に係る集積■路実装基板の構
成を示す平面図、第２図は集積回路実装時の等価回路図
、第３図は従来の集積回路実装基の構成を示す平面図で
ある。
１・・・４６号配線
２・・・ダイポンディングパッド
３・・・集積回路チップ
４・・・ワイヤポンディングパッド
５・・・ワイヤ
６・・・終端抵抗
７・・・電源線
８・・・チップ側ワイヤ・ボンディング・パッド８′・
・・信号入力端子
１１・・・絶縁性基板
１５・・・配線
１７・・・抵抗体
代理人 弁理士 則 近 憲 佑
同 松山隻之
完
第１図
第 ２ 図
第 ３ 図Figure 1 is a plan view showing the configuration of an integrated circuit mounting board according to an embodiment of the present invention, Figure 2 is an equivalent circuit diagram when an integrated circuit is mounted, and Figure 3 is a diagram showing the configuration of a conventional integrated circuit mounting board. FIG. 1... No. 46 wiring 2... Die bonding pad 3... Integrated circuit chip 4... Wire bonding pad 5... Wire 6... Terminating resistor 7... Power line 8... Chip side wire bonding pad 8'
...Signal input terminal 11...Insulating board 15...Wiring 17...Resistor agent Patent attorney Noriyuki Ken Yudo Matsuyama Figure 1 Figure 2 Figure 3
Claims (4)
・パッドと前記ＩＣ内の一定電位を有する電源パターン
の間に薄膜抵抗体、及び薄膜抵抗体と該ボンディング・
パッド、該電パターンを接続する配線を有し、前記薄膜
抵抗体の抵抗値は、実装基板内配線の特性インピーダン
スと整合していることを特徴とする集積回路装置。(1) A thin film resistor is placed between the bonding pad to which a signal is input on the GaAa IC and a power supply pattern having a constant potential within the IC, and the thin film resistor and the bonding pad are connected to each other.
What is claimed is: 1. An integrated circuit device comprising a pad and wiring connecting the electrical pattern, wherein the resistance value of the thin film resistor matches the characteristic impedance of the wiring within the mounting board.
ルにより形成されたことを特徴とする特許請求の範囲第
１項記載の集積回路装置。(2) The integrated circuit device according to claim 1, wherein the thin film resistor is made of nichrome or tantalum nitride.
シリコンにより保護膜を形成したことを特徴とする特許
請求の範囲第１項記載の集積回路装置。(3) The integrated circuit device according to claim 1, wherein a protective film is formed on the thin film resistor using silicon nitride or silicon oxide.
ることを特徴とする特許請求の範囲第１項記載の集積回
路装置。(4) The integrated circuit device according to claim 1, wherein the resistance value of the thin film resistor is 20Ω to 120Ω.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62089719A JP2575382B2 (en) | 1987-04-14 | 1987-04-14 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62089719A JP2575382B2 (en) | 1987-04-14 | 1987-04-14 | Integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63256001A true JPS63256001A (en) | 1988-10-24 |
| JP2575382B2 JP2575382B2 (en) | 1997-01-22 |
Family
ID=13978576
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62089719A Expired - Fee Related JP2575382B2 (en) | 1987-04-14 | 1987-04-14 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2575382B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5140407A (en) * | 1989-12-25 | 1992-08-18 | Hitachi, Ltd. | Semiconductor integrated circuit devices |
| JP5752862B1 (en) * | 2014-06-18 | 2015-07-22 | ゼンテルジャパン株式会社 | Semiconductor circuit device and semiconductor memory system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57126159A (en) * | 1981-01-29 | 1982-08-05 | Nec Corp | Integrated circuit package |
| JPS6282807A (en) * | 1985-10-08 | 1987-04-16 | Nec Corp | Integrated circuit |
-
1987
- 1987-04-14 JP JP62089719A patent/JP2575382B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57126159A (en) * | 1981-01-29 | 1982-08-05 | Nec Corp | Integrated circuit package |
| JPS6282807A (en) * | 1985-10-08 | 1987-04-16 | Nec Corp | Integrated circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5140407A (en) * | 1989-12-25 | 1992-08-18 | Hitachi, Ltd. | Semiconductor integrated circuit devices |
| JP5752862B1 (en) * | 2014-06-18 | 2015-07-22 | ゼンテルジャパン株式会社 | Semiconductor circuit device and semiconductor memory system |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2575382B2 (en) | 1997-01-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |