JPS63244673A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS63244673A JPS63244673A JP62076167A JP7616787A JPS63244673A JP S63244673 A JPS63244673 A JP S63244673A JP 62076167 A JP62076167 A JP 62076167A JP 7616787 A JP7616787 A JP 7616787A JP S63244673 A JPS63244673 A JP S63244673A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- capacitor electrode
- insulating film
- substrate
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 239000003990 capacitor Substances 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 238000002955 isolation Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的コ
（産業上の利用分野）
本発明は、ＭＯＳトランジスタとＭＯＳキャパシタによ
りメモリセルを構成した半導体記憶装置に係わり、特に
素子分離用溝にキャパシタ電極を埋込んだ半導体記憶装
置に関する。Detailed Description of the Invention [Purpose of the Invention (Industrial Field of Application) The present invention relates to a semiconductor memory device in which a memory cell is constituted by a MOS transistor and a MOS capacitor, and particularly relates to a semiconductor memory device in which a memory cell is configured by a MOS transistor and a MOS capacitor, and in particular, to a method for burying a capacitor electrode in an element isolation trench. The present invention relates to an integrated semiconductor memory device.
（従来の技術）
従来、ダイナミックＲＡＭ （以下ｄＲＡＭと略記する
）のメモリセルは、電荷を蓄積することにより情報を保
持するＭＯＳキャパシタと、その電荷を外部回路とやり
とりするスイッチングトランジスタにより構成されてい
る。その構成は、例えば第３図（ａ）に示すように半導
体基板４１上にゲート絶縁膜４２を介して設けられた第
１ポリシリコンゲート４３により構成されたＭＯＳキャ
パシタと、ゲート絶縁膜４４を介して設けられた第２ポ
リシリコンゲート電極４５及び基板と逆導電型の高濃度
不純物領域４６により構成されたＭＯＳトランジスタと
からなる。なお、図中４７は索子分離用の厚い酸化膜、
４８は層間絶縁膜である。また、第３図（ｂ）はそのゲ
ート幅方向断面図である。(Prior Art) Conventionally, a memory cell of a dynamic RAM (hereinafter abbreviated as dRAM) is composed of a MOS capacitor that retains information by accumulating charge, and a switching transistor that exchanges the charge with an external circuit. . For example, as shown in FIG. 3(a), the structure includes a MOS capacitor formed of a first polysilicon gate 43 provided on a semiconductor substrate 41 with a gate insulating film 42 interposed therebetween, and a MOS capacitor formed of a first polysilicon gate 43 provided on a semiconductor substrate 41 with a gate insulating film 44 interposed therebetween. The MOS transistor is composed of a second polysilicon gate electrode 45 and a high concentration impurity region 46 of a conductivity type opposite to that of the substrate. In addition, 47 in the figure is a thick oxide film for cordon separation;
48 is an interlayer insulating film. Further, FIG. 3(b) is a cross-sectional view in the gate width direction.
ところで、蓄積電荷の量はＭＯＳキャパシタのゲート絶
縁膜の厚さ及びキャパシタ面積で決まる。Incidentally, the amount of accumulated charge is determined by the thickness of the gate insulating film of the MOS capacitor and the area of the capacitor.
従って、情報の安定した書込み及び読出しのためには、
ＭＯＳキャパシタの面積を大きくせざるを得ず、これが
メモリセル”の微細化、高密度化を妨げる大きな要因と
なっていた。Therefore, for stable writing and reading of information,
The area of the MOS capacitor had to be increased, and this was a major factor hindering the miniaturization and higher density of memory cells.
そこで最近、キャパシタ容量を小さくすることなくメモ
リセル占有面積を縮小するために、素子分離領域に溝を
形成し、この溝の側面をキャパシタとして利用するメモ
リセル構造が提案されている。この構造では、平面的な
セル面積を増大することなく、キャパシタ容量を大きく
することができるので、メモリセルの微細化、高密度化
に極めて有効である。Recently, in order to reduce the area occupied by the memory cell without reducing the capacitance of the capacitor, a memory cell structure has been proposed in which a trench is formed in the element isolation region and the side surfaces of the trench are used as a capacitor. This structure allows the capacitor capacity to be increased without increasing the planar cell area, and is therefore extremely effective in miniaturizing and increasing the density of memory cells.
しかしながら、この種の装置にあっては次のような問題
があった。即ち、キャパシタ電極がトランジスタの周囲
を取囲むように配置されているため、このキャパシタ電
極の影響でスイッチングトランジスタの特性が不安定に
なる虞れがある。特に、キャパシタ形成領域以外の溝に
埋込まれたキャパシタ電極がトランジスタのチャネル領
域に近接しているので、この部分における影響でトラン
ジスタの特性が大きく劣化する虞れがあった。However, this type of device has the following problems. That is, since the capacitor electrode is arranged so as to surround the transistor, the characteristics of the switching transistor may become unstable due to the influence of the capacitor electrode. In particular, since the capacitor electrode buried in the trench other than the capacitor formation region is close to the channel region of the transistor, there is a possibility that the characteristics of the transistor will be significantly deteriorated due to the influence in this region.
（発明が解決しようとする問題点）
このように従来、素子分離用溝にキャパシタ電極が埋込
んだ構造においては、キャパシタ電極がスイッチング用
トランジスタを囲むことになり、且つトランジスタのチ
ャネル領域にキャパシタ電極が近接することになるので
、トランジスタの動作が不安定になると云う問題があっ
た。(Problems to be Solved by the Invention) Conventionally, in a structure in which a capacitor electrode is embedded in an element isolation trench, the capacitor electrode surrounds the switching transistor, and the capacitor electrode is located in the channel region of the transistor. There was a problem in that the operation of the transistor became unstable because the two transistors were placed close to each other.
本発明は上記事情を考慮してなされたもので、その目的
とするところは、素子分離用溝に埋込まれたキャパシタ
電極がスイッチングトランジスタの特性に悪影響を与え
るのを防止することができ、トランジスタ特性の安定化
をはかり得る半導体記憶装置を提供することにある。The present invention has been made in consideration of the above circumstances, and its purpose is to prevent the capacitor electrode embedded in the element isolation trench from having an adverse effect on the characteristics of the switching transistor. An object of the present invention is to provide a semiconductor memory device whose characteristics can be stabilized.
［発明の構成］
（問題点を解決するための手段）
本発明の骨子は、メモリセルのスイッチングトランジス
タをその周辺に埋込まれたキャパシタ電極の影響から隔
離すべく、キャパシタ電極がトランジスタのチャネル領
域に影響を与えないように、キャパシタ電極を基板表面
よりも低い位置に埋込むことにある。[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is that, in order to isolate the switching transistor of a memory cell from the influence of the capacitor electrode embedded in its periphery, the capacitor electrode is connected to the channel region of the transistor. The purpose is to bury the capacitor electrode at a position lower than the substrate surface so as not to affect the substrate surface.
即ち本発明は、ＭＯＳトランジスタ及びＭＯＳキャパシ
タからメモリセルを構成してなり、半導体基板の表面に
設けられた素子分離用溝の一部に上記キャパシタを形成
した半導体記憶装置において、前記溝内の全てに該溝の
壁面に形成された絶縁膜を介してキャパシタ電極を埋込
むと共に、キャパシタ形成領域以外ではキャパシタ電極
の表面が基板表面よりも下方に位置するようにし、且つ
このキャパシタ電極上に基板表面と略同じ高さまで絶縁
膜を埋込むようにしたものである。That is, the present invention provides a semiconductor memory device in which a memory cell is constituted by a MOS transistor and a MOS capacitor, and in which the capacitor is formed in a part of an element isolation trench provided on the surface of a semiconductor substrate. A capacitor electrode is embedded through an insulating film formed on the wall surface of the groove, and the surface of the capacitor electrode is located below the substrate surface in areas other than the capacitor formation area, and the substrate surface is placed on the capacitor electrode. The insulating film is buried to approximately the same height.
（作用）
本発明によれば、キャパシタ形成領域以外ではキャパシ
タ電極の表面が基板表面よりも低くなるので、基板表面
近傍に形成されるトランジスタのチャネル領域とキャパ
シタ電極とを十分離すことができる。さらに、キャパシ
タ形成領域以外の溝においてキャパシタ電極上に絶縁膜
を埋込んでいるので、トランジスタの周囲はキャパシタ
形成領域を除いて絶縁膜で囲まれることになる。従って
、スイッチングトランジスタはキャパシタ電極からの影
響を受シブることなく、安定した動作が実現される。(Operation) According to the present invention, since the surface of the capacitor electrode is lower than the substrate surface in areas other than the capacitor formation region, the channel region of the transistor formed near the substrate surface and the capacitor electrode can be sufficiently separated. Furthermore, since the insulating film is buried on the capacitor electrode in the groove other than the capacitor forming region, the transistor is surrounded by the insulating film except for the capacitor forming region. Therefore, the switching transistor is not influenced by the capacitor electrode, and stable operation is realized.
（実施例）
以下、本発明のｗｌＩｌを図示の実施例によって説明す
る。(Example) Hereinafter, wlIl of the present invention will be explained with reference to illustrated examples.
第１図は本発明の一実施例に係わるＭＯ８型ｄＲＡＭの
メモリセル部の構成を説明するためのもので、（ａ）は
平面図、（ｂ）は（ａ）の矢視Ａ−Ａ断面図である。な
お、このメモリセルは、１トランジスタ／１キヤパシタ
からなるものである。FIG. 1 is for explaining the configuration of a memory cell portion of an MO8 type dRAM according to an embodiment of the present invention, in which (a) is a plan view, and (b) is a cross section taken along arrow A-A in (a). It is a diagram. Note that this memory cell is composed of one transistor/one capacitor.
ｐ型Ｓｉ基板１１に溝１２が設けられ、この溝１２によ
り素子形成領域が島状に分離されている。A groove 12 is provided in the p-type Si substrate 11, and the groove 12 separates element formation regions into island shapes.
溝１２内には絶縁膜１３．１４を介してポリＳｉからな
るキャパシタ電極１５が埋込まれている。A capacitor electrode 15 made of poly-Si is embedded in the groove 12 with an insulating film 13, 14 interposed therebetween.
このキャパシタミル１５は、キャパシタ形成領域以外の
部分では基板表面よりも十分低い位置に埋込まれている
。そして、このキャパシタ電極１５上に絶縁膜１６が埋
込まれ、この絶縁膜１６の表面が基板表面と略一致する
ものとなっている。This capacitor mill 15 is buried at a position sufficiently lower than the substrate surface in a portion other than the capacitor forming region. An insulating film 16 is buried on this capacitor electrode 15, and the surface of this insulating film 16 substantially coincides with the surface of the substrate.
ここで、上記キャパシタ電極１５と溝１２の側壁に拡散
により形成されたｎ−１１７とからＭＯＳキャパシタが
構成されている。また、キャパシタ形成（！４域以外で
は溝側壁の絶縁膜１３の厚みは５００〜１０００人程度
であり、キャパシタ形成領域では溝側壁の絶縁［１１４
の厚みはそれより十分薄い１００人程度となっている。Here, a MOS capacitor is constituted by the capacitor electrode 15 and the n-117 formed on the side wall of the groove 12 by diffusion. In addition, the thickness of the insulating film 13 on the trench side wall is about 500 to 1000 in areas other than the capacitor formation region (!4), and the thickness of the insulating film 13 on the trench side wall in the capacitor formation region
Its thickness is much thinner than that, at around 100 people.
一方、前記溝１２により分割された島状領域（トランジ
スタ形成領域）には、ゲート酸化膜１８を介してワード
線となるゲート電極１９が形成され、さらにｎ”１１２
１．２２を形成してＭＯＳトランジスタが構成されてい
る。そして、この基板上に層間絶縁ＭＩ２３を介してビ
ット線となるへ２配線２４が形成されている。On the other hand, in the island-like regions (transistor formation regions) divided by the grooves 12, gate electrodes 19 which become word lines are formed via gate oxide films 18, and
1.22 to form a MOS transistor. Then, two wirings 24 that become bit lines are formed on this substrate via an interlayer insulation MI23.
次に、上記素子の製造工程について、第２図を参照して
説明する。Next, the manufacturing process of the above device will be explained with reference to FIG.
まず、第２図（ａ）に示す如く、ｐ型３ｉ基板１１上に
ＳｉＯ２等のマスク（図示せず）を設け、反応性イオン
エツチング（ＲＩＥ）等により格子状に溝１２を形成し
、複数の島状領域を形成する。First, as shown in FIG. 2(a), a mask (not shown) such as SiO2 is provided on a p-type 3i substrate 11, and grooves 12 are formed in a grid pattern by reactive ion etching (RIE) or the like. form an island-like region.
続いて、マスクを除去したのち、キャパシタ電極の絶縁
のために、全面にやや厚めの酸化１１１１３を形成する
。Subsequently, after removing the mask, a somewhat thick oxide layer 11113 is formed over the entire surface to insulate the capacitor electrode.
次いで、第２図（ｂ）に示す如く、レジストからなるマ
スク３１を形成し、キャパシタを形成する部分について
は底部を除きレジストを選択的にエツチングする等して
、酸化膜１３を選択エツチングする。これは倒えば、レ
ジスト３１ポジ型を用いる場合、キャパシタ側を露光し
て０２プラズマでキャパシタ部のレジストを所望厚エツ
チングすることにより可能である。或いは、レジスト３
１上に他のマスクを形成し、キャパシタ部に所定厚のレ
ジスト３１を残すようにすることもできる。その後、レ
ジスト３１を全て除去してキャパシタ形成領域における
溝１２の側壁にｎ型不純物を拡散してｎ−型層１７を形
成する。このｎ一層１７の形成には、該層を形成する領
域上のみにＰＳＧ膜等を被着し、この膜からの同相拡散
等を用いればよい。Next, as shown in FIG. 2(b), a mask 31 made of resist is formed, and the oxide film 13 is selectively etched by selectively etching the resist except for the bottom portion where a capacitor is to be formed. In other words, when a positive type resist 31 is used, this can be done by exposing the capacitor side and etching the resist in the capacitor portion to a desired thickness using 02 plasma. Or resist 3
It is also possible to form another mask on the capacitor 1 and leave a predetermined thickness of the resist 31 in the capacitor portion. Thereafter, the resist 31 is completely removed and an n-type impurity is diffused into the sidewalls of the trench 12 in the capacitor formation region to form an n-type layer 17. To form this n-layer 17, a PSG film or the like may be deposited only on the region where the layer is to be formed, and in-phase diffusion from this film may be used.
次いで、第２図（Ｃ）に示す如く、キャパシタ形成領域
に薄めの絶縁１１１４を熱酸化等により形成する。続い
て、全面にキャパシタ電極となるポリ３ｉ膜１５を堆積
し、これにより溝１２内をポリ５ｉＩ１１５で完全に埋
込む。このポリ５ｉｌ１１５に対しての不純物の導入は
、堆積と同時でも、最後でも、またことによっては堆積
を数段階に分けたその途中でもよい。Next, as shown in FIG. 2C, a thin insulator 1114 is formed in the capacitor formation region by thermal oxidation or the like. Subsequently, a poly 3i film 15 that will become a capacitor electrode is deposited on the entire surface, thereby completely filling the groove 12 with poly 5iI 115. The impurity may be introduced into the poly 5il 115 at the same time as the deposition, at the end, or possibly during the deposition which is divided into several stages.
次いで、第２図（ｄ）に示す如く、キャパシタ形成領域
上にはレジスト等のマスク３２を形成しておき、ポリ５
１ｇ１１５をＲＩＥ等によりエッチバックする。そして
、キャパシタ形成領域以外ではポリｓ＋ｇｉ１５の表面
が基板表面よりも下方にくるようにする。Next, as shown in FIG. 2(d), a mask 32 such as a resist is formed on the capacitor formation area, and a poly 5
1g115 is etched back by RIE or the like. The surface of the polys+gi 15 is placed below the substrate surface in areas other than the capacitor formation region.
次いで、第２図（ｅ）に示す如く、キャパシタ電極１５
とゲートとを絶縁するために、キャパシタ形成領域以外
の溝１２においてキャパシタ電極１５上に埋込み絶縁膜
１６を形成し、この絶縁膜１６の表面を基板表面と略同
じ高さにする。絶縁１１６の埋込み形成には、全面に酸
化膜を堆積したのち、この酸化膜を基板表面が露出する
までエッチバックすればよい。このとき、絶縁１１１５
の表面が基板表面よりも下位にならないように制御する
。Next, as shown in FIG. 2(e), the capacitor electrode 15
In order to insulate the substrate and the gate, a buried insulating film 16 is formed on the capacitor electrode 15 in the trench 12 outside the capacitor formation region, and the surface of this insulating film 16 is made to be approximately at the same height as the substrate surface. To form the insulator 116 in a buried manner, an oxide film may be deposited over the entire surface, and then this oxide film may be etched back until the surface of the substrate is exposed. At this time, the insulation 1115
control so that the surface of the substrate is not lower than the substrate surface.
次いで、第２図（ｆ）に示す如く、ゲート酸化膜１８を
形成したのち、ゲート電極となるべきポリ５ｉ１１９を
堆積し、このポリ３ｉ膜１９をバターニングしてゲート
電極を形成する。さらに、不純物の拡散によりソース・
ドレイン領域（ｎ ＋層）２１．２２を形成する。Next, as shown in FIG. 2(f), after forming a gate oxide film 18, a poly 5i film 119 which is to become a gate electrode is deposited, and this poly 3i film 19 is patterned to form a gate electrode. Furthermore, due to the diffusion of impurities, the source
Drain regions (n+ layers) 21 and 22 are formed.
これ以降は、通常のｄＲＡＭセルの製造工程と同様にし
て、層間絶縁膜２３の形成及びビット線２５の形成等を
行うことによって、前記第１図に示す如き構造が実現さ
れることになる。Thereafter, the interlayer insulating film 23 and the bit line 25 are formed in the same manner as in the normal dRAM cell manufacturing process, thereby realizing the structure shown in FIG. 1.
かくして形成された本装置においては、キャパシタ形成
領域以外のキャパシタ電極１５が基板表面よりも下方に
埋込まれ、その上に絶縁１１１６が埋込まれているので
、基板表面部に形成されるトランジスタはキャパシタ形
成領域を除いて厚みの大きな絶縁膜１６で囲まれること
になる。しかも、この絶縁膜・１６の存在により、トラ
ンジスタのチャネルｌ１ｉｌＫとキャパシタ電極１５と
を十分離すことができる。このため、キャパシタ電極が
与えるトランジスタ特性の劣化を防止することができ、
スイッチングトランジスタは安定した特性を示すように
なる。また、絶縁膜１３を絶縁１１１４よりも十分厚く
しているので、溝内にポリＳ１を埋込んでも素子分離は
十分行うことができる。In this device thus formed, the capacitor electrode 15 other than the capacitor formation region is buried below the substrate surface, and the insulator 1116 is buried thereon, so that the transistor formed on the substrate surface is The region except for the capacitor formation region is surrounded by a thick insulating film 16. Furthermore, due to the presence of this insulating film 16, the channel l1ilK of the transistor and the capacitor electrode 15 can be separated sufficiently. Therefore, deterioration of transistor characteristics caused by the capacitor electrode can be prevented,
The switching transistor now exhibits stable characteristics. Furthermore, since the insulating film 13 is made sufficiently thicker than the insulating film 1114, element isolation can be achieved sufficiently even if poly S1 is buried in the trench.
なお、本発明は上述した実施例に限定されるものではな
い。例えば、前記埋込み絶縁膜や溝の側壁に形成する絶
縁膜は酸化膜に限るものではなく、窒化膜その他の絶縁
膜、さらには複数の絶縁膜を積層したものであってもよ
い。さらに、溝の側壁に形成する絶縁膜の厚みは仕様に
応じて適宜変更可能であるが、キャ゛バシタ領域ではキ
ャパシタ容量が大きくなるように薄（、それ以外の領域
では素子分離が確実となるように比較的厚くする必要が
ある。また、ゲート電極、キャパシタ電極はポリＳｉに
限るものではなく、ＭＯ等の金属或いは金属シリサイド
でもよい。さらに、基板としてＮ型を用いることもでき
るし、キャパシタの形態は仕様に応じて適宜変更可能で
ある。その他、本発明の要旨を逸脱しない範囲で、種々
変形して実施することができる。Note that the present invention is not limited to the embodiments described above. For example, the buried insulating film and the insulating film formed on the side walls of the trench are not limited to oxide films, but may be nitride films or other insulating films, or even a stack of a plurality of insulating films. Furthermore, the thickness of the insulating film formed on the side walls of the trench can be changed as appropriate depending on the specifications, but it should be thin in the capacitor region to increase the capacitance (and in other regions to ensure element isolation). In addition, the gate electrode and capacitor electrode are not limited to poly-Si, and may be made of metal such as MO or metal silicide.Furthermore, an N-type substrate can be used, and the capacitor electrode The form of can be changed as appropriate according to specifications.In addition, various modifications can be made without departing from the gist of the present invention.
［発明の効果］
以上詳述したように本発明によれば、キャパシタ電極が
トランジスタのチャネル領域に影響を与えないように、
キャパシタ電極を基板表面よりも低い位置に埋込み、且
つその上に絶縁膜を埋込んでいるので、キャパシタ電極
がスイッチングトランジスタの特性に悪影響を与、える
のを防止することができる。従って、トランジスタ特性
の安定化をはかることができ、信頼性の高いメモリセル
構造を実現することが可能となる。[Effects of the Invention] As detailed above, according to the present invention, the capacitor electrode is prevented from affecting the channel region of the transistor.
Since the capacitor electrode is buried at a position lower than the substrate surface and an insulating film is buried thereon, it is possible to prevent the capacitor electrode from adversely affecting the characteristics of the switching transistor. Therefore, transistor characteristics can be stabilized, and a highly reliable memory cell structure can be realized.
第１図は本発明の一実施例に係わる半導体記憶装置の概
略構造を示す平面図及び断面図、第２図は上記装置の製
造工程を示す断面図、第３図は従来の半導体記憶装置の
概略構造を示す断面図である。
１１・・・Ｓｉ基板、１２・・・素子分離用溝、１３゜
１４・・・絶縁膜、１５・・・キャパシタ電極、１６・
・・埋込み絶縁膜、１７・・・ｎ一層、１８・・・ゲー
ト酸化膜、１９・・・ゲート電極、２１．２２・・・ソ
ース・ドレイン領域（ｎ ４″層）、２３・・・層間絶
縁膜、２４・・・Ａｇ配線。
出願人代理人 弁理士 鈴江武彦
（ａ）
（ｂ）
第１図
第２図（１）
第２図（２）FIG. 1 is a plan view and a cross-sectional view showing a schematic structure of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the manufacturing process of the above device, and FIG. It is a sectional view showing a schematic structure. DESCRIPTION OF SYMBOLS 11... Si substrate, 12... Element isolation groove, 13° 14... Insulating film, 15... Capacitor electrode, 16...
...Buried insulating film, 17...N single layer, 18...Gate oxide film, 19...Gate electrode, 21.22...Source/drain region (N 4'' layer), 23...Interlayer Insulating film, 24...Ag wiring. Applicant's agent Patent attorney Takehiko Suzue (a) (b) Figure 1 Figure 2 (1) Figure 2 (2)
Claims (2)
モリセルを構成してなり、半導体基板の表面に設けられ
た素子分離用溝の一部に上記キャパシタを形成した半導
体記憶装置において、前記溝内の全てに該溝の壁面に形
成された絶縁膜を介してキャパシタ電極を埋込むと共に
、キャパシタ形成領域以外ではキャパシタ電極の表面が
基板表面よりも下方に位置し、且つこのキャパシタ電極
上に基板表面と略同じ高さまで絶縁膜を埋込んでなるこ
とを特徴とする半導体記憶装置。(1) In a semiconductor memory device in which a memory cell is constituted by a MOS transistor and a MOS capacitor, and the capacitor is formed in a part of an element isolation trench provided on the surface of a semiconductor substrate, the capacitor is completely filled in the trench. The capacitor electrode is buried through an insulating film formed on the wall of the groove, and the surface of the capacitor electrode is located below the substrate surface in areas other than the capacitor formation area, and the surface of the capacitor electrode is located at approximately the same height as the substrate surface. A semiconductor memory device characterized by having an insulating film embedded in the top.
形成領域よりもそれ以外の領域の方が厚く形成されてな
ることを特徴とする特許請求の範囲第１項記載の半導体
記憶装置。(2) The semiconductor memory device according to claim 1, wherein the insulating film on the wall surface of the element isolation trench is formed thicker in other regions than in the capacitor formation region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62076167A JP2607508B2 (en) | 1987-03-31 | 1987-03-31 | Semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62076167A JP2607508B2 (en) | 1987-03-31 | 1987-03-31 | Semiconductor storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63244673A true JPS63244673A (en) | 1988-10-12 |
| JP2607508B2 JP2607508B2 (en) | 1997-05-07 |
Family
ID=13597522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62076167A Expired - Fee Related JP2607508B2 (en) | 1987-03-31 | 1987-03-31 | Semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2607508B2 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6012752A (en) * | 1983-07-01 | 1985-01-23 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor memory device and manufacture thereof |
| JPS6239049A (en) * | 1985-08-14 | 1987-02-20 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS6254461A (en) * | 1985-09-03 | 1987-03-10 | Toshiba Corp | Semiconductor memory device |
| JPS6396950A (en) * | 1986-10-13 | 1988-04-27 | Matsushita Electric Ind Co Ltd | Semiconductor storage device |
-
1987
- 1987-03-31 JP JP62076167A patent/JP2607508B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6012752A (en) * | 1983-07-01 | 1985-01-23 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor memory device and manufacture thereof |
| JPS6239049A (en) * | 1985-08-14 | 1987-02-20 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS6254461A (en) * | 1985-09-03 | 1987-03-10 | Toshiba Corp | Semiconductor memory device |
| JPS6396950A (en) * | 1986-10-13 | 1988-04-27 | Matsushita Electric Ind Co Ltd | Semiconductor storage device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2607508B2 (en) | 1997-05-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR910010167B1 (en) | Stack capacitor dram cell and its manufacturing method | |
| US5290726A (en) | DRAM cells having stacked capacitors of fin structures and method of making thereof | |
| JPH05206451A (en) | Mosfet and its manufacture | |
| US6872629B2 (en) | Method of forming a memory cell with a single sided buried strap | |
| US5470778A (en) | Method of manufacturing a semiconductor device | |
| KR0139513B1 (en) | Semiconductor device | |
| US4921815A (en) | Method of producing a semiconductor memory device having trench capacitors | |
| KR20070047572A (en) | Semiconductor device and method for forming the same | |
| KR100566411B1 (en) | Semiconductor memory device and manufacturing method | |
| JPH05218329A (en) | Semiconductor device and its manufacture | |
| US6515326B2 (en) | Semiconductor memory device and method of fabricating the same | |
| JPS63244673A (en) | Semiconductor memory device | |
| JPH1197529A (en) | Manufacture of semiconductor device | |
| JPH0319362A (en) | Semiconductor memory and manufacture thereof | |
| JP3063203B2 (en) | Semiconductor memory and manufacturing method thereof | |
| JPH0621388A (en) | Semiconductor memory and manufacture thereof | |
| JP3120633B2 (en) | Semiconductor memory device and manufacturing method thereof | |
| JPS61134058A (en) | Manufacture of semiconductor device | |
| JPH0786427A (en) | Semiconductor device and its manufacture | |
| KR0151126B1 (en) | Method for fabricating a shallow trench stacked capacitor with high integrated dram cell | |
| JPH0621387A (en) | Semiconductor memory and manufacture thereof | |
| JPH0434831B2 (en) | ||
| KR960001952B1 (en) | Method of manufacturing a stacked trench capacitor | |
| JP2969789B2 (en) | Method for manufacturing semiconductor memory device | |
| KR100215914B1 (en) | Memory cell capacitor fabrication method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |