JPS63237482A - Semiconductor pressure sensor - Google Patents
Semiconductor pressure sensorInfo
- Publication number
- JPS63237482A JPS63237482A JP7207887A JP7207887A JPS63237482A JP S63237482 A JPS63237482 A JP S63237482A JP 7207887 A JP7207887 A JP 7207887A JP 7207887 A JP7207887 A JP 7207887A JP S63237482 A JPS63237482 A JP S63237482A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- single crystal
- pressure sensor
- crystal silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 230000000694 effects Effects 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 23
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 11
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 230000035945 sensitivity Effects 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 9
- 239000013078 crystal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000005297 pyrex Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 241000257465 Echinoidea Species 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体圧力センサに係り、詳しくは高温におい
ても好適な小型半導体圧力センサに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor pressure sensor, and more particularly to a small-sized semiconductor pressure sensor suitable even at high temperatures.
（従来の技術〉
機械的応力を加える事によってピエゾ抵抗効果によりそ
の抵抗値が変化することを利用して、単結晶シリコン基
板の一部の肉厚を薄くしダイレフラムを形成し、そのグ
イＸ７フラムに歪ゲージを拡散層等で形成して、ダイヤ
フラムに加わる圧力により歪ゲージを変形させ、ピエゾ
抵抗効果による抵抗値の変化を検出して圧力を測定覆る
半導体圧力センサが用いられている。(Conventional technology) Utilizing the fact that the resistance value changes due to the piezoresistance effect when mechanical stress is applied, the wall thickness of a part of the single crystal silicon substrate is thinned to form a direflame. Semiconductor pressure sensors are used that measure pressure by forming a strain gauge with a diffusion layer or the like, deforming the strain gauge by pressure applied to a diaphragm, and detecting changes in resistance due to the piezoresistive effect.
（発明が解決しようとする問題点）
しかしながら、上記の半導体圧力ゼンリーによると、単
結晶シリコン基板と歪ゲージとの電気的分離はｊ１１結
晶シリコン基板内に形成されるＰＮ接合にて行ってあり
、この様なセンサを高温において使用する場合、ＰＮ接
合部においてリーク電流が増加してしまい安定した測定
が困難になるという問題があった。(Problems to be Solved by the Invention) However, according to the above-mentioned semiconductor pressure sensor, the single crystal silicon substrate and the strain gauge are electrically separated by a PN junction formed within the J11 crystal silicon substrate. When such a sensor is used at high temperatures, there is a problem in that leakage current increases at the PN junction, making stable measurement difficult.
（発明の目的〉
この発明の目的は上記問題点を解消し、高温においても
歪ゲージと基板とを電気的に完全に分離でき、その出力
特性が安定である小型の半導体圧力センサを提供するこ
とにある。(Objective of the Invention) The object of the present invention is to solve the above-mentioned problems and to provide a small semiconductor pressure sensor that can completely electrically separate the strain gauge and the substrate even at high temperatures and has stable output characteristics. It is in.
（問題点を解決するための手段）
この発明は上記目的を達成するためになされたものであ
って、凹部及び該凹部に貫通孔をその一部に有する基板
と、前記凹部上及び該凹部の周辺にほぼ平滑に形成され
、その少なくとも一部に絶縁性を有する部分を形成した
ダイヤフラムと、前記絶縁性を有する部分上の所定領域
に形成される感圧素子部とを備えた半導体圧力センサを
その要旨とする。(Means for Solving the Problems) The present invention has been made to achieve the above object, and includes a substrate having a recess and a through hole in the recess, and A semiconductor pressure sensor comprising: a diaphragm formed substantially smoothly around the periphery and having an insulating part formed on at least a part of the diaphragm; and a pressure sensitive element part formed in a predetermined area on the insulating part. This is the summary.
（実施例）
以下、この発明を具体化した一実施例を図面に従って説
明する。(Example) An example embodying the present invention will be described below with reference to the drawings.
第１図（ａ）〜（Ｃ１）は本発明の実施例を示す断面図
であって、その製造工程を順に説明する。FIGS. 1(a) to (C1) are cross-sectional views showing an embodiment of the present invention, and the manufacturing process thereof will be explained in order.
まず、第１図（ａ＞において、１は（１００）面の第１
の単結晶シリコン基板であり、２は第１の単結晶シリコ
ン基板１の主表面上の所定領域に形成するシリコン酸化
膜（Ｓ！ ０２ ）である。このシリコン酸化膜２をマ
スクとして水酸化カリウム（ＫＯＨ＞等による異方性の
エツチング液を用いてエツチングし、同図（ｂ）に示す
にうな凹部３を形成する。次に、凹部３内にレーザビー
ムによって２０〜５０Ｉｉｍ径の貫通孔４を形成する。First, in Figure 1 (a), 1 is the first point on the (100) plane.
2 is a silicon oxide film (S! 02 ) formed in a predetermined region on the main surface of the first single crystal silicon substrate 1 . Using this silicon oxide film 2 as a mask, etching is performed using an anisotropic etching solution such as potassium hydroxide (KOH) to form a concave recess 3 as shown in FIG. A through hole 4 having a diameter of 20 to 50 Im is formed using a laser beam.
尚、ここで用いる基板としてはその結晶面は（１１０）
でもよく、又、パイレックスガラス、サファイア等に凹
部及び貫通孔を形成したものであってもよい。The crystal plane of the substrate used here is (110)
Alternatively, it may be made of Pyrex glass, sapphire, or the like with recesses and through holes formed therein.
一方、同図（Ｃ）に示すように、例えば、その比抵抗が
３〜５ΩｃｍのＮ型導電型であって、結晶面が（１００
）あるいは（１１０）の第２の単結晶シリコン基板５の
主表面上の所定領域に、シリコン酸化膜６を形成し、そ
のシリコン酸化膜６をマスクとしてボロン（Ｂ）等のＰ
型不純物を高濃度に拡散しピエゾ抵抗層７を、＜１１０
＞方向に形成する。引き続き、シリコン酸化膜６を除去
した後に、同図（ｄ）に示すように第２の単結晶シリコ
ン基板５の主表面上の全面にＬ Ｐ ＣＶ Ｄ法又はプ
ラズマＣＶＤ法により膜厚が０．１〜２．０μｍのシリ
コン窒化膜（Ｓｉ ３ Ｎ４ ） ８を形成し、ざらに
このシリコン窒化膜８上にＢＰＳＧ膜９を形成する。尚
、この時、ＢＰＳＧ膜９の表面は４ぼ平滑な状態となっ
ている。On the other hand, as shown in FIG.
) Alternatively, a silicon oxide film 6 is formed in a predetermined region on the main surface of the second single crystal silicon substrate 5 (110), and P such as boron (B) is deposited using the silicon oxide film 6 as a mask.
The type impurity is diffused at a high concentration to form the piezoresistive layer 7 with <110
> direction. Subsequently, after removing the silicon oxide film 6, as shown in FIG. 4(d), a film with a thickness of 0.00 mm is formed on the entire main surface of the second single-crystal silicon substrate 5 by L P CV D method or plasma CVD method. A silicon nitride film (Si 3 N4 ) 8 having a thickness of 1 to 2.0 μm is formed, and a BPSG film 9 is roughly formed on this silicon nitride film 8 . Incidentally, at this time, the surface of the BPSG film 9 is approximately smooth.
そして、同図（ｅ）に示すように、第１の単結晶シリコ
ン基板１の主表面上に、上下のパターンが設定通り重な
るように例えば赤外顕微鏡で位置合けを行い第２の単結
晶シリコン基板５に形成されたＢＰＳＧ膜９を配置する
。Then, as shown in FIG. 2(e), the second single crystal is aligned on the main surface of the first single crystal silicon substrate 1 using, for example, an infrared microscope so that the upper and lower patterns overlap as set. A BPSG film 9 formed on a silicon substrate 5 is placed.
ここで、本実施例においては第１．第２の単結晶シリコ
ン基板１，５（あるいはそれらのウェハ）の周辺部を真
空中でレーザにより溶融接着して仮市のを行う。しかる
後に真空炉内に入れ約１０００°Ｃ〜１１００’Ｃに加
熱し、ＢＰＳＧ膜９を溶融し第１．第２の単結晶シリコ
ン基板１，５の両者の接着を行う。又、接着が完全に行
われるように基板上に重しを乗せて行っている。Here, in this embodiment, the first. The peripheral portions of the second single-crystal silicon substrates 1 and 5 (or their wafers) are melted and bonded using a laser in a vacuum to perform a temporary market. Thereafter, it is placed in a vacuum furnace and heated to approximately 1000°C to 1100'C to melt the BPSG film 9. Both second single crystal silicon substrates 1 and 5 are bonded. Also, a weight is placed on the substrate to ensure complete adhesion.
尚、両者の接着を行う為の接着（接合）層としてＢＰＳ
Ｇ膜９を用いているが、他の低融点ガラス等を用いても
よく、又、その両者の接合は低融点ガラスの溶融接着に
限定されることなく、例えば第１の単結晶シリコン基板
１上のシリコン酸化膜２を除去して、いわゆる陽極接合
（アノ−ディックボンディング）により接合してもよく
、又、高温炉内で３ｉとＳｉＯ２等間の、いわゆる直接
接合を利用してもよい。In addition, BPS is used as an adhesive (bonding) layer to bond the two.
Although the G film 9 is used, other low-melting glass or the like may be used, and the bonding between the two is not limited to melt bonding of low-melting glass. For example, the first single-crystal silicon substrate 1 The upper silicon oxide film 2 may be removed and bonding may be performed by so-called anodic bonding, or so-called direct bonding between 3i and SiO2 etc. may be utilized in a high temperature furnace.
又、接着用のＢＰＳＧ膜９はシリコン窒化膜Ｂ上の全面
に形成することなく接着部分のみに部分的に形成しても
よい。又、絶縁膜としてのシリコン窒化膜８はシリコン
酸化膜等の他の絶縁膜であってもよい。Further, the BPSG film 9 for adhesion may not be formed on the entire surface of the silicon nitride film B, but may be formed partially only on the bonding portion. Further, the silicon nitride film 8 as an insulating film may be another insulating film such as a silicon oxide film.
そして、同図（ｆ＞に示すように、第１の単結晶シリコ
ン基板１の他主面（＠面）をワックス等で覆い（図示は
しない）、第２の中結晶シリ：ｌン基板５の仙主面（裏
面）側より、例えばエチレンジ７ミン（２６０ｍＪ２
） 、ヒｃｌ力Ｔ］−）Ｌｔ （４５ｑ）、水（１２０
ｍ、Ｑ）を主成分とする異方性エツチング液により第２
の単結晶シリコン基板５をエツチング除去する。この際
、エツチングはＮ型導電型である領域を選択的に進行し
、高温度にボロンを拡散したピエゾ抵抗層７部分及びシ
リコン窒化膜８はほとんどエツチングされずに残る。こ
のようにして絶縁膜としてのシリコン窒化膜８−トに単
結晶のピエゾ抵抗層７が形成される。そして、同図（ｇ
）に示すように、表面保護膜１０、及びΔｇ等から成る
配線層１１を形成して本実施例の半導体圧力センサを構
成する。Then, as shown in FIG. For example, ethylenedi7mine (260mJ2
), Hcl force T]-)Lt (45q), water (120
The second etching process is carried out using an anisotropic etching solution mainly composed of
The single crystal silicon substrate 5 is removed by etching. At this time, the etching proceeds selectively in the N-type conductivity type region, and the piezoresistive layer 7 and the silicon nitride film 8 in which boron is diffused at high temperature remain almost unetched. In this way, a single crystal piezoresistive layer 7 is formed on the silicon nitride film 8 as an insulating film. And the same figure (g
), a surface protective film 10 and a wiring layer 11 made of Δg, etc. are formed to constitute the semiconductor pressure sensor of this embodiment.
そこで本実施例によると、ピエゾ抵抗層７はシリコン窒
化膜８等にＪ二り第１の単結晶シリコン基板１と電気的
に完全に分離でき、高温において使用してもその特性は
安定となる。しかも、本実施例においては、シリコン窒
化膜８上に単結晶のピエゾ抵抗層７が形成されるので、
従来の多結晶のピエゾ抵抗層と比較して感度を高く、ば
らつきを小さくできる。Therefore, according to this embodiment, the piezoresistive layer 7 can be completely electrically separated from the first single crystal silicon substrate 1 by the silicon nitride film 8, etc., and its characteristics are stable even when used at high temperatures. . Moreover, in this embodiment, since the single crystal piezoresistive layer 7 is formed on the silicon nitride film 8,
Compared to conventional polycrystalline piezoresistive layers, the sensitivity can be increased and variations can be reduced.
又、従来、絶縁膜上に多結晶のシリコンを形成し、それ
を再結晶化してピエゾ抵抗層を形成するものがあるが、
そのようなピエゾ抵抗層と比較しても特性のばらつきを
小さくでき、製造コストを低くできるという点で本実施
例の半導体圧力セン１１は有効である。In addition, conventionally, polycrystalline silicon is formed on an insulating film and then recrystallized to form a piezoresistive layer.
The semiconductor pressure sensor 11 of this embodiment is effective in that variations in characteristics can be reduced and manufacturing costs can be reduced compared to such a piezoresistive layer.
さらに、本実施例によると、第１の単結晶シリコン基板
１のピエゾ抵抗層７側に必たる表面（主表面）に凹部３
が形成されており、凹部３を形成するのにエツチングさ
れる体積は比較的小さくなっており、その分、第１の単
結晶シリコン基板１を有効に使用することができ、第１
の単結晶シリコン基板１内に半導体圧力センサからの信
号を処理する回路を形成する場合、全体として小型にＪ
ることができる。又、本実施例の場合、シリコン窒化膜
８とＢＰＳＧ膜９とで構成されるダイヤフラムは、凹部
３の上部、及び凹部３の周）２２である第１の単結晶シ
リコン基板１上にわたってほぼ平滑に形成されており、
従来の圧力センサにおいて空洞部を対土するために形成
されるエツチング孔は存在することがなく、従来そのエ
ツチング孔にり機械的応力が弱くなっていたが本センサ
は機械的応力に対してその分強く、又、出力特性もその
分安定である。Furthermore, according to this embodiment, the recesses 3 are formed on the surface (main surface) of the first single crystal silicon substrate 1 on the piezoresistive layer 7 side.
is formed, and the volume that is etched to form the recess 3 is relatively small, so that the first single crystal silicon substrate 1 can be used effectively.
When forming a circuit for processing signals from a semiconductor pressure sensor in the single-crystal silicon substrate 1 of
can be done. Further, in the case of this embodiment, the diaphragm composed of the silicon nitride film 8 and the BPSG film 9 is substantially smooth over the first single crystal silicon substrate 1, which is the upper part of the recess 3 and the circumference 22 of the recess 3. It is formed in
Conventional pressure sensors do not have etched holes formed to expose the cavity to the ground, and conventionally, the etched holes weaken mechanical stress, but this sensor has no effect on mechanical stress. It is stronger, and its output characteristics are also more stable.
しかし、従来の方法では貫通孔を形成させる際には、エ
ツチングにより貫通孔を形成していたので末広がりとな
りセンサの小形化を行なう上での降雪となっていたが、
上記実施例においては直線的な貫通孔４を形成できセン
サを小形化することができる。However, in the conventional method, when forming a through hole, the through hole was formed by etching, which caused the hole to widen at the end, which was a problem when downsizing the sensor.
In the above embodiment, the linear through hole 4 can be formed and the sensor can be made smaller.
又、従来の圧力センサ、例えば素子形成面に圧力を加え
る雰囲気を直接接触させないものの例を第９図、第１０
図に示し、そのセンサチップ１０１の概略の寸法は第１
０図に示すにうに厚さ方向に対して横（平面〉の寸法が
大きくセンサチップ１０１とパッケージ等の熱膨張係数
の差がピエゾ抵抗に影響を及ぼし特性面の安定性に欠け
、その対策として、センサデツプ１０１と熱膨張係数の
等しい（又は、はぼ同じ＞Ｓ＋又はパイレックスの台座
１０２を当てかい高さ方向を大きくしてその影響を除い
ている。本実施例のセンサチップ１２の寸法関係は第２
図、第３図に示すようなものであり、第３図に示すよう
にダイヤフラム部の平面寸法に比較して高さ方向は十分
な余裕があり台座等の対策は一切必要としない。よって
、］ス１〜面だけでなく接着部を減らすことが可能であ
り信頼性の向上につながる。Also, examples of conventional pressure sensors, such as those that do not bring the element forming surface into direct contact with the atmosphere that applies pressure, are shown in Figures 9 and 10.
The approximate dimensions of the sensor chip 101 are as shown in the figure.
As shown in Figure 0, the horizontal (plane) dimensions are large with respect to the thickness direction, and the difference in thermal expansion coefficient between the sensor chip 101 and the package affects the piezoresistance, resulting in a lack of stability in terms of characteristics. The pedestal 102 is made of Pyrex or Pyrex, which has the same coefficient of thermal expansion as the sensor depth 101 (or has the same coefficient of thermal expansion as that of the sensor depth 101), and increases the height in the height direction to eliminate the influence.The dimensional relationship of the sensor chip 12 of this embodiment is as follows. Second
3, and as shown in FIG. 3, there is a sufficient margin in the height direction compared to the planar dimension of the diaphragm portion, and no measures such as a pedestal are required. Therefore, it is possible to reduce not only the number of surfaces but also the number of bonded parts, leading to improved reliability.
尚、この発明は−Ｆ記実施例に限定される”ｂのでなく
、例えば、上記実施例ではグイＡ７フラムの厚ざはシリ
コン窒化膜８の膜厚によって調整されるが、接着前の第
２の単結晶シリコン基板５を、第４図に示すように、シ
リコン窒化膜８上に適当な熱膨張係数を有する多結晶シ
リコン層あるいは再結晶化した単結晶シリコン層１３を
形成し、その上にＢ Ｐ Ｓ Ｇ Ｉｌｕ ９を形成す
る構成とし、ダイヤフラムの厚さを例えば多結晶シリコ
ン層１３の厚さにより任意に調整してもよい。Note that this invention is not limited to the embodiment described in -F. For example, in the above embodiment, the thickness of the Gui A7 flam is adjusted by the thickness of the silicon nitride film 8, As shown in FIG. 4, a polycrystalline silicon layer or a recrystallized single-crystalline silicon layer 13 having an appropriate coefficient of thermal expansion is formed on a silicon nitride film 8, and then The structure is such that a B P S G Ilu 9 is formed, and the thickness of the diaphragm may be arbitrarily adjusted by, for example, the thickness of the polycrystalline silicon layer 13 .
又、上記実施例ではピエゾ抵抗層７のパターンは予め形
成されているが、第２の単結晶シリコン基板５内に主表
面側より所定の厚みをもって全面にＰ型不純物を拡散し
、第２の単結晶シリコン基板５のエツチング後に所定の
パターンを形成してもよい。Further, in the above embodiment, the pattern of the piezoresistive layer 7 is formed in advance, but P-type impurities are diffused over the entire surface of the second single crystal silicon substrate 5 from the main surface side to a predetermined thickness. A predetermined pattern may be formed after etching the single crystal silicon substrate 5.
ざらに、上記実施例の説明では簡単の為に省略したが、
半導体圧力セン９−の出力を処理する回路を第１の単結
晶シリコン基板１内に形成してもよい。そして、例えば
、第５図は出力処理回路の構成要素として、ＭＯＳＦＥ
Ｔを表わす断面図であり、同図において、１４は第１の
単結晶シリコン基板１内に形成されるＰ−ウェル領域、
１５，１６はＰ−ウェル領域１３内に形成されるそれぞ
れＮ＋ソース拡散領域、ドレイン拡散領域、１７はフィ
ールド絶縁膜、１８．１９はそれぞれソース電極、トレ
イン電極、２０はゲート電極、２１は絶縁膜であり、そ
の各々は公知の半導体加工技術により形成される。Roughly, in the explanation of the above example, it was omitted for the sake of brevity.
A circuit for processing the output of the semiconductor pressure sensor 9- may be formed within the first single crystal silicon substrate 1. For example, FIG. 5 shows a MOSFE as a component of the output processing circuit.
14 is a cross-sectional view showing T, in which 14 is a P-well region formed in the first single crystal silicon substrate 1;
15 and 16 are an N+ source diffusion region and a drain diffusion region formed in the P-well region 13, respectively, 17 is a field insulating film, 18 and 19 are a source electrode and a train electrode, respectively, 20 is a gate electrode, and 21 is an insulating film. , each of which is formed using known semiconductor processing techniques.
さらに、又、上記実施例においては貫通孔４の形成はウ
ェハ面に垂直に１本の孔をあけた例で示したが、これに
限定されない。例えば、第６図（ａ）に示すように斜め
方向に貫通孔４を形成したり、第６図（ｂ）に示すよう
にウェハの上面及び下面方向から別々の角度でもって形
成してもよい。このように、斜め方向に角度をもって形
成すると急激な圧力の変化、及び粒子等が圧力導入孔と
してのこの貫通孔４に飛び込んだ場合にも直接ダイヤフ
ラム而にあたることなく緩和される。又、第６図（Ｃ）
は複数個の貫通孔４を設けた場合の例であり、ダイヤフ
ラム形成後の洗浄等において効果が大きく、さらにゴミ
等による貫通孔４のふさがりに対しても効果がある。Furthermore, in the above embodiment, the through hole 4 is formed by forming one hole perpendicular to the wafer surface, but the present invention is not limited to this. For example, the through holes 4 may be formed obliquely as shown in FIG. 6(a), or may be formed at different angles from the upper and lower surfaces of the wafer as shown in FIG. 6(b). . In this way, if the pressure is formed at an angle in the diagonal direction, even if there is a sudden change in pressure or if particles or the like jump into the through hole 4 serving as the pressure introduction hole, the pressure will be alleviated without directly hitting the diaphragm. Also, Figure 6 (C)
This is an example in which a plurality of through holes 4 are provided, which is highly effective in cleaning after forming the diaphragm, and is also effective against clogging of the through holes 4 by dust and the like.
ざらに、第６図（ｄ）、（ｅ）は貫通孔４の形成におい
て、まずウニハエ程の途中では同図（ｄ）に示すように
貫通孔４を回通させず途中までとし残し部分２２を形成
しておく。このようにすればウニハエ程の途中で凹部３
２貫通部４ヘゴミ、不純物、洗浄液等が残留せずきれい
な状歳で保つことができる。そして、ウニハエ程の最終
までいった状態（ピエゾ抵抗１周辺回路、配線層、パッ
シベーション等形成後、本図では省略する）で裏面斜め
方向からレーデビームｌｂの照射により貫通孔４を形成
する。このように、斜め方向からレーデビームＬｂを照
射することにより、ダイヤフラム面に直接レーザビーム
Ｌｂが当ることがなく、ダメージを引き起さない。尚、
第６図（ａ）〜（ｅ）はそれぞれ組み合せて使用するこ
とが可能なことは言うまでもない。Roughly speaking, FIGS. 6(d) and 6(e) show that in forming the through-hole 4, first, in the middle of the sea urchin fly, the through-hole 4 is not passed through as shown in FIG. Form it. If you do this, the recess 3 will be in the middle of the sea urchin fly.
No dirt, impurities, cleaning liquid, etc. remain in the 2 penetration part 4, so it can be kept in a clean condition. Then, in the final state (after forming the peripheral circuit of the piezoresistor 1, the wiring layer, the passivation, etc., which is omitted from this figure)), the through hole 4 is formed by irradiating the back surface with the Lede beam lb from an oblique direction. In this way, by irradiating the laser beam Lb from an oblique direction, the laser beam Lb does not directly hit the diaphragm surface, and no damage is caused. still,
It goes without saying that FIGS. 6(a) to 6(e) can be used in combination.
又、本実施例ではレーデビームにより貫通孔４を形成し
たが第７図に示すようにシリコンの（１１０）面を用い
て第８図に示す方位に貫通孔パターンを形成して、Ｋ
ＯＨ溶液等の異方性エツチングを行なえば（１１１）面
を側壁としてシリコン基板１に貫通孔４を形成できる。In this embodiment, the through-holes 4 were formed using a Lede beam, but as shown in FIG. 7, the (110) plane of silicon was used to form the through-hole pattern in the direction shown in FIG.
By performing anisotropic etching using an OH solution or the like, a through hole 4 can be formed in the silicon substrate 1 with the (111) plane as a side wall.
また（１１０）面の方位を傾けることにより、斜め方向
に貫通孔を形成することも可能である。Furthermore, by tilting the orientation of the (110) plane, it is also possible to form the through hole in an oblique direction.
発明の効果
以上述べたように本発明によると、感圧素子部はダイヤ
フラムの絶縁性を有する部分により高温にＪ３いても基
板と電気的に完全に分離され、又、ダイヤフラムは基板
の凹部上及び凹部の周辺部にわたってほぼ重滑に形成さ
れているので、機械的強度が比較的強く、出力特性は安
定となる。又、感圧素子部側の基板より凹部を形成して
いるので、その凹部を小ざくすることができ、又、ダイ
ヤフラムの厚さを薄く形成できるので小型の半導体圧力
センサを提供できる優れた効果を発揮する。Effects of the Invention As described above, according to the present invention, the pressure-sensitive element portion is completely electrically isolated from the substrate even at high temperatures due to the insulating portion of the diaphragm, and the diaphragm is completely separated from the substrate by the insulating portion of the diaphragm. Since the concave portion is formed to be substantially smooth over the periphery thereof, the mechanical strength is relatively strong and the output characteristics are stable. In addition, since the recess is formed from the substrate on the pressure-sensitive element side, the recess can be made smaller, and the diaphragm can be made thinner, which has the advantage of providing a compact semiconductor pressure sensor. demonstrate.
第１図（ａ）〜（ｇ）はこの発明の実施例を示す図、第
２図は本発明の半導体圧力センサの全体図、第３図は本
発明の圧力センサの一部拡大図、第４図は別例を示す図
、第５図は他の別例を示す図、第６図（ａ）〜（ｅ）は
他の別例を示す図、第７図及び第８図は別例を説明する
ための図、第９図は従来の半導体圧力センサの全体図、
第１０図は従来の半導体圧力センサの要部拡大図である
。
図中、１は第１の単結晶シリコン基板、３は凹部、４は
貫通孔、５は第２の単結晶シリコン基板、７はピエゾ抵
抗層、８はシリコン窒化膜、９はＢＰＳＧ膜である。
第１図
第４図
ｑ
第５図
第７図
第８図1(a) to (g) are diagrams showing embodiments of the present invention, FIG. 2 is an overall view of the semiconductor pressure sensor of the present invention, and FIG. 3 is a partially enlarged view of the pressure sensor of the present invention. Figure 4 is a diagram showing another example, Figure 5 is a diagram showing another example, Figures 6 (a) to (e) are diagrams showing other examples, and Figures 7 and 8 are other examples. Figure 9 is an overall diagram of a conventional semiconductor pressure sensor.
FIG. 10 is an enlarged view of the main parts of a conventional semiconductor pressure sensor. In the figure, 1 is a first single crystal silicon substrate, 3 is a recess, 4 is a through hole, 5 is a second single crystal silicon substrate, 7 is a piezoresistive layer, 8 is a silicon nitride film, and 9 is a BPSG film. . Figure 1 Figure 4 q Figure 5 Figure 7 Figure 8
Claims (1)
、 前記凹部上及び該凹部の周辺にほぼ平滑に形成され、そ
の少なくとも一部に絶縁性を有する部分を形成したダイ
ヤフラムと、 前記絶縁性を有する部分上の所定領域に形成される感圧
素子部と を備えることを特徴とする半導体圧力センサ。 ２、前記感圧素子部はピエゾ抵抗効果を有するピエゾ抵
抗層である特許請求の範囲第１項記載の半導体圧力セン
サ。 ３、前記ダイヤフラムは絶縁層である特許請求の範囲第
１項又は第２項に記載の半導体圧力センサ。 ４、前記ダイヤフラムは絶縁層及び該絶縁層と前記基板
とを接合するための接合層との少なくとも２層から成る
ものである特許請求の範囲第１項乃至第３項のいずれか
１項に記載の半導体圧力センサ。[Scope of Claims] 1. A substrate having a recess and a through hole in the recess as a part thereof, and a portion having an insulating property at least in part, which is formed substantially smoothly on and around the recess. A semiconductor pressure sensor comprising: a formed diaphragm; and a pressure sensitive element portion formed in a predetermined region on the insulating portion. 2. The semiconductor pressure sensor according to claim 1, wherein the pressure sensitive element portion is a piezoresistive layer having a piezoresistance effect. 3. The semiconductor pressure sensor according to claim 1 or 2, wherein the diaphragm is an insulating layer. 4. The diaphragm is composed of at least two layers: an insulating layer and a bonding layer for bonding the insulating layer and the substrate, according to any one of claims 1 to 3. semiconductor pressure sensor.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62072078A JPH0831608B2 (en) | 1987-03-25 | 1987-03-25 | Method for manufacturing semiconductor pressure sensor |
| US07/132,573 US4975390A (en) | 1986-12-18 | 1987-12-08 | Method of fabricating a semiconductor pressure sensor |
| DE3743080A DE3743080C2 (en) | 1986-12-18 | 1987-12-18 | Method of manufacturing a semiconductor pressure sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62072078A JPH0831608B2 (en) | 1987-03-25 | 1987-03-25 | Method for manufacturing semiconductor pressure sensor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63237482A true JPS63237482A (en) | 1988-10-03 |
| JPH0831608B2 JPH0831608B2 (en) | 1996-03-27 |
Family
ID=13479013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62072078A Expired - Lifetime JPH0831608B2 (en) | 1986-12-18 | 1987-03-25 | Method for manufacturing semiconductor pressure sensor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0831608B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1022510A (en) * | 1996-03-28 | 1998-01-23 | Commiss Energ Atom | Strain gage sensor using piezoelectric resistance action and its manufacture |
| JP2007184546A (en) * | 2005-12-30 | 2007-07-19 | Samsung Electronics Co Ltd | Silicon direct bonding method |
| JP2010181372A (en) * | 2009-02-09 | 2010-08-19 | Fujikura Ltd | Method of manufacturing pressure sensor and pressure sensor |
| JP2015168143A (en) * | 2014-03-06 | 2015-09-28 | セイコーエプソン株式会社 | Formation method of through-hole, member, inkjet head, inkjet head unit and inkjet type recording apparatus |
| CN111504540A (en) * | 2019-01-30 | 2020-08-07 | 美蓓亚三美株式会社 | Sensor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55162272A (en) * | 1979-06-05 | 1980-12-17 | Mitsubishi Electric Corp | Semiconductor pressure converter |
| JPS607044U (en) * | 1983-06-28 | 1985-01-18 | 株式会社フジクラ | semiconductor pressure sensor |
-
1987
- 1987-03-25 JP JP62072078A patent/JPH0831608B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55162272A (en) * | 1979-06-05 | 1980-12-17 | Mitsubishi Electric Corp | Semiconductor pressure converter |
| JPS607044U (en) * | 1983-06-28 | 1985-01-18 | 株式会社フジクラ | semiconductor pressure sensor |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1022510A (en) * | 1996-03-28 | 1998-01-23 | Commiss Energ Atom | Strain gage sensor using piezoelectric resistance action and its manufacture |
| JP2007184546A (en) * | 2005-12-30 | 2007-07-19 | Samsung Electronics Co Ltd | Silicon direct bonding method |
| JP2010181372A (en) * | 2009-02-09 | 2010-08-19 | Fujikura Ltd | Method of manufacturing pressure sensor and pressure sensor |
| JP2015168143A (en) * | 2014-03-06 | 2015-09-28 | セイコーエプソン株式会社 | Formation method of through-hole, member, inkjet head, inkjet head unit and inkjet type recording apparatus |
| CN111504540A (en) * | 2019-01-30 | 2020-08-07 | 美蓓亚三美株式会社 | Sensor device |
| CN111504540B (en) * | 2019-01-30 | 2023-10-03 | 美蓓亚三美株式会社 | sensor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0831608B2 (en) | 1996-03-27 |
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