JPS63234575A - Formation of pattern of superconducting circuit - Google Patents
Formation of pattern of superconducting circuitInfo
- Publication number
- JPS63234575A JPS63234575A JP62067789A JP6778987A JPS63234575A JP S63234575 A JPS63234575 A JP S63234575A JP 62067789 A JP62067789 A JP 62067789A JP 6778987 A JP6778987 A JP 6778987A JP S63234575 A JPS63234575 A JP S63234575A
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- Prior art keywords
- film
- layer
- pattern
- wiring
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title description 7
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- 230000001681 protective effect Effects 0.000 claims description 19
- 238000001259 photo etching Methods 0.000 abstract description 8
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 133
- 239000010410 layer Substances 0.000 description 55
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 239000001307 helium Substances 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 229910003087 TiOx Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- JLQFVGYYVXALAG-CFEVTAHFSA-N yasmin 28 Chemical compound OC1=CC=C2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1.C([C@]12[C@H]3C[C@H]3[C@H]3[C@H]4[C@@H]([C@]5(CCC(=O)C=C5[C@@H]5C[C@@H]54)C)CC[C@@]31C)CC(=O)O2 JLQFVGYYVXALAG-CFEVTAHFSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49888—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing superconducting material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0156—Manufacture or treatment of devices comprising Nb or an alloy of Nb with one or more of the elements of group IVB, e.g. titanium, zirconium or hafnium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は超電導回路のパターン形成方法に係り、特に超
電導集積回路の特性向上に好適な超電導回路のパターン
形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a pattern of a superconducting circuit, and particularly to a method of forming a pattern of a superconducting circuit suitable for improving the characteristics of a superconducting integrated circuit.
従来、超電導回路の多層配線パターンの平坦化方法は、
特公昭５８−６３０６号に代表されるように、第１層膜
パターンとパターン間絶縁膜を形成したのち、スパッタ
エツチング等の乾式エツチング法により表面を平坦化し
、層間絶縁膜の形成、第１層、第２層膜合用開口部の形
成、第２層パターンの形成を順次行なう方法である。Conventionally, the method for flattening multilayer wiring patterns of superconducting circuits is as follows:
As typified by Japanese Patent Publication No. 58-6306, after forming a first layer film pattern and an inter-pattern insulating film, the surface is flattened by a dry etching method such as sputter etching, and an interlayer insulating film is formed. , the formation of the opening for second layer film formation, and the formation of the second layer pattern are performed in this order.
また、超電導回路用抵抗素子製造方法は、最近、特願昭
６０−１０８２８８号で提案されているように、基板」
二にＷ、ＷＮ等の抵抗膜を直流マグネトロンスパッタ法
あるいは電子線蒸着法で形成したのち、抵抗素子用フォ
トレジストパターンを形成し、プラズマエツチング法あ
るいはイオンミリング法により抵抗膜をエツチングし、
さらにＳｉＯ等の保護ＩＮ３縁膜、Ｎｂ等の電極配線膜
を形成して、抵抗素子を形成する方法であった。In addition, as recently proposed in Japanese Patent Application No. 60-108288, a method for manufacturing a resistive element for a superconducting circuit has been developed using a substrate.
Second, a resistive film such as W or WN is formed by direct current magnetron sputtering or electron beam evaporation, a photoresist pattern for a resistive element is formed, and the resistive film is etched by plasma etching or ion milling.
Furthermore, a protective IN3 film made of SiO or the like and an electrode wiring film made of Nb or the like were formed to form a resistance element.
上記従来の多層パターンの平坦化技術は、１Ｍ毎に配線
を平坦化していく方法であり、第１ＦｒＪ膜を形成した
のち膜表面を大気中などに晒すため、該表面が変質し、
第］−１第２層間の電気的接合特性が悪くなるという問
題があった。これは超電導集積回路において特に顕著な
問題となる。Ｐｂ。The above-mentioned conventional multilayer pattern planarization technology is a method of planarizing the wiring every 1M, and after forming the first FrJ film, the film surface is exposed to the atmosphere, so the surface changes in quality.
]-1 There was a problem in that the electrical bonding characteristics between the second layer deteriorated. This is a particularly serious problem in superconducting integrated circuits. Pb.
Ｎｂ等の超電導配線膜を大気中に晒すと、表面に自然酸
化膜が形成され、これがトンネル障壁層となって第１−
１第２層間に流す超電導接合電流の低下を引き起こすと
いう問題があった。When a superconducting wiring film such as Nb is exposed to the atmosphere, a natural oxide film is formed on the surface, and this becomes a tunnel barrier layer.
There is a problem in that the superconducting junction current flowing between the first and second layers decreases.
また、」二記従来の抵抗素子の製造方法では、抵抗膜形
成後に抵抗素子パターンを加工するため、抵抗膜を大気
中に放置し、またフカｌ−レジスト膜等を表面に触れさ
ざるを得なかった。このため抵抗膜表面に酸化膜が形成
され、抵抗値が変化するという問題があった。またこの
酸化膜のため、フォトレジストと抵抗膜との接着力が低
下してフォトレジスト膜が剥離し、抵抗素子パターンの
形成が困難になるという問題点があった。これらの問題
は、表面に酸化膜が形成されやすいＭｏ、Ｔａ。In addition, in the conventional manufacturing method for resistive elements described in Section 2, the resistive element pattern is processed after the resistive film is formed, so the resistive film is left in the atmosphere, and the surface must be touched with a scaly resist film, etc. There wasn't. Therefore, there was a problem in that an oxide film was formed on the surface of the resistive film, resulting in a change in resistance value. Further, due to this oxide film, the adhesion between the photoresist and the resistive film decreases, causing the photoresist film to peel off, making it difficult to form a resistive element pattern. These problems are caused by Mo and Ta, which tend to form oxide films on their surfaces.
ＭｏＮ抵抗膜において顕著に発生した。This occurred significantly in the MoN resistive film.
第１の発明の目的は、配線間の電気接合特性を良好にし
得るかつ多層線を平坦化できる超電導集積回路のパター
ンの形成方法を供することにある。A first object of the invention is to provide a method for forming a pattern for a superconducting integrated circuit that can improve the electrical connection characteristics between wirings and flatten multilayer wiring.
第２の発明の目的は、抵抗膜表面の酸化を防止して抵抗
素子パターンの形成を容易にし、かつ抵抗値が変化しな
い超電導回路用抵抗素子を有した超電導回路のパターン
形成方法を提供することにある。A second object of the invention is to provide a method for forming a pattern of a superconducting circuit having a resistive element for a superconducting circuit that prevents oxidation of the surface of a resistive film, facilitates the formation of a resistive element pattern, and does not change the resistance value. It is in.
上記目的を達成するため、第１の発明では予め第１層配
線用の溝パターンを形成した基板上に、第１層配線膜と
第２層配線膜を連続して形成し、フォトレジストを塗布
したのち乾式エツチング法により、フォトレジストおよ
び該配線膜の凸部をエツチングして表面を平坦化する。In order to achieve the above object, in the first invention, a first layer wiring film and a second layer wiring film are successively formed on a substrate on which a groove pattern for the first layer wiring is formed in advance, and a photoresist is applied. Thereafter, the protrusions of the photoresist and the wiring film are etched by dry etching to flatten the surface.
次いでフォトエツチング法により第２層配線パターンを
形成して、該配線膜を乾式エツチングすることにより、
第２層配線を形成すると共に、第１層配線膜を該溝内に
残して第１層配線を形成する。Next, a second layer wiring pattern is formed by a photoetching method, and the wiring film is dry etched.
At the same time as forming a second layer wiring, a first layer wiring is formed by leaving the first layer wiring film in the trench.
また、上記目的を達成するため、第２の発明ではまず基
板」二にＭ ｏ Ｎ等の抵抗膜を形成し、さらにＳｉと
Ｔｊ、ＯｘあるいはＳｊＯとＴｉｄｘ等の２層膜からな
る保護絶縁膜を連続して形成する。In addition, in order to achieve the above object, in the second invention, a resistive film such as M o N is first formed on the substrate, and then a protective insulating film consisting of a two-layer film such as Si and Tj, Ox or SjO and Tidx is formed. are formed continuously.
こののち抵抗素子用フォトレジストパターンを形成し、
抵抗膜の加工、電極配線膜、保Ｍ膜の形成を行って抵抗
素子を形成する。After this, a photoresist pattern for the resistor element is formed,
A resistive element is formed by processing a resistive film, forming an electrode wiring film, and an M retaining film.
上記のごとく第１の発明では、予め基板上に第１層配線
用の溝パターンを形成し、かつ第１層配線膜と第２層配
線膜を一括して形成加工するため、平坦化された２層配
線が容易に形成できる。また第１層膜と第２層膜を連続
して形成するため、層間の電気的接合性の改善、特に従
来第１層膜表面に形成された酸化物等を極めて低減でき
、接合電流の低下を防止できる。As described above, in the first invention, the groove pattern for the first layer wiring is formed on the substrate in advance, and the first layer wiring film and the second layer wiring film are formed and processed at once, so that the flattened Two-layer wiring can be easily formed. In addition, since the first layer film and the second layer film are formed continuously, it is possible to improve the electrical connectivity between the layers, and in particular to significantly reduce the oxides etc. that are conventionally formed on the surface of the first layer film, reducing the junction current. can be prevented.
また、第２の発明では、抵抗膜とその保護絶縁膜を連続
して形成するため、大気中放置あるいは以後のフォトエ
ツチング等の工程における抵抗膜表面の酸化、すなわち
抵抗値の変化を防止できる。Furthermore, in the second invention, since the resistive film and its protective insulating film are formed continuously, oxidation of the resistive film surface, that is, change in resistance value, can be prevented during exposure to the atmosphere or subsequent steps such as photo etching.
また抵抗膜上ではなく保護絶縁膜上にフォトレジストパ
ターンを形成するため、抵抗膜表面の酸化によって生じ
ていたフォトレジストパターンの形成が困難という問題
も解消できる。Furthermore, since the photoresist pattern is formed on the protective insulating film rather than on the resistive film, the problem of difficulty in forming the photoresist pattern caused by oxidation of the resistive film surface can be solved.
以上のように、多層に積層される配線膜又は抵抗膜表面
の変質を防止できるので、超電導回路の電気特性を良好
に保つことができる。As described above, since deterioration of the surface of the wiring film or the resistive film stacked in multiple layers can be prevented, the electrical characteristics of the superconducting circuit can be maintained in good condition.
まず、第１の発明の一実施例を説明する。 First, an embodiment of the first invention will be described.
〔実施例１〕
本実施例は超電導集積回路の２層配線に適用した例で、
第１図に示す製作工程に従って説明する。[Example 1] This example is an example applied to two-layer wiring of a superconducting integrated circuit.
The explanation will be made according to the manufacturing process shown in FIG.
（１）Ｓｉ基板１上に熱酸化法により厚さ約６００ｎｍ
の５ｉ０２膜２を形成し、該表面にフォトエツチング法
および乾式エツチング法により、幅５μｍ、深さ１１０
０ｎの第１層パターン溝３を形成した（第１図（ａ））
。(1) Approximately 600 nm thick on Si substrate 1 by thermal oxidation method.
A 5i02 film 2 of
A first layer pattern groove 3 of 0n was formed (Fig. 1(a)).
.
（２）該基板上に第１層配線用Ｎｂ膜４を１１０５ｎの
厚さに、続いて第２層配線用Ｎｂ膜５を２００ｎｍの厚
さに、それぞれ直流マグネトロンスパッタ法により連続
して形成した。そしてこの上にフォトレジスト（５ｈｉ
ｐｌｅｙ社製、商品名ＡＺ１４７０）６を４００ｎｍの
厚さにスピンナーにより塗布した（第１図（ｂ））。(2) On the substrate, a first-layer wiring Nb film 4 with a thickness of 1105 nm and a second-layer wiring Nb film 5 with a thickness of 200 nm were successively formed by DC magnetron sputtering. . And on top of this, photoresist (5hi
AZ1470 (trade name) 6 manufactured by Play Inc. was applied to a thickness of 400 nm using a spinner (FIG. 1(b)).
（３）次いで該フォトレジスト膜および該Ｎｂ膜５をフ
ォトレジスト膜表面から５０５〜５１０ｎｍの深さまで
、乾式エツチング法によりエツチングした（第１図（Ｃ
））。このときエツチング装置として高周波プラズマエ
ツチング装置（日型アネルバ社製、ＤＥＭ−４５１型）
。(3) Next, the photoresist film and the Nb film 5 were etched by a dry etching method to a depth of 505 to 510 nm from the surface of the photoresist film (Fig. 1(C)
)). At this time, as an etching device, a high frequency plasma etching device (manufactured by Nikki Anelva Co., Ltd., model DEM-451) was used.
.
を用いた。was used.
代表的なエツチング条件は、導入ガスとしてＣＦ４を用
い、導入量は１００ｃｍ３／ｍｉｎ、ガス分圧は１３
、３ ｍ Ｐ ａ、印加電力は１００Ｗである。この条
件はフォトレジスト膜とＮｂ膜のエツチング速度が約３
２ｎｍ／ｍｉｎと、はぼ等しくなるため条件で、第１図
（ｃ）に示すように、エツチング後のＮｂ膜表面は平坦
になった。Typical etching conditions are: CF4 is used as the introduced gas, the amount introduced is 100 cm3/min, and the gas partial pressure is 13
, 3 mPa, and the applied power was 100W. Under these conditions, the etching rate of the photoresist film and Nb film is approximately 3
Under the condition that the etching rate was approximately equal to 2 nm/min, the surface of the Nb film after etching became flat as shown in FIG. 1(c).
（４）続いて、該基板上にフォトエツチング法に＝７−
より、フォトレジスト（Ａｚ１４７０）で線幅５μｍの
第２層配線用フォトレジストパターン７（マスクパター
ン）を形成した。そして該Ｎｂ膜４．５をマスクパター
ンをマスクとして基板表面までエツチングして、第１層
パターン溝３内に厚さ１１００ｎのＮｂ第１層配線８を
残すと同時に該Ｎｂ膜４，５よりなる第２層配線９を形
成した（第１図（ｄ））。エツチング装置は前述のもの
を用い、２６．６ｍＰａの ＣＦ４ガス雰囲気中で、１
００Ｗの高周波電力を印加した。(4) Subsequently, a second layer wiring photoresist pattern 7 (mask pattern) having a line width of 5 μm was formed using photoresist (Az1470) on the substrate by photoetching. Then, the Nb film 4.5 is etched to the substrate surface using the mask pattern to leave the Nb first layer wiring 8 with a thickness of 1100 nm in the first layer pattern groove 3, and at the same time, the Nb film 4.5 is made of the Nb films 4 and 5. A second layer wiring 9 was formed (FIG. 1(d)). The etching equipment described above was used, and 1
A high frequency power of 00 W was applied.
（５）最後に残ったフォトレジスト膜７をアセトンで溶
解除去して、２層配線パターンを完成した（第１図（ｅ
））。(5) The last remaining photoresist film 7 was dissolved and removed with acetone to complete a two-layer wiring pattern (Fig. 1(e)
)).
次に本発明により作製した配線間の超電導接合電流を４
．２°にの液体ヘリウム中で調べた結果、５μｍ口当り
３０ｍＡ以上の接合電流が得られた。Next, the superconducting junction current between the interconnects fabricated according to the present invention is 4
．． As a result of investigation in liquid helium at 2°, a junction current of 30 mA or more per 5 μm mouth was obtained.
一方１層毎に作製した従来の方法では、５μｍ口当り１
〜１００μＡであった。この結果から、接合電流低下の
原因となっていた第１層配線表面の酸化膜を極めて低減
できたことがわかる。On the other hand, in the conventional method of manufacturing each layer, 1
It was ~100 μA. This result shows that the oxide film on the surface of the first layer wiring, which was a cause of a decrease in junction current, was significantly reduced.
上記実施例では第１．第２層配線ともＮｂ膜で構成した
が、第１層配線膜をＮｂＮ、第２層配線膜をＮｂＮとＮ
ｂ膜の２層膜とするように、種々の配線材を組み合わせ
ることも可能である。また半導体集積回路等においても
本発明を適用できる。In the above embodiment, the first. Although both the second layer wiring was made of Nb film, the first layer wiring film was made of NbN, and the second layer wiring film was made of NbN and Nb.
It is also possible to combine various wiring materials so as to form a two-layer film of b film. The present invention can also be applied to semiconductor integrated circuits and the like.
例えばＡｆｌ配線膜を用いた場合、大気中に試料を晒す
従来法ではＡＱ膜表面に２〜３ｎｍの酸化膜が形成され
、これが１−ンネル障壁層となって配線間の接合電流を
低下させていたが、本発明によれば第１．第２層ＡＱ配
線膜を真空中で連続形成できるので、上述の酸、化膜の
形成を防止できる。超電導集積回路においては、第１層
配線膜を抵抗膜とすることも可能である。ちなみに第１
層膜をＭ ｏ Ｎ抵抗膜とし、第２層膜をＮｂ膜とした
場合、本発明によれば抵抗の配線となる第２層配線膜は
Ｍ ｏ Ｎ膜とＮｂ膜の２層膜となるが、配線電流（超
電導電流）はＮｂ膜部分でのみ流れるため、配線上特に
問題とならない。For example, when using an Afl wiring film, in the conventional method of exposing the sample to the atmosphere, a 2-3 nm thick oxide film is formed on the surface of the AQ film, which acts as a channel barrier layer and reduces the junction current between the wirings. However, according to the present invention, the first. Since the second layer AQ wiring film can be formed continuously in a vacuum, the formation of the above-mentioned acidic and chemical films can be prevented. In a superconducting integrated circuit, it is also possible to use a resistive film as the first layer wiring film. By the way, the first
When the layer film is a M o N resistance film and the second layer film is a Nb film, according to the present invention, the second layer wiring film that becomes the resistance wiring is a two-layer film of the M o N film and the Nb film. However, since the wiring current (superconducting current) flows only in the Nb film portion, there is no particular problem with the wiring.
〔実施例２〕
以下、第２の発明の実施例を第２図により説明する。抵
抗膜とその保護絶縁膜の形成は、スパッタ槽と蒸着槽を
有する真空薄膜形成装置を用いて行った。まず直径５ｃ
ｍのＳｊウェハ１０１上に熱酸化法により厚さ約３００
ｎｍの５ｉ０２膜１０２を形成した基板を該装置のスパ
ッタ槽側に設置し、該基板上に厚さ］、 ＯＯｎ ｍの
Ｍ ｏ Ｎ抵抗膜１０３を直流マグネトロンスパッタ法
により形成した。次いでこの試料を大気中に晒すことな
くスパッタ槽から蒸着槽側に移動し、Ｓ ｉ −Ｔｉｄ
ｘｉ護絶縁膜１０４として厚さ１５０ｎｍのＳｉ膜と厚
さ１〜５ｎｍのＴｉＯｘ膜を真空蒸着法により形成した
（第２図（ａ））。Ｍ ｏ Ｎ抵抗膜１０３は、真空槽
を２Ｘ１０−４Ｐａ以下まで真空排気したのち、２．６
ｍＰａの窒素ガスを含むアルゴンガスを５３０ｍＰａ導
入し、３５０ＶＸ２Ａの商科電力を印加して、１２．５
ｃｍＸ２５ｃｍのＭ。[Example 2] Hereinafter, an example of the second invention will be described with reference to FIG. 2. The resistive film and its protective insulating film were formed using a vacuum thin film forming apparatus having a sputtering tank and a vapor deposition tank. First, diameter 5c
The thickness of approximately 300 mm is deposited on the SJ wafer 101 by thermal oxidation.
A substrate on which a 5i02 film 102 with a thickness of 100 nm was formed was placed on the sputtering tank side of the apparatus, and an M o N resistive film 103 with a thickness of 00 nm was formed on the substrate by direct current magnetron sputtering. Next, this sample was moved from the sputtering tank to the evaporation tank without being exposed to the atmosphere, and S i -Tid
As the xi-protecting insulating film 104, a Si film with a thickness of 150 nm and a TiOx film with a thickness of 1 to 5 nm were formed by vacuum evaporation (FIG. 2(a)). The M o N resistive film 103 is formed by evacuating the vacuum chamber to 2×10 −4 Pa or less, and then applying the pressure to 2.6 Pa.
Introducing 530 mPa of argon gas containing mPa of nitrogen gas and applying commercial power of 350 V x 2 A to 12.5
M of cmX25cm.
ターゲットからＭｏをスパッタリングすることにより形
成した。このときのスパッタ速度は１．６ｎ ｍ ／
ｓであった。この条件で形成したＭ ｏ Ｎ膜で、液体
ヘリウム温度（４，２Ｋ）において０．２２μΩｍの抵
抗率が得られた。Ｓｉ膜はＭ ｏ Ｎ抵抗膜形成後７Ｘ
１０−５Ｐａ以下まで真空排気したのち２．６ Ｘ １
０−４Ｐ ａ以下の真空中でＷボー１−よりＳｉを蒸発
させて形成した。このＳｉ膜の液体ヘリウム温度（４，
２Ｋ）における抵抗率は約１００ＭΩｍで、Ｍ ｏ Ｎ
抵抗膜の抵抗率（０，２２μΩｍ）よりも十分大きく、
保護絶縁膜としての機能を十分満たすものであった。Ｔ
ｊＯＸ膜はフカ１〜レジスト膜との接着力を高めるため
のもので、Ｓｉ膜膜着着後０、８ ｍ Ｐ ａの酸化ガ
ス雰囲気中でＴｊ線を加熱蒸発させることにより形成し
た。It was formed by sputtering Mo from a target. The sputtering speed at this time was 1.6nm/
It was s. The M o N film formed under these conditions had a resistivity of 0.22 μΩm at liquid helium temperature (4.2 K). The Si film is 7X after forming the M o N resistive film.
After evacuating to 10-5 Pa or less, 2.6 x 1
It was formed by evaporating Si from a W bow 1- in a vacuum of 0-4 Pa or less. The liquid helium temperature of this Si film (4,
The resistivity at 2K) is about 100 MΩm, and M o N
Sufficiently larger than the resistivity of the resistive film (0.22 μΩm),
It sufficiently fulfilled its function as a protective insulating film. T
The jOX film is intended to enhance the adhesion between the adhesive film 1 and the resist film, and was formed by heating and evaporating the Tj line in an oxidizing gas atmosphere at 0.8 mPa after the Si film was deposited.
次にフォトエツチング法により、該試料上にフォトレジ
スト（Ｓｈｉｐｌｅｙ社製、商品名Ａ Ｚ １４７０、
以下フオトレジス１〜はこの型式を使用した）で抵抗素
子用のフォトレジストパターン１０５を形成したのち、
アルゴンガスを用いたイオンミリング法によりＳｊとＴ
ｉ ＯＸからなる保護絶縁膜］、 ０４をエツチング
した（第２１４１７１ （ｂ） ）。そして該レジスト
１０５をアセ１〜ンで溶解除去した（第２図（Ｃ））。Next, a photoresist (manufactured by Shipley, trade name AZ 1470,
After forming a photoresist pattern 105 for a resistor element (this type is used for photoresist 1 to below),
Sj and T by ion milling method using argon gas
A protective insulating film made of iOX], 04 was etched (No. 214171 (b)). The resist 105 was then dissolved and removed using acetone (FIG. 2(C)).
その後、該保護絶縁膜１０４上にフォトエッチング法に
より該抵抗素子の配線端子部を開口したフォトレジスト
パターン１０６を形成し、プラズマエツチング法により
該検品絶縁膜１０４をエツチングしく第２図（ｄ））
、該レジスｊ・１０６をアセトンで溶解除去した（第２
図（ｅ））。Thereafter, a photoresist pattern 106 is formed on the protective insulating film 104 using a photoetching method to open the wiring terminal portion of the resistor element, and the inspection insulating film 104 is etched using a plasma etching method (see FIG. 2(d)).
, the resist J・106 was dissolved and removed with acetone (second
Figure (e)).
次に厚さ２００ｎｍのＮｂ配線膜１０７を直流マグネト
ロンスパッタ法により形成しく第２図（ｆ））、フォト
エツチング法により配線用フカ１〜レジストパターン８
を形成したのち、プラズマエツチング法によりＮｂ配線
膜１０７をエツチングした（第２図（ｇ））。そして該
レジスＩ−１０８をアセトンで溶解除去したのち、厚さ
３００ｎｍのＳｉ保護膜１０９を真空蒸着法により形成
して。Next, a Nb wiring film 107 with a thickness of 200 nm is formed by direct current magnetron sputtering (FIG. 2(f)), and then by photo-etching, the Nb wiring film 107 is formed using a photoetching method.
After forming the Nb wiring film 107, the Nb wiring film 107 was etched by a plasma etching method (FIG. 2(g)). After the resist I-108 was dissolved and removed with acetone, a Si protective film 109 with a thickness of 300 nm was formed by vacuum evaporation.
Ｎｂ配線膜１０７とＭ ｏ Ｎ抵抗膜１０３の側壁部を
絶縁保護し、超電導回路用Ｍ ｏ Ｎ抵抗素子とそのＮ
ｂ配線を完成した（第２図（ｈ））。The side walls of the Nb wiring film 107 and the M o N resistance film 103 are insulated and protected, and the M o N resistance element for the superconducting circuit and its N
b wiring has been completed (Fig. 2 (h)).
本実施例によれば、Ｍ ｏ Ｎ抵抗膜形成直後と約２４
時間大気中に放置した後、およびフォトエツチング工程
等を経た抵抗素子完成後の抵抗率の変化は、いづれも０
．０５％以下の増加率であった。According to this example, immediately after the formation of the M o N resistive film and about 24
The change in resistivity after being left in the atmosphere for an hour and after the resistor element is completed after going through a photo-etching process, etc., is 0.
．． The increase rate was less than 0.05%.
一方従来法の場合は、それぞれ１〜４％および６〜１０
％抵抗率が増加していた。また、フォトレジスト膜が剥
離してパターン形成が困難になるという従来法の問題は
、本実施例で述べたようにＭ ｏ Ｎ抵抗膜上に直接フ
ォトレジストパターンを形成しないため、解消した。従
来法の場合、Ｍ。On the other hand, in the case of the conventional method, 1-4% and 6-10%, respectively.
% resistivity was increasing. In addition, the problem of the conventional method in which the photoresist film peels off and pattern formation becomes difficult has been solved because the photoresist pattern is not directly formed on the M o N resistive film as described in this embodiment. In the case of the conventional method, M.
Ｎ抵抗膜形成後、大気中に４時間放置すると５〜２０％
のフォトレジストパターン（以下５μｍ×３０μｍのパ
ターンの場合）が剥離し、８時間放置すると５０〜７５
％、１２時間以」二装置すると１００％剥離した。5-20% when left in the air for 4 hours after forming the N resistance film
The photoresist pattern (hereinafter in the case of a 5 μm x 30 μm pattern) peels off, and when left for 8 hours, it becomes 50 to 75
%, 100% peeling was achieved after 12 hours or more.
本実施例では抵抗膜としてＭ ｏ Ｎ膜を用いた例を示
したが、Ｍｏ膜、Ｔａ膜についても同様の結果が得られ
た。また保護絶縁膜としてＳｊのがわりにＳｉ膜を用い
ても同様の結果が得られた。In this example, an example was shown in which a Mo N film was used as the resistive film, but similar results were obtained with Mo films and Ta films. Similar results were also obtained when a Si film was used instead of Sj as the protective insulating film.
以上説明したごとく、第１の発明によれば第１層配線と
第２層配線を一括して形成、平坦化加工、配線加工を行
なえるので、平坦化２層配線が容易に形成できる。また
第１層配線と第２層配線を連続形成できるので、層間の
電気的接合特性、特に接合電流の低下を防止できる。As described above, according to the first invention, the first layer wiring and the second layer wiring can be formed, planarized, and wire processed all at once, so that a flattened two-layer wiring can be easily formed. Furthermore, since the first layer wiring and the second layer wiring can be formed continuously, it is possible to prevent a decrease in electrical bonding characteristics between layers, particularly in junction current.
また、第２発明によれば、超電導回路用抵抗素子の製造
において、
（１）抵抗膜とその保護絶縁膜を連続形成して抵抗膜表
面の酸化を防止したため、これに起因する抵抗値の変化
を従来と比して１００分の５以下に低減できた、
（２）抵抗膜上にかえて保護絶縁膜上にフォトレジスト
パターンを形成できるため、フォトレジスト膜の剥離は
なくなり、パターン形成が容易になった・
すなわち、回路部材の表面の変質を防止し超電導回路の
電気的特性を良好に保つことができる。Further, according to the second invention, in manufacturing a resistive element for a superconducting circuit, (1) a resistive film and its protective insulating film are continuously formed to prevent oxidation of the resistive film surface, resulting in a change in resistance value caused by this; (2) Since the photoresist pattern can be formed on the protective insulating film instead of on the resistive film, there is no peeling of the photoresist film and pattern formation is easy. In other words, deterioration of the surface of the circuit member can be prevented and the electrical characteristics of the superconducting circuit can be maintained in good condition.
第１図は本発明の実施例１における製造工程を示す集積
回路の断面図である。
第２図は本発明の実施例２における製造工程を示す抵抗
素子の断面図である。
１・・・Ｓｉ基板、２・・・５ｉ０２膜、３・・・第１
層パターン溝、４・・・第１層配線用Ｎｂ膜、５・・・
第２層配線用Ｎｂ膜、６・・・フォトレジスト、７・・
・フォトレジストパターン、８・・・Ｎｂ第１層配線、
９・・・Ｎｂ第２層配線、１０１・・・Ｓｉウェハ、１
０２・・・５ｉ０２膜、１０３・・・Ｍ ｏ Ｎ抵抗膜
、１０４・・・５Ｌ−ＴｉＯｘ保護絶縁膜、１０５，１
０６，１０８・・・フォトレジストパターン、１０７・
・・Ｎｂ配線膜、１０９・・・Ｓｉ保護膜。FIG. 1 is a cross-sectional view of an integrated circuit showing the manufacturing process in Example 1 of the present invention. FIG. 2 is a cross-sectional view of a resistance element showing the manufacturing process in Example 2 of the present invention. 1...Si substrate, 2...5i02 film, 3...first
Layer pattern groove, 4... Nb film for first layer wiring, 5...
Nb film for second layer wiring, 6... photoresist, 7...
・Photoresist pattern, 8...Nb first layer wiring,
9...Nb second layer wiring, 101...Si wafer, 1
02...5i02 film, 103...M o N resistance film, 104...5L-TiOx protective insulating film, 105,1
06,108...Photoresist pattern, 107.
...Nb wiring film, 109...Si protective film.
Claims (1)
ーン形成方法。 （１）基板表面に第１層パターン用の溝を形成する工程
、 （２）前記基板上に前記溝の深さよりも厚い第１層膜を
形成し、前記第１層膜上に第２層膜を形成する工程、 （３）前記第２層膜上にフォトレジストを塗布する工程
、 （４）前記フォトレジストおよび前記第２層膜をエッチ
ングして、前記第２層膜表面を平坦化する工程、 （５）前記平坦化された第２層膜表面に第２層パターン
用のフォトレジストよりなるマスクパターンを形成する
工程、 （６）前記マスクパターンをマスクとして、前記第２層
膜および前記第１層膜を基板表面までエッチングして、
前記溝内に前記第１層膜を残すことにより、第１層パタ
ーンおよび第２層パターンを形成する工程。 ２、下記工程を含むことを特徴とする超電導回路のパタ
ーン形成方法。 （１）基板表面に抵抗膜を形成する工程、 （２）前記工程（１）に連続して前記抵抗膜上に保護絶
縁膜を形成する工程、 （３）前記保護絶縁膜上に、フォトレジストパターンを
形成する工程、 （４）前記保護絶縁膜を前記フォトレジストパターンを
マスクとしてエッチングする工程、 （５）前記保護絶縁膜上に延在する配線膜を形成する工
程、 （６）前記配線膜をパターン化する工程、 （７）前記配線膜上に保護膜を形成する工程。[Scope of Claims] 1. A method for forming a pattern of a superconducting circuit, characterized by including the following steps. (1) Forming a groove for a first layer pattern on the substrate surface; (2) Forming a first layer film thicker than the depth of the groove on the substrate, and forming a second layer on the first layer film. (3) applying a photoresist on the second layer; (4) etching the photoresist and the second layer to planarize the surface of the second layer; (5) forming a mask pattern made of photoresist for a second layer pattern on the planarized surface of the second layer film; (6) using the mask pattern as a mask, forming the second layer film and the second layer film; Etching the first layer film to the substrate surface,
forming a first layer pattern and a second layer pattern by leaving the first layer film in the groove; 2. A method for forming a pattern of a superconducting circuit, characterized by including the following steps. (1) Forming a resistive film on the surface of the substrate; (2) Forming a protective insulating film on the resistive film following the step (1); (3) Applying photoresist on the protective insulating film. (4) etching the protective insulating film using the photoresist pattern as a mask; (5) forming a wiring film extending on the protective insulating film; (6) the wiring film. (7) forming a protective film on the wiring film;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62067789A JPS63234575A (en) | 1987-03-24 | 1987-03-24 | Formation of pattern of superconducting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62067789A JPS63234575A (en) | 1987-03-24 | 1987-03-24 | Formation of pattern of superconducting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63234575A true JPS63234575A (en) | 1988-09-29 |
Family
ID=13355071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62067789A Pending JPS63234575A (en) | 1987-03-24 | 1987-03-24 | Formation of pattern of superconducting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63234575A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6464339A (en) * | 1987-09-04 | 1989-03-10 | Toshiba Corp | Semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5979584A (en) * | 1982-10-29 | 1984-05-08 | Hitachi Ltd | Resistor fot josephson integrated circuit |
| JPS6143488A (en) * | 1984-08-08 | 1986-03-03 | Agency Of Ind Science & Technol | Manufacture of superconductive contact |
| JPS61115360A (en) * | 1984-11-10 | 1986-06-02 | Agency Of Ind Science & Technol | Manufacture of josephson integrated circuit |
| JPS61241988A (en) * | 1985-04-19 | 1986-10-28 | Agency Of Ind Science & Technol | Manufacture of josephson integrated circuit |
-
1987
- 1987-03-24 JP JP62067789A patent/JPS63234575A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5979584A (en) * | 1982-10-29 | 1984-05-08 | Hitachi Ltd | Resistor fot josephson integrated circuit |
| JPS6143488A (en) * | 1984-08-08 | 1986-03-03 | Agency Of Ind Science & Technol | Manufacture of superconductive contact |
| JPS61115360A (en) * | 1984-11-10 | 1986-06-02 | Agency Of Ind Science & Technol | Manufacture of josephson integrated circuit |
| JPS61241988A (en) * | 1985-04-19 | 1986-10-28 | Agency Of Ind Science & Technol | Manufacture of josephson integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6464339A (en) * | 1987-09-04 | 1989-03-10 | Toshiba Corp | Semiconductor device |
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