JPS63226072A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63226072A JPS63226072A JP5952187A JP5952187A JPS63226072A JP S63226072 A JPS63226072 A JP S63226072A JP 5952187 A JP5952187 A JP 5952187A JP 5952187 A JP5952187 A JP 5952187A JP S63226072 A JPS63226072 A JP S63226072A
- Authority
- JP
- Japan
- Prior art keywords
- threshold voltage
- electron beam
- region
- layer
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000010894 electron beam technology Methods 0.000 claims abstract description 27
- 238000000137 annealing Methods 0.000 claims abstract description 16
- 230000003247 decreasing effect Effects 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 238000011084 recovery Methods 0.000 abstract description 2
- 229920006395 saturated elastomer Polymers 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 45
- 239000012535 impurity Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に関し、さらに詳し
くは、主に電力用スイッチング素子として用いられる堅
型ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏ
ｌａｒＴｒａｎｓｉｓｔｏｒ）の製造方法に係るもので
ある。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device.
larTransistor).
近年、この種の電力用スイッチング素子には、従来から
一般に用いられてきたバイポーラトランジスタに代わる
ものとして、その高速性、および制御回路の簡略化が可
能であるなどの利点を有することから、いわゆる、堅型
パワーＭＯ９ＦＥＴ（ＭＯ３Ｆｉｌｅｄ Ｅｆｆｅｃｔ
Ｔｒａｎｓｉｓｔｏｒ）へｃ７）移行が注目されてい
る。しかしながら、一方で、５００Ｖ以上での高耐圧の
堅型パワーＭＯＳ ＦＥＴにおいては、必然的にそのオ
ン抵抗が高くなって、大電流を流すことが難かしくなる
と云う不利がある。In recent years, this type of power switching element has been used as an alternative to the conventionally commonly used bipolar transistor, as it has advantages such as high speed and simplification of the control circuit. Rigid power MO9FET (MO3Filed Effect
c7) is attracting attention. However, on the other hand, a rigid power MOS FET with a high withstand voltage of 500 V or more has the disadvantage that its on-resistance inevitably becomes high, making it difficult to flow a large current.
そこで、この点を解消するための電力用スイッチング素
子として、先の１９８１年に、米国ＲＣＡ社から、特開
昭５６−１５０８７０号公報として示される堅型ＩＧＢ
Ｔが提案された。この堅型ＩＧＥＴは、ドレイン領域に
ソース領域とは逆の導電型層を形成することにより、こ
の逆導電型層から高抵抗層への注入を起こさせ、高抵抗
層に伝導度変調を生じさせて、オン抵抗を下げるように
したものである。Therefore, as a power switching element to solve this problem, in 1981, RCA Corporation of the United States proposed a rigid IGB disclosed in Japanese Patent Application Laid-Open No. 56-150870.
T was proposed. In this rigid IGET, by forming a layer of conductivity type opposite to that of the source region in the drain region, injection is caused from this opposite conductivity type layer to the high resistance layer, causing conductivity modulation in the high resistance layer. Therefore, the on-resistance is lowered.
第４図にこの提案に係る堅型ＩＧＢＴの基本的な構成を
示す。FIG. 4 shows the basic configuration of the rigid IGBT according to this proposal.
すなわち、この第４図従来例構成において、符号ｌは１
０１９／ｃゴ程度の高濃度ダシリコン基板であり、この
ダシリコン基板ｌ上にエビタギシャル成長などにより高
濃度ｎ＋層２を形成させ、また、この高濃度ｎ＋層２上
に低不純物濃度のｎ一層３を形成させ、さらに、このｎ
一層３の主表面上にあって、ＤＳＡ（Ｄｉｆｆｕｓｅｄ
Ｓｅｌｆ−Ａｌｉｇｎｍｅｎｔ）法により ｐウェル
層４と同層４中へのｎ＋型ソース層５とを選択的に形成
させる。That is, in the conventional configuration shown in FIG. 4, the symbol l is 1.
A high concentration n+ layer 2 is formed on this silicon substrate l by epitaxial growth, etc., and an n layer 3 with a low impurity concentration is formed on this high concentration n+ layer 2. furthermore, this n
On the main surface of layer 3, the DSA (Diffused
A p-well layer 4 and an n+ type source layer 5 in the same layer 4 are selectively formed by a self-alignment method.
そして、前記１１ＳＡ法では、 ｐウェルＭ４を形成す
るための拡散窓をして、ｎ＋型ソース層５を形成するた
めの拡散窓の一部として用いるために、チャンネル領域
θが素子のあらゆる部分で一定となるように、ｎ１型ソ
一ス層５を形成できる。In the 11SA method, in order to use the diffusion window for forming the p-well M4 as a part of the diffusion window for forming the n+ type source layer 5, the channel region θ is formed in all parts of the device. The n1 type source layer 5 can be formed so as to be constant.
ついで、チャンネル領域６上にゲート絶縁膜７を介して
ゲート電極８を形成させ、また、ｎ１型ン一ス層５とｐ
ウェル層４とを同時にオーミックコンタクトするように
ソース電極９を形成させ、さらに、ダシリコン基板１の
他面にドレイン電極１０を形成させ、このようにして目
的とする堅型ＩＧＢＴＵを得ているのである。Next, a gate electrode 8 is formed on the channel region 6 with a gate insulating film 7 interposed therebetween, and the n1 type conductor layer 5 and the p
A source electrode 9 is formed to make ohmic contact with the well layer 4 at the same time, and a drain electrode 10 is further formed on the other surface of the silicon substrate 1, thus obtaining the intended rigid IGBTU. .
従って、前記構成による堅型ＩＧＢＴＩＩの場合にあっ
ては、ｎ“型ソース層５からチャンネル領域６を通って
ｎ一層３に注入される電子電流に対し、ダシリコン基板
１から高濃度ｎ１層２を介してｎ一層３へ正孔注入を生
じ、この結果、高抵抗を有するｎ″′′層３導度変調を
起こして低抵抗化を図り得るのである。Therefore, in the case of the hard type IGBT II having the above configuration, the high concentration n1 layer 2 from the silicon substrate 1 is Through this, holes are injected into the n layer 3, and as a result, the conductivity of the n'''' layer 3, which has a high resistance, is modulated and the resistance can be lowered.
しかしながら、前記従来例構成による竪Ｗ ＩＧＢＴＵ
では、一方でこの堅型ＩＧＢＴＩＩをターンオフさせた
とき、高濃度ｎ＋暦２に注入された残留正孔のために、
ターンオフ時間が長くなると云う問題点がある。However, the vertical W IGBTU according to the conventional configuration
On the other hand, when this rigid IGBTII is turned off, due to the residual holes injected into the high concentration n+ calendar 2,
There is a problem that the turn-off time becomes longer.
こ−で、一般に堅型ｒＧＢＴ１１においては、高濃度ｎ
一層２内での前記残留正孔のライフタイムを制御するた
めに１重金属や電子線などの放射線照射などをなしてお
り、特に電子線照射による手段が、ライフタイムの制御
性の良さ、およびオン電圧とターンオフ時間の相関の良
さによって採用されている。Therefore, in general, in rigid rGBT11, high concentration n
In order to control the lifetime of the residual holes in the layer 2, irradiation with heavy metals, electron beams, etc. is used. In particular, electron beam irradiation provides good controllability of the lifetime and It is adopted because of the good correlation between voltage and turn-off time.
しかし、前記電子線照射方法によるときは、その電子線
照射によってＭＯＳ部のゲート絶縁膜７がダメージを受
は易く、この種の堅型ＩＧＢＴＩＩの重要な特性の一つ
であるゲートしきい値電圧ｖＧＳ（ｔｈ）が大幅に低下
することになると云う不都合があった。However, when using the electron beam irradiation method, the gate insulating film 7 of the MOS section is easily damaged by the electron beam irradiation, and the gate threshold voltage is one of the important characteristics of this type of hard IGBTI. There was the disadvantage that vGS(th) would be significantly reduced.
この発明は従来のこのような問題点を解消するためにな
されたものであって、その目的とするところは、製造後
においてもゲートしきい値電圧特性を低下させることの
ない、この種の半導体装置の製造方法、こ−では堅型Ｉ
Ｃ８丁の製造方法を提供することである。This invention was made to solve these conventional problems, and its purpose is to develop a semiconductor of this type that does not deteriorate the gate threshold voltage characteristics even after manufacturing. The manufacturing method of the device, in this case rigid type I
The purpose of the present invention is to provide a method for manufacturing C8.
前記目的を達成するために、この発明に係る半導体装置
の製造方法は、チャンネル領域の形成時に、まず、その
表面濃度を、素子構成のしきい値電圧がお覧よそ５〜１
０ｖ程度になるように設定させ、ついで、同表面側から
電子線を照射後、アニール処理して、電子線照射時に低
下したしきい値電圧を、お−よそ２〜５Ｖ程度まで回復
させるようにしたものである・
〔作 用〕
すなわち、この発明においては、中間段階での素子構成
に電子線照射をなして製造終了した後における素子構成
のしきい値電圧を、所期の値であるお＼よそ２〜５Ｖの
範囲に維持できると共に、高温度によるしきい値電圧の
低減に対しても、最低のしきい値電圧を保持し得るので
ある。In order to achieve the above object, in the method of manufacturing a semiconductor device according to the present invention, when forming a channel region, first, the surface concentration of the channel region is adjusted so that the threshold voltage of the device structure is approximately 5 to 1.
Then, after irradiating the same surface side with an electron beam, an annealing treatment is performed to recover the threshold voltage, which decreased during electron beam irradiation, to approximately 2 to 5 V. [Function] That is, in the present invention, the device structure at an intermediate stage is irradiated with an electron beam, and the threshold voltage of the device structure after manufacturing is completed is set to the desired value. It is possible to maintain the voltage within the range of about 2 to 5 V, and even when the threshold voltage is reduced due to high temperature, the lowest threshold voltage can be maintained.
以下、この発明に係る半導体装置の製造方法の一実施例
につき、第１図ないし第３図を参照して詳細に説明する
。Hereinafter, one embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 to 3.
第１図はこの実施例方法を適用した堅型ＩＧＢＴの概要
構成を示す断面図である。FIG. 1 is a sectional view showing the general structure of a rigid IGBT to which this embodiment method is applied.
すなわち、この実施例装置の場合にも、ダシリコン基板
２１上には、エピタキシャル成長などにより高儂度１層
２２．および低不純物濃度のｎ一層２３を順次に形成さ
せ、かつこのｎ一層２３の主表面上に、ＤＳＡ法により
ｐウェル層２４．および同層２４中へのｎ＋型ソース
層２５とを選択的に形成させてチャンネル領域２Ｂを得
る。そしてこのとき、このチャンネル領域２６の表面濃
度をして、素子における電子線照射前のしきい値電圧が
５〜１０ｖ程度になるように設定しておくのである。That is, in the case of this embodiment device as well, a high-temperature single layer 22. is formed on the silicon substrate 21 by epitaxial growth or the like. and a low impurity concentration n-type layer 23 are sequentially formed, and on the main surface of this n-type layer 23, a p-well layer 24 is formed by the DSA method. Then, an n+ type source layer 25 is selectively formed in the same layer 24 to obtain a channel region 2B. At this time, the surface concentration of the channel region 26 is set so that the threshold voltage of the element before electron beam irradiation is approximately 5 to 10V.
ついで、チャンネル領域２６上にゲート絶縁膜２７を介
してゲート電極２８を、ｎ＋型ンース層２５と ｐウェ
ル層２４とを同時にオーミックコンタクトするようにソ
ース電極２８を、ダシリコン基板２１の他面にドレイン
電極３０をそれぞれに形成させた上で、電子線を照射す
ると共に、かつ熱処理して、素子のしきい値電圧が２〜
５Ｖ程度になるようにしたものである。Next, a gate electrode 28 is placed on the channel region 26 via the gate insulating film 27, a source electrode 28 is placed in ohmic contact with the n+ type source layer 25 and the p well layer 24, and a drain is placed on the other side of the silicon substrate 21. After forming the electrodes 30 on each of them, electron beam irradiation and heat treatment are performed to raise the threshold voltage of the device to 2 to 2.
The voltage is set to about 5V.
従って、前記のようにして製造された実施例構成による
堅型ＩＧＢＴＩＩにおいては、装置の製造後にあって２
〜５Ｖ程度の範囲のしきい値電圧ｖＧＳ（ｔｈ）が得ら
れ、温度の経時変化に対しても、このしきい値電圧Ｖ。Therefore, in the rigid IGBT II with the embodiment structure manufactured as described above, two
A threshold voltage vGS(th) in the range of ~5V is obtained, and this threshold voltage V remains constant even when the temperature changes over time.
５（ｔｈ）は殆んど変動することがない。5(th) hardly changes.
そしてまた、通常、考えられる１０ｍＶ／’０程度の高
温度Ｖ。５（ｔｈ）の低減に対しても、 １５０℃の高
温において、最低０．７ｖ程度の値を保証できるのであ
る。Also, a high temperature V of about 10 mV/'0 is normally considered. Even with a reduction of 5(th), a minimum value of about 0.7V can be guaranteed at a high temperature of 150°C.
こ＼で、前記した従来例構成におけるように、電子線照
射前に設定されたしきい値電圧Ｖ。５（ｔｈ）が２〜５
Ｖ程度であると、電子線照射後に７二−ルしても、この
しきい値電圧ｖＧＳ（ｔｈ）が１〜２．５Ｖ程度までし
か回復せず、その下限値であるＩＶでは、１０ｍＶ／’
０程度までの温度低減率を考慮するとき、１５０℃程度
の高温の場合にはノーマリ−オン状態となってしまい、
この堅型ＩＧＢＴの制御が不能になる。Here, as in the conventional configuration described above, the threshold voltage V is set before electron beam irradiation. 5(th) is 2 to 5
If it is about V, this threshold voltage vGS(th) will only recover to about 1 to 2.5V even after 7 hours after electron beam irradiation, and at the lower limit of IV, it will be 10mV/ '
When considering the temperature reduction rate down to about 0, at a high temperature of about 150℃, it will be in a normally on state,
This hard IGBT becomes uncontrollable.
そして、前記従来例構成での電子線照射前の初期しきい
値電圧ｖＧＳ（ｔｈ）を２〜５Ｖ程度に設定するのには
、この実施例構成の第１図を参考にして、チャンネル領
域２８部を１〜２ Ｘ １０１７ｃｍ−３の表面濃度に
するため、 １〜２ Ｘｌ０１４／ｃｒｎ”での９例え
ば、Ｂ＋のイオン注入がなされる。しかして、この場合
」こは、ｎ＋型ソース層２５の直下のｐウェル領域２４
の濃度が低下することによるところの、各層２５，２４
゜２３．２１でのｎｐｎｐサイリスタ領域のラッチアッ
プが問題になるために、通常、符号２４で示したような
ラッチアップ対策用の１領域の形成を必要とするのであ
る。To set the initial threshold voltage vGS(th) before electron beam irradiation in the conventional configuration to about 2 to 5V, refer to FIG. In order to achieve a surface concentration of 1-2 X 1017 cm-3 in the n+ type source layer 25, for example, B+ ion implantation is performed at 1-2 Xl014/crn. p-well region 24 directly under
Each layer 25, 24 due to a decrease in the concentration of
Since the latch-up of the npnp thyristor region at 23.21°C becomes a problem, it is usually necessary to form a region as shown by the reference numeral 24 to prevent latch-up.
しかして、このような従来例構成に対し、この実施例構
成の場合には、電子線照射前の初期しきい値電圧ｖｃｓ
（ｔｈ）を５〜ＩＯＶ程度に高く設定しているために、
前記したチャンネル領域２６部を３〜５Ｘ １０１７ｃ
ｍ−３の表面濃度にし得て、ｎ”ｆｆｉソース層２５の
直下のｐウェル領域２４の濃度が高くなり、これによっ
て、ラフチアツブ対策用の１領域を形成せずに済み、偽
って製造プロセスの簡略化もまた可能になるのである。However, in contrast to such a conventional configuration, in the case of this embodiment configuration, the initial threshold voltage vcs before electron beam irradiation
Because (th) is set as high as 5 to IOV,
26 parts of the channel area described above are 3 to 5X 1017c
m-3 surface concentration, and the concentration of the p-well region 24 directly under the n''ffi source layer 25 becomes high, thereby eliminating the need to form a region for preventing rough lumps and falsely improving the manufacturing process. Simplification is also possible.
次に、この実施例方法による具体例について述べる。Next, a specific example of this embodiment method will be described.
第２図（ａ）ないしくｄ）はこの実施例方法を適用した
堅型ＩＧＢ↑の製造態様の概要を工程順に示すそれぞれ
断面図である。FIGS. 2(a) to 2(d) are cross-sectional views showing an overview of the manufacturing method of the rigid IGB↑ to which the method of this embodiment is applied in order of steps.
すなわち、この実施例方法の場合にあっては、まず、０
．０１Ω−Ｃ１程度のダ型シリコン基板２１の主面上に
、０．１Ω−ｃｍ程度のｎ＋不純物エピタキシャル層か
らなる高濃度１１層２２を約２０ｇｍの厚さに形成させ
、かつこの高濃度ｎ＋層２２上に、５０Ω−Ｃ■程度の
低不純物濃度のｎ一層２３を約１１００ｐの厚さに形成
させる（第２図（ａ））。That is, in the case of this embodiment method, first, 0
．． On the main surface of the Da type silicon substrate 21 of about 0.1 Ω-C1, 11 high-concentration layers 22 consisting of an n+ impurity epitaxial layer of about 0.1 Ω-cm are formed to a thickness of about 20 gm, and this high-concentration n+ layer An n layer 23 having a low impurity concentration of about 50 Ω-C2 is formed on the layer 22 to a thickness of about 1100 p (FIG. 2(a)).
ついで、前記ｎ一層２３の表面を酸化させることにより
、約１０００〜１５００λの厚さのゲート絶縁膜２７を
形成させたのち、その上に約５０００λの厚さのポリシ
リコンからなるゲート電極２８を形成させる。また、そ
の後、このゲート電極２日をマスクにしてイオン注入な
どの手段により、約５Ｘ １０１４／ｃｒｎ’のＢ＋を
ドープし、かつ拡散によって約１０ｇｍ程度の深さのｐ
ウェル層２４を選択的に形成させ、さらに、ゲート電極
２８による窓の中央部のみを絶縁膜で覆い、これらのゲ
ート電極２８および絶縁膜をマスクにしてＡｓやリンを
拡散し、 ｐウェル層２４中にｎ＋型ソース層２５を選
択的に形成させてチャンネル領域２６を得る（同図（ｂ
））。Next, by oxidizing the surface of the n-layer 23, a gate insulating film 27 with a thickness of about 1000 to 1500λ is formed, and then a gate electrode 28 made of polysilicon with a thickness of about 5000λ is formed thereon. let Then, using this gate electrode as a mask, B+ is doped at about 5X 1014/crn' by means such as ion implantation, and a p-type layer is doped to a depth of about 10 gm by diffusion.
The well layer 24 is selectively formed, and further, only the central part of the window formed by the gate electrode 28 is covered with an insulating film, and As and phosphorus are diffused using the gate electrode 28 and the insulating film as a mask to form the p-well layer 24. An n+ type source layer 25 is selectively formed therein to obtain a channel region 26 (see (b) in the same figure).
)).
さらに、前記ｎ＋型ソース層２５とｐウェル層２４とを
同時にオーミックコンタクトするようにしてソース電極
２８を形成させ・、また、前記ダシリコン基板２１の他
面にはドレイン電極３０をそれぞれに形成させる（同図
（Ｃ））、こへで、このようにして得た中間段階の素子
構成の初期しきい値電圧ｖＧＳ（ｔｈ）は５〜ＩＱＶ程
度である。Furthermore, a source electrode 28 is formed by simultaneously bringing the n+ type source layer 25 and the p well layer 24 into ohmic contact, and a drain electrode 30 is formed on the other surface of the silicon substrate 21, respectively. (C) of the same figure, the initial threshold voltage vGS(th) of the intermediate stage element configuration thus obtained is about 5 to IQV.
そしてまた、前記中間段階での素子構成に対しては、続
いて、５×１０ 〜８×１０１４ｃｍ−２程度の照耐量
の電子線を照射させ（同図（ｄ））、その後、温度約３
００℃程度で、おへよそ２〜５時間程度アニール処理し
て、前記第１図に示した堅型ＩＧＢＴを完成する。Furthermore, the element configuration at the intermediate stage is then irradiated with an electron beam having an irradiation capacity of about 5 x 10 to 8 x 1014 cm-2 (see figure (d)), and then at a temperature of about 3
The rigid IGBT shown in FIG. 1 is completed by annealing at about 00° C. for about 2 to 5 hours.
しかして、この場合、第３図に示されている通り、前記
電子線の照射後のしきい値電圧ｖＧＳ（ｔｈ）は、−４
〜５Ｖ程度まで低下するが、その後のアニール処理に伴
ない２〜５Ｖ程度まで回復する。すなわち、このアニー
ル処理に伴なって、ターンオフ時間は、アニール処理時
間と共に徐々に回復し、一方、しきい値電圧Ｖ。５（ｔ
ｈ）は、その回復がお−よそ２〜５時間程度で飽和して
しまう、（７”１つて、このアニール処理は、温度約３
００℃程度で、 ２〜５時間程度行なうことが望ましい
。In this case, as shown in FIG. 3, the threshold voltage vGS(th) after irradiation with the electron beam is -4
Although it decreases to about 5 V, it recovers to about 2 to 5 V with the subsequent annealing process. That is, with this annealing treatment, the turn-off time gradually recovers as the annealing treatment time increases, while the threshold voltage V. 5(t
h), the recovery is saturated in about 2 to 5 hours (7"), and this annealing process is performed at a temperature of about 3.
It is desirable to carry out the heating at about 00°C for about 2 to 5 hours.
すなわち９以上のようにして、目的とするところの、前
記作用、効果を有する所期の堅型ＩＧＢＴを製造し得る
のである。That is, as described above, it is possible to manufacture the desired rigid IGBT having the desired functions and effects described above.
なお、前記実施例方法においては、素子構成各部の導電
形をそれぞれに特定した場合について述べたが、これら
を逆の導電形にした場合にも適用できて、同様な作用、
効果を得られることは勿論である。In addition, in the above-mentioned example method, the case where the conductivity type of each component part of the element is specified respectively is described, but it can also be applied to the case where these are made to be the opposite conductivity type, and the same effect,
Of course, it is effective.
以上詳述したようにこの発明によれば、相互に逆の導電
形で直列に隣接するソース領域、ウェル領域、基体領域
、およびドレイン領域を有してサイリスタ構成とされ、
かつソース領域とウェル領域との表面に、 ＤＳＡ法に
よって自己整合的にチャンネル領域を形成させ、チャン
ネル領域にゲート絶縁膜を介して形成されるゲート電極
により制御可能にした堅型ＩＧＢＴにおいて、まず、チ
ャンネル領域の形成時に、このチャンネル領域の表面濃
度を、素子構成のしきい値電圧がお〜よそ５〜ｌＯｖ程
度になるように設定させ、ついで、同表面側から電子線
を照射後、アニール処理して、電子線照射時に低下した
しきい値電圧を、お覧よそ２〜５Ｖ程度まで回復させる
ようにしたから、中間段階での素子構成に電子線照射を
なして製造終了した後のしきい値電圧を、常時、所定の
値であるところの、お−よそ２〜５Ｖの範囲に維持し得
ると共に、高温度によるしきい値電圧の低減に対しても
、最低のしきい値電圧を効果的に保持でき、しかも、こ
の種のサイリスタ構成におけるラッチアップ対策をも自
動的に講することができて、製造工程自体の簡略化をも
図り得るなどの優れた特長を有するものである。As described in detail above, according to the present invention, a thyristor is formed by having a source region, a well region, a base region, and a drain region adjacent in series and having mutually opposite conductivity types,
In a rigid IGBT in which a channel region is formed in a self-aligned manner on the surfaces of a source region and a well region by the DSA method, and can be controlled by a gate electrode formed in the channel region via a gate insulating film, first, When forming the channel region, the surface concentration of this channel region is set so that the threshold voltage of the device structure is approximately 5 to 1 Ov, and then, after irradiation with an electron beam from the same surface side, annealing treatment is performed. As a result, the threshold voltage, which had decreased during electron beam irradiation, was restored to approximately 2 to 5 V, so that the threshold voltage after the device configuration was irradiated with electron beams at an intermediate stage and manufacturing was completed. The value voltage can always be maintained at a predetermined value in the range of approximately 2 to 5 V, and the lowest threshold voltage can be effectively maintained even when the threshold voltage is reduced due to high temperature. Furthermore, it has excellent features such as being able to automatically take measures against latch-up in this type of thyristor configuration and simplifying the manufacturing process itself.
第１図はこの発明に係る半導体装置の製造方法の一実施
例を適用した堅型ＩＧＢＴの概要構成を示す断面図、第
２図（ａ）ないしくｄ）は同上堅型ＩＧＢＴの製造態様
の概要を工程順に示すそれぞれ断面図、第３図は同上方
法でのアニール処理時におけるしきい値電圧、およびタ
ーンオフ時間と、アニール処理時間との関係を示す説明
図であり、また、第４図は同上従来例による堅型ＩＧＢ
Ｔの概要構成を示す断面図である。
２１・・・・ｐ＋シリコン基板、２２・・・・高濃度Ｂ
＋層、２３・・・・低不純物濃度のｎ一層、２４・・・
・ｐウェル層、２５・・・・ｎ＋型ソース層、２６・・
・・チャンネル領域、２７・・・・ゲート絶縁膜、２８
・・・・ゲート電極２８．２９・・・・ソース電極、３
０・・・・ドレイン電極。
代理人 大 岩 増 雄
第１１
第２図
第２図
第３図
↑（ｈ ｒｓ、）
第４図
手続補正書（自発）
２、発明の名称
半導体装置の製造方法
３、補正をする者
代表者志岐守哉
４、代理人
住 所 東京都千代田区丸の内二丁目２番３号５
、補正の対象
６、補正の内容
（１） 明細書の特許請求の範囲を別紙のとおり補正
する。
（２）同書６頁１４行の「同表面側から」を削除する。
以 上
特許請求の範囲
（１） 相互に逆の導電形で直列に隣接するソース領
域、ウェル領域、基体領域、およびドレイン領域を有し
、かつ前記ソース領域とウェル領域との表面に、ＤＳＡ
法によって自己整合的にチャンネル領域を形成した素子
構成とされ、前記チャンネル領域にゲート絶縁膜を介し
て形成したゲート電極にょυ制御される堅型ＩＧＢＴに
おいて、前記チャンネル領域の形成時に１まず、その表
面濃度を、素子構成のしきい値電圧がお＼よそ５〜ＩＯ
Ｖ程度になるように設定させ、ついで、電子線を照射後
、アニール処理して、電子線照射時に低下した前記しき
い値電圧を、お＼よそ２〜５Ｖ程度まで回復させるよう
にしたことを特徴とする半導体装置の製造方法。
（２）チャンネル領域形成時における表面濃度か、３〜
５ｘ１０１７０ｙＩ−ｓであることを特徴とする特許請
求の範囲第１項に記載の半導体装置の製造方法。
（３）電子線照射量が、５×１０１３”〜８×１０１４
伽であることを特徴とする特許請求の範囲第１項に記載
の半導体装置の製造方法。
（４）アニール処理条件が、お＼よそ３００℃の温度で
、２〜５時間の処理であることを特徴とする特許請求の
範囲第１項に記載の半導体装置の製造方法。FIG. 1 is a sectional view showing the general structure of a rigid IGBT to which an embodiment of the method for manufacturing a semiconductor device according to the present invention is applied, and FIGS. FIG. 3 is an explanatory diagram showing the relationship between the threshold voltage, turn-off time, and annealing time during annealing in the same method as above, and FIG. Rigid IGB according to the conventional example above
FIG. 2 is a cross-sectional view showing the general configuration of T. 21...p+ silicon substrate, 22...high concentration B
+ layer, 23...N layer with low impurity concentration, 24...
・P well layer, 25...n+ type source layer, 26...
... Channel region, 27 ... Gate insulating film, 28
...Gate electrode 28.29...Source electrode, 3
0...Drain electrode. Agent Masuo Oiwa No. 11 Figure 2 Figure 2 Figure 3 ↑ (hrs,) Figure 4 Procedural amendment (voluntary) 2. Name of the invention Method for manufacturing semiconductor devices 3. Representative of the person making the amendment Moriya Shiki 4, agent address: 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, Subject of amendment 6, Contents of amendment (1) The claims of the specification are amended as shown in the attached sheet. (2) Delete "from the front side" on page 6, line 14 of the same book. Claims (1) A source region, a well region, a base region, and a drain region that are of mutually opposite conductivity types and are adjacent in series, and a DSA is provided on the surfaces of the source region and the well region.
In a rigid IGBT, which has a device configuration in which a channel region is formed in a self-aligned manner by a method, and which is controlled by a gate electrode formed in the channel region via a gate insulating film, when forming the channel region, 1. The surface concentration is determined by the threshold voltage of the device configuration being approximately 5 to IO.
After irradiating the electron beam, annealing is performed to recover the threshold voltage, which decreased during electron beam irradiation, to approximately 2 to 5 V. A method for manufacturing a featured semiconductor device. (2) Surface concentration at the time of channel region formation, 3~
5. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is 5x10170yI-s. (3) Electron beam irradiation amount is 5×1013” to 8×1014
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a tong. (4) The method for manufacturing a semiconductor device according to claim 1, wherein the annealing treatment conditions are a treatment at a temperature of approximately 300° C. for 2 to 5 hours.
Claims (4)
ウェル領域、基体領域、およびドレイン領域を有し、か
つ前記ソース領域とウェル領域との表面に、ＤＳＡ法に
よつて自己整合的にチャンネル領域を形成した素子構成
とされ、前記チャンネル領域にゲート絶縁膜を介して形
成したゲート電極により制御される堅型ＩＧＢＴにおい
て、前記チャンネル領域の形成時に、まず、その表面濃
度を、素子構成のしきい値電圧がおゝよそ５〜１０Ｖ程
度になるように設定させ、ついで、同表面側から電子線
を照射後、アニール処理して、電子線照射時に低下した
前記しきい値電圧を、おゝよそ２〜５Ｖ程度まで回復さ
せるようにしたことを特徴とする半導体装置の製造方法
。(1) Source regions adjacent in series with mutually opposite conductivity types;
The device has a well region, a base region, and a drain region, and has a channel region formed in a self-aligned manner on the surfaces of the source region and the well region by the DSA method, and has a gate insulator in the channel region. In a rigid IGBT controlled by a gate electrode formed through a film, when forming the channel region, first, the surface concentration is adjusted so that the threshold voltage of the device structure is approximately 5 to 10 V. Then, after irradiating an electron beam from the same surface side, an annealing treatment is performed to recover the threshold voltage, which decreased during the electron beam irradiation, to about 2 to 5 V. A method for manufacturing a semiconductor device.
５×１０＾１＾７ｃｍ＾−＾３であることを特徴とする
特許請求の範囲第１項に記載の半導体装置の製造方法。(2) The surface concentration at the time of channel region formation is 3~
The method for manufacturing a semiconductor device according to claim 1, wherein the size is 5×10^1^7 cm^-^3.
１＾４ｃｍ＾−＾２であることを特徴とする特許請求の
範囲第１項に記載の半導体装置の製造方法。(3) The electron beam irradiation amount is 5 x 10^1^3 to 8 x 10^
The method for manufacturing a semiconductor device according to claim 1, wherein the thickness is 1^4 cm^-^2.
、２〜５時間の処理であることを特徴とする特許請求の
範囲第１項に記載の半導体装置の製造方法。(4) The method for manufacturing a semiconductor device according to claim 1, wherein the annealing treatment conditions are a treatment at a temperature of approximately 300° C. for 2 to 5 hours.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62059521A JPH0728036B2 (en) | 1987-03-13 | 1987-03-13 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62059521A JPH0728036B2 (en) | 1987-03-13 | 1987-03-13 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63226072A true JPS63226072A (en) | 1988-09-20 |
| JPH0728036B2 JPH0728036B2 (en) | 1995-03-29 |
Family
ID=13115650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62059521A Expired - Lifetime JPH0728036B2 (en) | 1987-03-13 | 1987-03-13 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0728036B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02185069A (en) * | 1988-12-02 | 1990-07-19 | Motorola Inc | Semiconductor device having high-energy stopping power and temperature-compensated stopping voltage |
| JPH0327573A (en) * | 1989-06-26 | 1991-02-05 | Hitachi Ltd | Semiconductor device |
| KR102251761B1 (en) * | 2019-11-27 | 2021-05-14 | 현대모비스 주식회사 | Power semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5929741B2 (en) * | 2012-01-23 | 2016-06-08 | 株式会社デンソー | Manufacturing method of semiconductor device |
-
1987
- 1987-03-13 JP JP62059521A patent/JPH0728036B2/en not_active Expired - Lifetime
Non-Patent Citations (8)
| Title |
|---|
| CONF. REC. IEEE IND. APPL. SOC. ANNU. MEET. 21ST=1986 * |
| IEEE TRANSACTIONS ON ELECTRON DEVICES=1977 * |
| IEEE TRANSACTIONS ON ELECTRON DEVICES=1984 * |
| IEEE TRANSACTIONS ON ELECTRON DEVICES=1985 * |
| J. ELECTROCHEM. SOC.=1977 * |
| J. ELECTROCHEM. SOC.=1983 * |
| SOLID-STATE ELECTRONICS=1983 * |
| VLSI TECHNOLOGY=1983 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02185069A (en) * | 1988-12-02 | 1990-07-19 | Motorola Inc | Semiconductor device having high-energy stopping power and temperature-compensated stopping voltage |
| JPH0327573A (en) * | 1989-06-26 | 1991-02-05 | Hitachi Ltd | Semiconductor device |
| KR102251761B1 (en) * | 2019-11-27 | 2021-05-14 | 현대모비스 주식회사 | Power semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0728036B2 (en) | 1995-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100232206B1 (en) | Method of manufacturing semiconductor device | |
| KR920009745B1 (en) | Manufacturing method of semiconductor | |
| JPH0467343B2 (en) | ||
| JP2001077363A (en) | Silicon carbide semiconductor device and its manufacturing method | |
| JPS60210861A (en) | Semiconductor device | |
| JP3863926B2 (en) | Three-terminal power insulated gate transistor and manufacturing method thereof | |
| JPH07101737B2 (en) | Method for manufacturing semiconductor device | |
| JPS63226072A (en) | Manufacture of semiconductor device | |
| JPH0436584B2 (en) | ||
| US4216038A (en) | Semiconductor device and manufacturing process thereof | |
| JPS6184867A (en) | Manufacture of igfet | |
| JP3240896B2 (en) | MOS type semiconductor device | |
| JP2964609B2 (en) | Insulated gate bipolar transistor and method of manufacturing the same | |
| JP3369862B2 (en) | Method for manufacturing semiconductor device | |
| JP3186298B2 (en) | Method for manufacturing MOS type semiconductor device | |
| JPH0234937A (en) | Manufacture of semiconductor device | |
| JP2808945B2 (en) | Method of manufacturing vertical MOS field effect transistor | |
| JPH05343667A (en) | Manufacture of conductivity modulation type mosfet | |
| JP3017783B2 (en) | Conduction modulation type MOSFET | |
| JPH0472771A (en) | Mosfet | |
| JPS6223170A (en) | Manufacture of vertical type field-effect transistor for power | |
| JPH01189175A (en) | Double-diffusion type field effect semiconductor device | |
| JPS6369271A (en) | Semiconductor device and manufacture thereof | |
| JPH07249760A (en) | Fabrication of semiconductor device | |
| JPS61203679A (en) | Mos transistor of high withstand voltage |