JPS6184867A - Manufacture of igfet - Google Patents
Manufacture of igfetInfo
- Publication number
- JPS6184867A JPS6184867A JP60214398A JP21439885A JPS6184867A JP S6184867 A JPS6184867 A JP S6184867A JP 60214398 A JP60214398 A JP 60214398A JP 21439885 A JP21439885 A JP 21439885A JP S6184867 A JPS6184867 A JP S6184867A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- region
- source
- junction
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims description 62
- 229910052782 aluminium Inorganic materials 0.000 claims description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000003071 parasitic effect Effects 0.000 description 10
- 239000002019 doping agent Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000153 supplemental effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の背景〕
この発明は、金属酸化物半導体電界効果トランジスタ（
以下ＭＯ８ＦＥＴと称する）のような絶縁ゲート電界効
果トランジスタ（以下ＩＧＦＥＴと称する）に関する。[Detailed Description of the Invention] [Background of the Invention] The present invention relates to a metal oxide semiconductor field effect transistor (
The present invention relates to insulated gate field effect transistors (hereinafter referred to as IGFETs) such as MO8FETs (hereinafter referred to as MO8FETs).
すなわち、この発明は半導体ウェハの一方の面にソース
およびゲート電極が配置され、反対側の面にドレン電極
が配置された縦型ＭＯ８ＦＦＩ：ＴＫ閃し、特に導電度
変調ＦＥＴ（以下Ｃ０ＭＦＥＴと称する）のような縦型
２重拡散ＭＯ８ＦＥＴ （以下ＶＤＭＯ８、！：称する
＞Ｋ。That is, this invention is a vertical MO8FFI:TK type in which a source and gate electrode are arranged on one side of a semiconductor wafer and a drain electrode is arranged on the opposite side, and in particular, a conductivity modulated FET (hereinafter referred to as C0MFET). Vertical double diffusion MO8FET (hereinafter referred to as VDMO8, !:>K).
関する。related.
ＶＤＭＯ８装置は交互に導電型が変るソース、基体、ド
レンの各領域を半導体ウェハ内に直列に配置したもので
、その基体領域はウエハ面に隣接して配置され、ソース
およびドレン領域はウエハ表面の基体領域にチャンネル
領域の長さと幅を画定するように設けられている。Ｖ
Ｄ ＩＶＩ ＯＳという用語はこの装置の製造方法に由
来しており、その方法は、半導体ウエハ面にドレン領域
を設け、そのドレン領域の一部にマスク開孔を介して基
体領域用ドーグ剤とソース領域用ドープ剤を通常順次拡
散する各段階からなる。A VDMO8 device has source, substrate, and drain regions of alternating conductivity types arranged in series within a semiconductor wafer, with the substrate region located adjacent to the wafer surface and the source and drain regions adjacent to the wafer surface. A channel region is provided in the substrate region to define the length and width of the channel region. V
The term DIVI OS originates from the method of manufacturing this device, in which a drain region is provided on the surface of a semiconductor wafer, and a portion of the drain region is injected with a dope agent for the substrate region and a source through mask openings. The steps usually involve sequential diffusion of the dopant for the region.
ウェハ表面にはチャンネル領域に跨って絶縁ゲート電極
が設けられ、装置の動作中にこれに特定の聞直電圧より
大きな電圧を印加すると、チャンネル領域のウェハ表面
に隣接する部分における基体の導電型が反転し、これに
よってソース領域とドレン領域の間にｆＢ子または正孔
、Ｅ流を流す反転チャンネルと称するものが形成される
。従って、装置の動作はゲートに印加される電圧によっ
て電子まだは正孔の流れが選択的に変調される→÷中゛
−ユニポーラ
型のものとして説明される。通常のＶＤＭＯ８の構造お
よび処理についてのこれ以上の細部は米国特許第４．１
４５．７００号および第４ 、０７２ 、９７５号の各
明細書に記載されている。An insulated gate electrode is provided on the wafer surface spanning the channel region, and when a voltage greater than a certain direct voltage is applied to this during operation of the device, the conductivity type of the substrate in the portion of the channel region adjacent to the wafer surface changes. This forms what is called an inversion channel that allows fB electrons or holes, E current to flow between the source and drain regions. Therefore, the operation of the device can be described as unipolar, in which the flow of electrons and holes is selectively modulated by the voltage applied to the gate. Further details on the construction and processing of conventional VDMO8s are found in U.S. Patent No. 4.1.
No. 45.700 and No. 4,072,975.
Ｃ０ＭＦＥＴはＶＤＭＯ３装置の変形で、ドレン領域に
隣接してこれと反対の導電型の第４番目の半導体領域を
含んでいる。この第４番目の半導体領域は、陽極領域と
称することもあり、装置の動作中電荷キャリヤの供給源
となってこれに隣接するドレン領域の導電度を変調する
働らきをする。A COMFET is a variation of a VDMO3 device that includes a fourth semiconductor region of opposite conductivity type adjacent to the drain region. This fourth semiconductor region, sometimes referred to as the anode region, serves as a source of charge carriers to modulate the conductivity of the adjacent drain region during operation of the device.
Ｃ０ＭＦＥＴ装置の大きな特徴の１っけ同じ構造の３層
ＶＤＭＯ８ＦＥＴに比して動作抵抗が極めて低いことで
ある。Ｃ０ＭＦＥＴの構造の詳細は米国特許第４，３６
４，０７３号の明細書に記・載されている。One major feature of the C0MFET device is that its operating resistance is extremely low compared to a three-layer VDMO8FET of the same structure. Details of the structure of C0MFET can be found in U.S. Patent No. 4,36.
It is described and described in the specification of No. 4,073.
ＭＯ３Ｆ’ＥＴの３層ソース／基体／ドレンｔ→１４造
には本来寄生ｎｐｎまたはｐｎｐバイポーラトランジス
タが備わっていて、ソース／基体／ドレンＱのＭＯＳＦ
ＥＴの構造はエミッタ／ベース／コレクタ型の寄生バイ
ポーラ構造に対応する。ＭＯＳＦＥＴの動作中にエミッ
タ、ベース間ｐ ｎ 接合が順バイアスされると、寄生
バイポーラトランジスタが導通するが、これはＭＯＳＦ
ＥＴの性能に有害のため、寄生バイポーラトランジスタ
の利得を下げるだめの種々の努力が払われてきた。この
努力の１例は上記米国特許第４ 、０７２ 、９７５号
明細書の他特願昭６０−３４２８５号の明、細部にも記
載されている。The three-layer source/substrate/drain t→14 structure of MO3F'ET is originally equipped with a parasitic npn or pnp bipolar transistor, and the source/substrate/drain Q MOSF
The structure of the ET corresponds to an emitter/base/collector type parasitic bipolar structure. When the p n junction between the emitter and base is forward biased during operation of the MOSFET, the parasitic bipolar transistor becomes conductive;
Various efforts have been made to reduce the gain of parasitic bipolar transistors because it is detrimental to ET performance. An example of this effort is described in the specification of the above-mentioned US Pat.
Ｃ０ＭＦＥＴにおいて寄生パイボーラトラノジスタの利
得を下げることは、寄生ｎｐｎｐまたはｐｎｐｎサイリ
スタのラッチアップを防ぐためソース／基体／ドレン型
バイポーラトランジスタの利得と陽極／ドレン／基体型
寄生バイポーラトランジスタの利得の和を１未満に維持
する必要がある点で特に重要である。もしラッチアップ
が生じるとゲート制御が失なわれて装置はもはやＣ０Ｍ
ＦＥＴとして動作しなくなる。Reducing the gain of the parasitic bipolar transistor in a C0MFET reduces the sum of the gain of the source/substrate/drain type bipolar transistor and the gain of the anode/drain/substrate type parasitic bipolar transistor to prevent latch-up of the parasitic npnp or pnpn thyristor. This is particularly important as it must be kept below 1. If latch-up occurs, gate control is lost and the device is no longer at C0M.
It will no longer work as an FET.
この発明はこのＣ０ＭＦＥＴにおけるラッチアップの発
生を抑制すると共に３層Ｖ Ｄ Ｍ ＯＳ装置における
寄生バイポーラトランジスタの影響ヲ減じるためになさ
れたものである。This invention was made to suppress the occurrence of latch-up in this C0MFET and to reduce the influence of parasitic bipolar transistors in three-layer V D MOS devices.
寄生バイポーラ効果を減じだＩＧＦＥＴはその 。 IGFETs reduce parasitic bipolar effects.
表面に第１の導電型のドレン領域を有する半導体ウェハ
を含み、その表面の一部から内部に第２の導電型の基体
領域を拡散して、基体／ドレンｐｎ接合を形成した後、
その基゛体領域の境界内にウェハ表面から第１の導電型
のソース領域を拡散してその表面から所定の深さに沈ん
だソース／基体ｐｎ接合を形成する。このソース／基体
ｐｎ接合は基体／ドレンｐｎ接合から離れてウェハ表面
の基体領域内にチャンネル領域を画定する。このウェハ
表面上に所定の深さのソース／基体ｐｎ接合と接触する
アルミニウム層が形成され、ソース／基体ｐｎ接合が装
置の動作時に順バイアスされるのを防いでいる。comprising a semiconductor wafer having a drain region of a first conductivity type on a surface, and diffusing a substrate region of a second conductivity type inward from a portion of the surface to form a substrate/drain p-n junction;
A source region of a first conductivity type is diffused from the wafer surface into the boundaries of the substrate region to form a source/substrate p-n junction sunk to a predetermined depth from the surface. The source/substrate pn junction defines a channel region within the substrate region of the wafer surface separate from the substrate/drain pn junction. An aluminum layer is formed on the wafer surface in contact with the source/substrate pn junction at a predetermined depth to prevent the source/substrate pn junction from becoming forward biased during operation of the device.
図に示すように、この発明を含むＶ Ｄ Ｍ ＯＳ装置
１０は例えば３層ＭＯ８ＦＥＴまたは４ノラＣＯＭＦＥ
Ｔである。説明を明確にするだめ、この発明をＮチャン
ネルＶＤＭＯ３装置に実施しだ場合を引用するが、全て
の導電型を反転してｐチャンネルＶ Ｄ Ｍ ＯＳ装置
を形成することもできることを理解されたい。この装置
１０は第１および第２の主表面１４．１６を持つ半導体
ウエハ１２を含み、その第２の主表面１６の全面に比較
的高導電度のｎ型まだはｐ型の領域１８が配置されてい
る。領域１８は３層＋
ｎチャンネルＭＯＳＦＥＴではｎ型材料から成り、ドレ
ン領域と呼ばれるが、ｎチャンネルＣＱ Ｍ ＦＥＴで
はｐ型材料から成り、陽極領域と呼ばれる。As shown in the figure, a V D M OS device 10 including the present invention is configured using, for example, a 3-layer MO8FET or a 4-layer MO8FET.
It is T. For clarity of explanation, reference will be made to the implementation of the invention in an N-channel VDMO3 device, but it should be understood that all conductivity types can also be reversed to form a p-channel VDMOS device. The apparatus 10 includes a semiconductor wafer 12 having first and second major surfaces 14.16, with a relatively highly conductive n-type or p-type region 18 disposed over the second major surface 16. has been done. Region 18 is made of n-type material in a 3-layer + n-channel MOSFET and is called the drain region, whereas in an n-channel CQ M FET it is made of p-type material and is called the anode region.
ｎチャンネルＣ０ＭＦＥＴ構造では、図に点線で示すよ
うに陽極領域１８上にｎ型ドレン領域２０が付加され、
そのｎ型ドレン領域２０に隣接して、或いは領域２０が
ないときは比較的高導電度の領域１８に隣接して、第１
の主表面１４の方向に拡るｎ−型延長ドし７頑域２２が
ある。In the n-channel C0MFET structure, an n-type drain region 20 is added above the anode region 18, as shown by the dotted line in the figure.
Adjacent to the n-type drain region 20, or in the absence of region 20, adjacent to the relatively high conductivity region 18, a first
There is an n-type extended region 22 extending in the direction of the major surface 14 of the substrate.
第１の主表面１４からウェハ１２内にｐ−型基体領域２
４が拡ってｎ−型延長ドレン領域２２との境界に基体／
ドレノｐｎ接合２６を形成している。推奨実施例では、
基体領域２４を主表面１４０選ばれた部分からウェハ内
に拡散させて、その基体／ドレンｐｎ接合２６が６角形
または４角形のような正多角形の形で主表面１４と交わ
るようにしである。その基体領域２４の境界内の第１の
主表面１４からウェハ１２内に＋
ｎ型ソース領域２８が拡がり、基体領域２４との境界で
ソース／基体ｐｎ接合３０を形成している。このソース
／基体ｐｎ接合３０は、第１の主表面１４で基体／ドレ
ンｐｎ接合２６から離れてその主表面１４で基体２４内
にチャンネル領域３２の長さと幅を画定している。ソー
ス領域２８の形状は一般に環状であるが円形ではない。A p-type substrate region 2 is formed into the wafer 12 from the first major surface 14.
4 expands to form a substrate/
A dreno pn junction 26 is formed. In the recommended practice,
The substrate region 24 is diffused into the wafer from selected portions of the major surface 140 such that the substrate/drain pn junction 26 intersects the major surface 14 in the form of a regular polygon, such as a hexagon or a quadrilateral. . A +n type source region 28 extends into the wafer 12 from the first major surface 14 within the boundaries of the substrate region 24 and forms a source/substrate pn junction 30 at the boundary with the substrate region 24 . The source/substrate p-n junction 30 defines the length and width of a channel region 32 within the substrate 24 at its first major surface 14 away from the substrate/drain p-n junction 26 at its first major surface 14 . The shape of source region 28 is generally annular, but not circular.
ソース／基体ｐｎ接合３０の外部は、基体／ドレンｐｎ
接合２６と同様の正多角形の形状で主表面１４と交わっ
ている。環状ソース領域２８によって包囲された基体領
域２４の中央部には、その主表面１４からｐ型相補基体
碩域３４が入り込んでいる。External to the source/substrate pn junction 30 is the substrate/drain pn
It intersects with the main surface 14 in a regular polygonal shape similar to the junction 26 . A p-type complementary substrate subregion 34 extends from the main surface 14 into the center of the substrate region 24 surrounded by the annular source region 28 .
チャンネル領域３２上の第１の表面１４には、その上の
ゲート絶縁物３６とさらにその上のゲート電極３８とを
含む絶縁ゲート電極が配置されている。ゲート絶縁物３
６は一般に厚さ約５００〜２０００人のノリコン酸化物
から成り、ゲート電＠３８は一般にドーグされた多結晶
シリコンから成る。このゲート電極３８上にはこれをそ
の上層から電気的に絶縁するために燐珪酸ガラス、硼珪
酸ガラスまたは燐硼珪酸ガラスのような珪ポガラスを一
般に含む絶縁層４０が被覆されている。この絶縁層４０
上にはアルミニウムのソース電極４２が被覆され、第１
の主表面１４に接触してソース領域２８および基体領域
２４との接触を形成している。第２の主表面１６上の高
導電 ・度碩域１８にはドレン電極４４が接触してい
る。An insulated gate electrode is disposed on the first surface 14 over the channel region 32 and includes a gate insulator 36 thereon and a gate electrode 38 thereon. Gate insulator 3
6 typically consists of a Noricon oxide approximately 500 to 2000 thick and the gate electrode 38 typically consists of doped polycrystalline silicon. Overlying the gate electrode 38 is an insulating layer 40, typically comprising a silica glass such as phosphosilicate glass, borosilicate glass, or phosphoborosilicate glass, to electrically insulate it from layers above it. This insulating layer 40
An aluminum source electrode 42 is coated on top, and the first
, forming contact with source region 28 and substrate region 24 . A drain electrode 44 is in contact with the highly conductive region 18 on the second main surface 16 .
この発明の方法では、アルミニウムのソース電極４２を
これがウェハ１２内に少なくともソース／基体ｐｎ接合
３０の深さまで進入してｐ型の基体領域２４に接触する
ようにすることが肝要である。このアルミニウムの進入
部図中に４３で示されている。In the method of the present invention, it is important to extend the aluminum source electrode 42 into the wafer 12 at least to the depth of the source/substrate pn junction 30 so that it contacts the p-type substrate region 24. This aluminum entry is shown at 43 in the drawing.
このアルミニウムの進入現象の詳細は米国特許第３．６
０９，４７０号明細書に記載されている。この発明では
アルミニウムがチャンネル領域３２に有害な影響を与え
ずにできるだけ大きな面積でソース／基体ｐｎ接合を貫
通してこれに接触することが望ましい。進入の深さが最
適の場合、このアルミニウム進入部４３はソース／基体
ｐｎ接合３０を貫通するが、基体領域２４内には余り進
入しない。The details of this aluminum intrusion phenomenon are described in U.S. Patent No. 3.6.
No. 09,470. In the present invention, it is desirable for the aluminum to penetrate and contact the source/substrate pn junction in as large an area as possible without deleteriously affecting the channel region 32. If the depth of penetration is optimal, this aluminum penetration 43 penetrates the source/substrate pn junction 30 but does not penetrate significantly into the substrate region 24.
アルミニウム進入部は、ソース電極４２の被着中または
彼着装に装置を熱処理することによって形成される。推
奨実施例では、アルミニウムのソース成極４２が蒸着や
スパツタリングのような通常の蒸着手段によって被着さ
れだ後約４００〜４５０℃で約１５分ないし１時間熱処
理され、これによって主表面１４から約０．５〜１．５
μｍ入り込んだアルミニウム進入部４３が形成される。The aluminum intrusion is formed by heat treating the device during or after the deposition of the source electrode 42. In a preferred embodiment, the aluminum source electrode 42 is deposited by conventional deposition means, such as evaporation or sputtering, and then heat treated at about 400-450° C. for about 15 minutes to 1 hour, thereby removing about 0.5-1.5
An aluminum intrusion portion 43 having a depth of μm is formed.
１ 、５ ｆｍがこの熱処理によるほぼ最大の進入距離
であるので、装置の他の処理によってソース／基体ｐｎ
接合３０の主表面１４からの深さが絶対に１．５μｍ未
満になるようにしなければならない。この推奨実施例で
は、ソース／基体ｐｎ接合３０の深さは１μｍ未満がよ
く、約０．５μｍ未満が最適である。これはソース領域
の深さが１μｍ以上ある通常の装置に比較して浅いが、
この比較的浅いソース／基体ｐｎ接合の深さを制御でき
るようにするにはソース領域２８用のｎ型ドープ剤とし
て砒素を用いることが望ま゛しい。砒素に代えて燐をｎ
型ソースドープ剤に用いることもできるが、拡散を１μ
ｍ以下に制御するのが困難になる。Since 1,5 fm is approximately the maximum penetration distance by this heat treatment, the source/substrate pn
It must be ensured that the depth of the bond 30 from the main surface 14 is never less than 1.5 μm. In this preferred embodiment, the depth of the source/substrate pn junction 30 should be less than 1 μm, optimally less than about 0.5 μm. Although this is shallow compared to a conventional device in which the depth of the source region is 1 μm or more,
It is desirable to use arsenic as the n-type dopant for source region 28 to allow control of the depth of this relatively shallow source/substrate p-n junction. phosphorus instead of arsenic
It can also be used as a type source dopant, but the diffusion is limited to 1 μm.
It becomes difficult to control the temperature to below m.
この装置１０の製造において、絶縁ゲート電画は、１１
主表面１４にソース領域２８と基本領域２４の位ｌａ決
めをするマスクの動きをする。一般に絶縁ゲート電極は
孔あき層の形をしており、基体領域とソース領域のドー
プ剤がこの開孔を介してウェハ１２内に導入される。こ
の絶縁ゲート電極の開孔を図に符号４６で示す。この発
明の進入部形成効果を最大にするという観点から見ると
、第１主表面１４上のソース電極４２の接触領域は、チ
ャンネル領域３２からできるだけ離れた点でソース／基
体ｐｎ接合３０の上に来る必要がある。これによって上
述の熱処理後アルミニウム進入部４３が接触するソース
／基本ｐｎ接合３０の面積が最大になる。In the manufacture of this device 10, the insulated gate electrodes are 11
A mask movement is performed to position the source region 28 and basic region 24 on the main surface 14. Generally, the insulated gate electrode is in the form of a perforated layer through which the dopants of the substrate and source regions are introduced into the wafer 12. The opening of this insulated gate electrode is indicated by reference numeral 46 in the figure. From the point of view of maximizing the entry-forming effect of the present invention, the contact area of the source electrode 42 on the first major surface 14 should be placed over the source/substrate p-n junction 30 at a point as far away from the channel region 32 as possible. I need to come. This maximizes the area of the source/basic pn junction 30 with which the aluminum entry portion 43 contacts after the above-mentioned heat treatment.
さらに、この発明を実施するときはｐ型の基体領域２４
のドープ剤濃度を調節してソース領域２８の比較的浅い
拡散に対して装置の闇値電圧を補償する必要がある。す
なわち、ソース領域を比較的浅くする拡散では、横方向
の拡散距離も比較的短かくなる。閾値電圧（すなわち反
転チャンネルが形成されている所の電圧）は、チャンネ
ル領域３２に隣接するソース／基体ｐｎ接合３０のキャ
リヤ濃度によって制御されるので、ソース／基体ｐｎ接
合３０の基体領域２４内のｐ型ドープ剤濃度はソース領
域２８のｎ型ドーグ剤の横方向拡散距離の減少と均衡す
るように減じる必要がある。Furthermore, when carrying out this invention, the p-type base region 24
It is necessary to adjust the dopant concentration of the dopant to compensate the dark value voltage of the device for the relatively shallow diffusion of the source region 28. That is, when the source region is diffused to be relatively shallow, the lateral diffusion distance is also relatively short. The threshold voltage (i.e., the voltage at which the inversion channel is formed) is controlled by the carrier concentration of the source/substrate pn junction 30 adjacent the channel region 32, so that the The p-type dopant concentration must be reduced to balance the reduction in the lateral diffusion length of the n-type dopant in source region 28.
アルミニウム進入部４３はＶＤＭＯ３装置１０のｎｐｎ
型ソース／基体／ドレ／構造に対応する寄生バイポーラ
トランジスタの順方向−流利得αを効果的に減少させる
。この発明を含む装置をアルミニウム進入部を設けない
装置と比較すると、進入部を設けない装置でばαが約０
．９であるが、典型的な進入部を設けた装置ではαが０
．２５以下となることが観測され、ＣＯＭ Ｆ Ｅ Ｔ
にこの発明を実施するとアルミニウム進入部がランチア
ンプ電流を１００倍までも増加させることが観測された
。The aluminum entry portion 43 is the npn of the VDMO3 device 10.
effectively reducing the forward-flow gain α of the parasitic bipolar transistor corresponding to the type source/substrate/drain/structure. When comparing a device including this invention with a device not having an aluminum inlet, α is approximately 0 in the device not having an inlet.
．． 9, but in a device with a typical entry section, α is 0.
．． 25 or less, and COM F E T
When the invention was practiced, it was observed that the aluminum inlet increases the launch amplifier current by up to 100 times.
さらに、この発明の方法では、アルミニウム進入部４３
が基体領域２４とソース／基体ｐｎ接合の双方に接触を
形成してｐ型基体領域２４をソース電槙４２に接続する
ため、ｐ型の補充用基体領域３４の必要がなくなること
もある。さらにまたこの発明の方法では、ソース領域２
８を環状とする必要がないため、これをさらに簡単な形
にすることもできる。Furthermore, in the method of the present invention, the aluminum entry portion 43
The need for a p-type supplemental substrate region 34 may be eliminated because the p-type substrate region 24 forms contacts to both the substrate region 24 and the source/substrate p-n junction to connect the p-type substrate region 24 to the source voltage 42. Furthermore, in the method of the present invention, the source region 2
Since 8 does not need to be annular, it can also be made into a simpler shape.
アルミニウム進入部４３はソース／基体ｐｎ接合３０の
深さに入り込んでいるので、基体領域２４を第１主表面
１４でソース電極に接続するための補充領域３４の必要
もなくなる。Because the aluminum entry 43 extends to the depth of the source/substrate pn junction 30, the need for a supplementary region 34 to connect the substrate region 24 to the source electrode at the first major surface 14 is also eliminated.
最後に、この発明をＶＤＭＯ８装置について説明したが
、ＩＧＦＥＴと同様に横型ＭＯ８装置にも容易に適用し
得ることを理解すべきである。Finally, although the invention has been described with respect to a VDMO8 device, it should be understood that it can be easily applied to lateral MO8 devices as well as IGFETs.
図はこの発明を宮むＶＤＭＯ８の断面図である。
１２・・・ウェハ、１４・・・ウエハ１面、２２・・・
ドレン、２４・・・基体、２６・・・基体／ドレンｐｎ
接合、２８・・・ソース、３０・・・ソース／基体ｐｎ
接合、３２・・・チャンネル。The figure is a sectional view of the VDMO 8 embodying the present invention. 12... Wafer, 14... One wafer surface, 22...
drain, 24...substrate, 26...substrate/drain pn
Junction, 28...source, 30...source/substrate pn
Junction, 32...channel.
Claims (1)
レン領域を設ける段階と、その表面の一部から上記ウェ
ハ内に第２の導電型の基体領域を拡散して基体／ドレン
ｐｎ接合を形成する段階と、上記基体領域の境界内に第
１の導電型のソース領域を拡散して上記ウェハの表面か
ら所定の深さに沈み、上記基体／ドレン接合から離れて
そのウエハ表面の上記基体領域内にチャンネル領域を限
定するソース／基体ｐｎ接合を形成する段階と、上記ウ
ェハ表面に上記所定の深さの上記ソース／基体接合に接
触するアルミニウム層を形成して、装置の動作中に上記
ソース／基体ｐｎ接合が順バイアスされるのを防ぐよう
にする段階とを含むＩＧＦＥＴの製造方法。(1) providing a drain region of a first conductivity type adjacent to the surface of a semiconductor wafer, and diffusing a base region of a second conductivity type into the wafer from a portion of the surface to drain the base/drain pn; forming a junction; and diffusing a source region of a first conductivity type within the boundaries of the substrate region to a predetermined depth below the surface of the wafer and away from the substrate/drain junction to a depth of the wafer surface. forming a source/substrate p-n junction defining a channel region within the substrate region; and forming an aluminum layer on the wafer surface in contact with the source/substrate junction at the predetermined depth during operation of the apparatus. and preventing the source/substrate pn junction from becoming forward biased.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US65510984A | 1984-09-27 | 1984-09-27 | |
| US655109 | 1984-09-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6184867A true JPS6184867A (en) | 1986-04-30 |
Family
ID=24627549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60214398A Pending JPS6184867A (en) | 1984-09-27 | 1985-09-26 | Manufacture of igfet |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS6184867A (en) |
| DE (1) | DE3533808A1 (en) |
| FR (1) | FR2570880A1 (en) |
| GB (1) | GB2165091B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01181571A (en) * | 1988-01-11 | 1989-07-19 | Nippon Denso Co Ltd | Conduction modulation type mosfet |
| JPH01235277A (en) * | 1988-03-15 | 1989-09-20 | Nec Corp | Vertical field-effect transistor |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2193597A (en) * | 1986-08-08 | 1988-02-10 | Philips Electronic Associated | Method of manufacturing a vertical DMOS transistor |
| JPS63302535A (en) * | 1987-06-03 | 1988-12-09 | Mitsubishi Electric Corp | Gallium arsenide integrated circuit |
| JP2510710B2 (en) * | 1988-12-13 | 1996-06-26 | 三菱電機株式会社 | MOS field effect transistor formed in semiconductor layer on insulator substrate |
| KR20100135521A (en) * | 2009-06-17 | 2010-12-27 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
| CN106206300A (en) * | 2015-04-29 | 2016-12-07 | 北大方正集团有限公司 | Vertical double diffused metal-oxide semiconductor field effect transistor and processing method |
| CN109817707A (en) * | 2019-01-15 | 2019-05-28 | 上海华虹宏力半导体制造有限公司 | RC-IGBT structure and its manufacturing method |
| CN117238969A (en) * | 2023-11-13 | 2023-12-15 | 深圳基本半导体有限公司 | Silicon carbide MOSFET device and preparation method and application thereof |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5363983A (en) * | 1976-11-19 | 1978-06-07 | Toshiba Corp | Semiconductor device |
| JPS543480A (en) * | 1977-06-09 | 1979-01-11 | Fujitsu Ltd | Manufacture of semiconductor device |
| DE2930780C2 (en) * | 1979-07-28 | 1982-05-27 | Deutsche Itt Industries Gmbh, 7800 Freiburg | Method of manufacturing a VMOS transistor |
| DE3240162C2 (en) * | 1982-01-04 | 1996-08-01 | Gen Electric | Method of fabricating a double-diffused source-based short-circuit power MOSFET |
| US4503598A (en) * | 1982-05-20 | 1985-03-12 | Fairchild Camera & Instrument Corporation | Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques |
| JPS5957477A (en) * | 1982-09-27 | 1984-04-03 | Fujitsu Ltd | Semiconductor device |
| CA1216968A (en) * | 1983-09-06 | 1987-01-20 | Victor A.K. Temple | Insulated-gate semiconductor device with improved base-to-source electrode short and method of fabricating said short |
-
1985
- 1985-09-19 FR FR8513907A patent/FR2570880A1/en active Pending
- 1985-09-21 DE DE19853533808 patent/DE3533808A1/en not_active Withdrawn
- 1985-09-25 GB GB08523651A patent/GB2165091B/en not_active Expired
- 1985-09-26 JP JP60214398A patent/JPS6184867A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01181571A (en) * | 1988-01-11 | 1989-07-19 | Nippon Denso Co Ltd | Conduction modulation type mosfet |
| JPH01235277A (en) * | 1988-03-15 | 1989-09-20 | Nec Corp | Vertical field-effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2570880A1 (en) | 1986-03-28 |
| DE3533808A1 (en) | 1986-04-03 |
| GB2165091A (en) | 1986-04-03 |
| GB8523651D0 (en) | 1985-10-30 |
| GB2165091B (en) | 1988-04-20 |
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