JPS63215050A - Manufacture of dielectric isolation substrate - Google Patents
Manufacture of dielectric isolation substrateInfo
- Publication number
- JPS63215050A JPS63215050A JP4758987A JP4758987A JPS63215050A JP S63215050 A JPS63215050 A JP S63215050A JP 4758987 A JP4758987 A JP 4758987A JP 4758987 A JP4758987 A JP 4758987A JP S63215050 A JPS63215050 A JP S63215050A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystal
- dielectric
- substrate
- dielectric film
- dielectric isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000013078 crystal Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 9
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 abstract description 8
- 239000007789 gas Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 5
- 229910002092 carbon dioxide Inorganic materials 0.000 abstract description 4
- 239000001569 carbon dioxide Substances 0.000 abstract description 4
- 238000005245 sintering Methods 0.000 abstract description 4
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000012808 vapor phase Substances 0.000 abstract 1
- 238000000926 separation method Methods 0.000 description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 239000012535 impurity Substances 0.000 description 3
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 3
- 239000005052 trichlorosilane Substances 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- 230000008602 contraction Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、誘電体分離基板の製造方法に係り、特に湾曲
の小さい誘電体分離基板の製造法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a dielectric isolation substrate, and particularly to a method of manufacturing a dielectric isolation substrate with small curvature.
誘電体分離基板は、ＩＣの回路構成技術の１つで、接合
分離法では得られない高耐圧、高周波特性を有する。A dielectric isolation substrate is one of the IC circuit construction techniques, and has high breakdown voltage and high frequency characteristics that cannot be obtained with the junction isolation method.
第２図により従来の誘電体分離基板の製造法を説明する
。第２図（ａ）において、１はＳｉ単結晶板で、この一
主面に所要の数および形状の分離溝２をエツチングなど
により形成してあり、この分離溝２を形成した面にＳｉ
Ｏ２膜などの誘電体膜１３を被着形成する。次に（ｂ）
の如く、誘電体膜１３上に気相成長反応等によりＳｉ多
結晶層４を成長させる。その後Ｓｉ単結晶板１の表面を
研磨除去して（０）の如き誘電体分離基板５を製造する
。A conventional method for manufacturing a dielectric isolation substrate will be explained with reference to FIG. In FIG. 2(a), reference numeral 1 is a Si single crystal plate, on one main surface of which separation grooves 2 of a required number and shape are formed by etching, etc., and on the surface on which these separation grooves 2 are formed,
A dielectric film 13 such as an O2 film is deposited. Then (b)
As shown in FIG. 1, a Si polycrystalline layer 4 is grown on the dielectric film 13 by a vapor phase growth reaction or the like. Thereafter, the surface of the Si single crystal plate 1 is removed by polishing to produce a dielectric isolation substrate 5 as shown in (0).
Ｓｉ単結晶板１上に誘電体膜１３を介してＳｉ多結晶層
４を形成した、所謂多層構体は、それぞれの層の熱膨張
係数が等しくないので、多結晶層４を形成した高温から
室温に冷却する際、それぞれの熱収縮量の差によって湾
曲が生ずる。Ｓｉ単結晶とＳｉ多結晶とでは熱膨張係数
は後者の方が大なため、Ｓｉ多結晶側を凹とした湾曲を
形成する。この湾曲は、後に施されるＩＣ製造工程に少
なからず妨害を及ぼすので、解消せねばならない。The so-called multilayer structure in which a Si polycrystalline layer 4 is formed on a Si single-crystalline plate 1 via a dielectric film 13 has unequal thermal expansion coefficients for each layer. During cooling, curvature occurs due to the difference in the amount of thermal contraction. Since the thermal expansion coefficient of the Si single crystal and the Si polycrystal is larger, a curve is formed with the Si polycrystal side being concave. This curvature has to be eliminated, since it interferes with the subsequent IC manufacturing process.
その改良として、特公昭４５−３２７３１号公報に記載
のように、多結晶成長の原料ガスであるＨ２とＳＩＨ，
Ｘ、（Ｘは通常ハロゲン元素、ｎ及びｍはＯ〜４の数値
）との混合物に不純物を添加し、多結晶Ｓｉの微粒子を
変性結晶構造とする技術がある。しかし、製造条件や反
応装置の変動等により、その効果は必ずしも完全でなく
、歩留りに影響を与えるほどの湾曲高さとなることもあ
った。本発明は、以上の欠点を克服するためになされた
もので、本発明の目的とするところは、多結晶成長工程
における誘電体分離基板５の湾曲をより一層低減、且つ
安定化することが可能で、結果的に基板湾曲がなく、製
品歩留りを大幅に向上できる誘電体分離基板の製造法を
提供することにある。As an improvement, as described in Japanese Patent Publication No. 45-32731, H2 and SIH, which are raw material gases for polycrystal growth,
There is a technique in which impurities are added to a mixture of X, (X is usually a halogen element, and n and m are numerical values of O to 4) to give polycrystalline Si fine particles a modified crystal structure. However, due to variations in manufacturing conditions and reactor equipment, the effect is not always perfect, and the height of the curvature may sometimes be such that it affects the yield. The present invention has been made to overcome the above drawbacks, and an object of the present invention is to further reduce and stabilize the curvature of the dielectric isolation substrate 5 during the polycrystalline growth process. Therefore, it is an object of the present invention to provide a method for manufacturing a dielectrically isolated substrate that results in no substrate curvature and can greatly improve product yield.
発明者は、分離溝２の湾曲に対する影響を知るため、Ｓ
ｉ単結晶板１の一生面上における分離溝２の有無につい
て湾曲高さを実験比較したところ。In order to know the influence on the curvature of the separation groove 2, the inventor
i Experimental comparison of curvature height with and without separation grooves 2 on the whole surface of single crystal plate 1.
分離溝２のない場合は分離溝２を有する場合の約６０％
の湾曲高さとなることをつきとめ、分離溝２の存在が誘
電体分離基板５の湾曲に影響しているとの認識を得た。Approximately 60% of the case without separation groove 2 compared to the case with separation groove 2
It was found that the height of the curvature was , and it was recognized that the presence of the isolation groove 2 influenced the curvature of the dielectric isolation substrate 5.
第３図は分離溝２内のＳｉ多結晶の組織構造を示す断面
模型図であるが、Ｓｉ多結晶層４内の多条の線は断面で
あることを示すハツチングではなく繊維状多結晶の繊維
方向を示している。分離溝２内のＳｉ多結晶４ａは、分
離溝壁面とほぼ垂直に成長していた。これらの事から、
分離溝２内のＳｉ多結晶４ａは分離溝壁面を索引する力
が強いことが考えられた。そこで、分離溝２内のＳｉ多
結晶４ａが繊維状にならないように不純物を添加しない
ように形成し、第４図のようにＳｉ多結晶４を形成した
。図において、１４は、多結晶粒が塊状に成長した大粒
形Ｓｉ多結晶層で、分離溝２内が大粒形Ｓｉ多結晶層１
４で満される厚さに形成したものである。かかる構造に
よれば、第３図示のものの約７５％の湾曲高となった。FIG. 3 is a cross-sectional model diagram showing the structure of the Si polycrystal in the separation groove 2, but the multiple lines in the Si polycrystalline layer 4 are not hatched to indicate a cross section, but are fibrous polycrystalline. Indicates fiber direction. The Si polycrystal 4a in the separation groove 2 had grown almost perpendicular to the wall surface of the separation groove. From these things,
It was considered that the Si polycrystal 4a in the separation groove 2 had a strong indexing force against the wall surface of the separation groove. Therefore, in order to prevent the Si polycrystal 4a in the isolation groove 2 from becoming fibrous, impurities were not added to form the Si polycrystal 4 as shown in FIG. In the figure, reference numeral 14 denotes a large-grain Si polycrystalline layer in which polycrystalline grains have grown in a lump, and the inside of the separation groove 2 is a large-grain Si polycrystalline layer 1.
4. According to this structure, the bending height was approximately 75% of that shown in the third figure.
これは分離溝２内のＳｉ多結晶が塊状であるため、繊維
状に比べ、分離・溝壁を索引する力の伝達が弱いものと
考えられる。本発明は、以上述べた知見にもとづいてな
されたもので、Ｓｉ多結晶を塊状にするためには、不純
物を添加しない気相成長を行い、次いでＳｉ多結晶が繊
維状にするようにしたことを特徴としている。This is considered to be because the Si polycrystal in the separation groove 2 is in the form of a lump, so that the force that indexes the separation/groove wall is transmitted weaker than in the case of a fibrous form. The present invention has been made based on the above-mentioned knowledge, and in order to form Si polycrystals into lumps, vapor phase growth is performed without adding impurities, and then the Si polycrystals are made into fibers. It is characterized by
分離溝２内のＳｉ多結晶を塊状にすると、熱収縮時の力
が分離溝壁に作用しにくくなり誘電体分離基板の湾曲高
さが小となる。When the Si polycrystal in the separation groove 2 is made into a lump, the force during thermal contraction is less likely to act on the separation groove wall, and the curved height of the dielectric separation substrate is reduced.
以下１本発明の実施例を第１図に従って詳細に説明する
。まず第１図（ａ）に示すように、Ｓｉ単結晶板１を出
発材料として選択エツチング等の方法で一生面上に深さ
５０μｍのＶ形の分離溝２を形成した後、誘電体膜とし
て１．５μｍ厚の５ｉＯｚ膜３を熱酸化法により全面に
形成する。An embodiment of the present invention will be described in detail below with reference to FIG. First, as shown in FIG. 1(a), a V-shaped separation groove 2 with a depth of 50 μm is formed on a single surface using a method such as selective etching using a Si single crystal plate 1 as a starting material, and then a dielectric film is formed. A 5iOz film 3 having a thickness of 1.5 μm is formed over the entire surface by thermal oxidation.
次いでこのＳｉ単結晶板１を気相反応装置（図示せず）
に一主面側を上方に向けて装着し、温度１０００”０〜
１２００℃の下で水素と三塩化シラン蒸気の混合ガスを
供給し、約１０〜１５分間の処理により（ｂ）に示すよ
うに第１のＳｉ多結晶４１を成長させる。この時分離溝
２上のＳｉ多結晶４１ａは、その両側より、表面高は低
いが、その高さは分離溝２の岸２ａの高さより高いこと
が必要で、斯くすることにより、分離溝２内は第１のＳ
ｉ多結晶４１によって満たされる。次に引続いて、上記
反応ガス中に炭酸ガスを三塩化シラン蒸気の流量の５％
の流量で添加し、酸素を含む多結晶Ｓｉを所要の厚さに
成長させると（ｃ）に示すように第２の多結晶５ｉ４２
が形成される。この間の気相成長により、多結晶Ｓｉ粒
は焼結が起き、隣接する粒同志が次々に統合し合い塊状
の多結晶Ｓｉになるが第２の多結晶５ｉ４２は炭酸ガス
添加の効果により焼結が阻害され、一方第一のＳｉ多結
晶層４１は焼結が起き、塊状の多結晶層となる。所要の
気相反応を終了後、三塩化シラン、炭酸ガスの流入を止
め１反応装置の温度を下げ工程を終了し、多結晶付きＳ
ｉ板１５を得る。この冷却過程で多結晶付きＳｉ板１５
の各々の部分は、各々の熱膨張係数に従って収縮するが
、分離溝２内の塊状の多結晶Ｓｉが分離溝２の壁を索引
する力が弱いので分離溝２の存在によるウェハ湾曲が軽
減され、多結晶付きＳｉ板１５の湾曲は小さい。Next, this Si single crystal plate 1 was placed in a gas phase reactor (not shown).
Attach the machine with one main surface facing upward, and keep the temperature at 1000" 0~
A mixed gas of hydrogen and trichlorosilane vapor is supplied at 1200° C., and the process is performed for about 10 to 15 minutes to grow the first Si polycrystal 41 as shown in FIG. At this time, the surface height of the Si polycrystal 41a on the separation groove 2 is lower than that on both sides, but the height needs to be higher than the height of the bank 2a of the separation groove 2. Inside is the first S
It is filled with i-polycrystal 41. Subsequently, carbon dioxide gas is introduced into the reaction gas at a rate of 5% of the flow rate of the trichlorosilane vapor.
When polycrystalline Si containing oxygen is grown to the required thickness, the second polycrystalline 5i42 is grown as shown in (c).
is formed. Due to the vapor phase growth during this period, sintering occurs in the polycrystalline Si grains, and adjacent grains merge one after another to form a block of polycrystalline Si, but the second polycrystalline 5i42 is sintered due to the effect of carbon dioxide addition. On the other hand, the first Si polycrystalline layer 41 undergoes sintering and becomes a lumpy polycrystalline layer. After completing the required gas phase reaction, the inflow of trichlorosilane and carbon dioxide gas is stopped, the temperature of the reactor is lowered, and the process is completed.
An i-board 15 is obtained. During this cooling process, the polycrystalline Si plate 15
Each part contracts according to its respective coefficient of thermal expansion, but since the force of the bulk polycrystalline Si in the separation groove 2 to index the walls of the separation groove 2 is weak, wafer curvature due to the presence of the separation groove 2 is reduced. , the curvature of the polycrystalline Si plate 15 is small.
以上、本発明によれば、分離溝による湾曲を排除するた
め、誘電体分離基板を歩留り良く製造できる。As described above, according to the present invention, since the curvature caused by the isolation groove is eliminated, a dielectric isolation substrate can be manufactured with high yield.
第１図（ａ）〜（ｃ）は本発明の一実施例を示す誘電体
分離基板の断面図、第２図（ａ）〜（ｃ）は技術分野を
説明する誘電体分離基板の断面図、第３図は従来法によ
って得られた誘電体分離基板を示す断面図、第４図は本
発明の原理を示す誘電体分離基板の断面図である。
１・・・半導体単結晶板、２・・・溝、３・・・誘電体
膜、筋１図
（α）
（Ｃ）
皐２図
（ｂン
（０）。
第３図
不生図
？FIGS. 1(a) to (c) are cross-sectional views of a dielectric separation substrate showing one embodiment of the present invention, and FIGS. 2(a) to (c) are cross-sectional views of a dielectric separation substrate illustrating the technical field. 3 is a sectional view showing a dielectric isolation substrate obtained by a conventional method, and FIG. 4 is a sectional view of a dielectric isolation substrate illustrating the principle of the present invention. 1...Semiconductor single crystal plate, 2...Groove, 3...Dielectric film, line Figure 1 (α) (C) Figure 2 (bn (0)). Figure 3: Insei diagram?
Claims (1)
膜で覆われている単結晶半導体板の誘電体膜上に、該溝
が酸素を含有しない多結晶半導体で満たされるように酸
素を含有しない多結晶半導体層を形成し、然る後、酸素
を含有する多結晶半導体層を形成することを特徴とする
誘電体分離基板の製造法。1. On a dielectric film of a single crystal semiconductor board having a groove on one principal surface and at least the surface of the principal surface being covered with a dielectric film, the groove is filled with a polycrystalline semiconductor that does not contain oxygen. 1. A method for manufacturing a dielectric isolation substrate, comprising: first forming a polycrystalline semiconductor layer that does not contain oxygen, and then forming a polycrystalline semiconductor layer containing oxygen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4758987A JPS63215050A (en) | 1987-03-04 | 1987-03-04 | Manufacture of dielectric isolation substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4758987A JPS63215050A (en) | 1987-03-04 | 1987-03-04 | Manufacture of dielectric isolation substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63215050A true JPS63215050A (en) | 1988-09-07 |
Family
ID=12779438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4758987A Pending JPS63215050A (en) | 1987-03-04 | 1987-03-04 | Manufacture of dielectric isolation substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63215050A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5576241A (en) * | 1994-05-31 | 1996-11-19 | Fuji Electric Co., Ltd. | Method of separating semiconductor wafer with dielectrics |
-
1987
- 1987-03-04 JP JP4758987A patent/JPS63215050A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5576241A (en) * | 1994-05-31 | 1996-11-19 | Fuji Electric Co., Ltd. | Method of separating semiconductor wafer with dielectrics |
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