JPS63205992A - Method of forming wiring board - Google Patents
Method of forming wiring boardInfo
- Publication number
- JPS63205992A JPS63205992A JP3790787A JP3790787A JPS63205992A JP S63205992 A JPS63205992 A JP S63205992A JP 3790787 A JP3790787 A JP 3790787A JP 3790787 A JP3790787 A JP 3790787A JP S63205992 A JPS63205992 A JP S63205992A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- conductor layer
- forming
- wiring board
- wiring groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 13
- 239000004020 conductor Substances 0.000 claims description 24
- 238000001312 dry etching Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 30
- 239000010408 film Substances 0.000 description 11
- 239000010409 thin film Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000011651 chromium Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229960003280 cupric chloride Drugs 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は配線板の製造方法に係り、特に高アスペクト比
の配線を高密度に形成するのに好適な薄膜配線板の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a wiring board, and more particularly to a method for manufacturing a thin film wiring board suitable for forming wiring with a high aspect ratio at a high density.
従来、薄膜配線板は、絶縁基板上にＣｒ薄膜、Ｃｕ薄膜
を順次蒸着法で形成し、Ｃｕ薄膜上に７オトレジストを
塗布し、このレジストを露光、現像してエツチングマス
クを形成し、上記Ｃｒ薄膜、Ｃｕ薄膜を選択的にエツチ
ング除去して配線パターンを形成して薄膜配線板として
いた。上記の薄膜配線板の製造方法としては、例えばプ
ロシーディング番オブ・イー・シー・シーｅオブ・ザ・
サーチイーフォース−イー・シー・シー（Ｐｒｏｃｅｅ
ｄｉｎｇｓ ｏｆＥ、Ｃ，Ｃｏｆ ｔｈｅ ３４ｔｈ
Ｂ、Ｃ，Ｃ）、 ８２〜８７゜１９８４年に示されて
いる。Conventionally, thin film wiring boards have been produced by forming a Cr thin film and a Cu thin film on an insulating substrate sequentially by vapor deposition, applying a 7-photoresist on the Cu thin film, exposing and developing this resist to form an etching mask, and etching the Cr thin film. The thin film and Cu thin film were selectively etched and removed to form a wiring pattern to form a thin film wiring board. As a method for manufacturing the above-mentioned thin film wiring board, for example, Proceedings of the
Search E-Force - E.C.C. (Procee)
dings ofE,C,Cof the 34th
B, C, C), 82-87° 1984.
上記従来技術においては、厚さ５μｍ程度の配線パター
ンでは高密度配線ができる。しかし、例えば厚さ２０μ
ｍの配線パターンを高密度に形成しようとすると、配線
の壁面がエツチングによってテ−バー状（０状）となり
、特にアスペクト比の高〔問題点を解決するための手段
〕
上記目的は、絶縁層にドライエツチングによりテーパー
のない垂直な壁面を有する配線溝を加工し、該配線溝が
埋まるように導体層を形成した後上記工程によって該配
線溝の中央に凹部が生じた上記導体層にレジスト膜を形
成し、上記レジスト膜の全面をドライエツチングして上
記凹部にレジスト膜を残存させた後、上記配線溝内以外
の該導体層を除去することによって達成される。In the above-mentioned conventional technology, high-density wiring can be achieved with a wiring pattern having a thickness of about 5 μm. However, for example, the thickness is 20μ
When an attempt is made to form a wiring pattern of m with high density, the wall surface of the wiring becomes a taber shape (0 shape) due to etching, especially when the aspect ratio is high. After processing a wiring groove with vertical walls without a taper by dry etching and forming a conductor layer to fill the wiring groove, a resist film is applied to the conductor layer in which a recess is formed in the center of the wiring groove by the above process. This is accomplished by forming a resist film, dry etching the entire surface of the resist film to leave the resist film in the recess, and then removing the conductor layer except in the wiring trench.
本発明においては、所定の位置にドライエツチングによ
り垂直な配線溝を加工し、該配線溝が埋まる厚さに導体
層を形成して該配線溝内の導体層の中央に凹部を生じさ
せる。In the present invention, a vertical wiring groove is formed at a predetermined position by dry etching, a conductor layer is formed to a thickness that fills the wiring groove, and a recess is created at the center of the conductor layer within the wiring groove.
ついで、上記導体層上にレジスト膜を形成すると、該レ
ジスト層の上記凹部が他の部分よりも極端に厚く形成さ
れる。Then, when a resist film is formed on the conductor layer, the recessed portion of the resist layer is formed to be extremely thicker than other portions.
しかるのち、このレジスト膜を全面ドライエツチングす
ると、上記凹部内のレジスト膜は膜厚が厚いため残存す
る。Thereafter, when the entire surface of this resist film is dry-etched, the resist film within the recesses remains because it is thick.
この状態で上記配線溝以外の上記導体層を除去すると、
上記凹部下の導体層は、上記残存したレジスト膜がマス
クとなって除去されず、上記配線溝内が上記平坦な導体
層によって充填される。If the conductor layer other than the wiring groove is removed in this state,
The conductor layer under the recess is not removed because the remaining resist film serves as a mask, and the inside of the wiring trench is filled with the flat conductor layer.
このようにすれば、テーパーのない垂直な配線溝内に導
体層を充填するので、テーパーのない垂 、直な膜厚の
大きい配線が形成できる。In this way, since the conductor layer is filled in the vertical wiring groove without a taper, it is possible to form a vertical wiring with a large thickness without a taper.
配線間のピッチは、加工溝間のピンチによって定まる。The pitch between the wires is determined by the pinch between the processed grooves.
この加工溝はテーパーのない垂直な壁面を有する溝であ
るから加工溝間のピッチを狭くすることができ、配線間
ピッチも狭くすることかできる。Since this processed groove has a vertical wall surface without a taper, the pitch between the processed grooves can be narrowed, and the pitch between the wiring lines can also be narrowed.
以下、本発明の実施例である第１図（ａ）乃至（ｇ）に
より説明する。Embodiments of the present invention will be explained below with reference to FIGS. 1(a) to 1(g).
第１図（ａ）に示すように、セラミック板もしくは厚膜
多層配線板等の基板１上に、例えは日立化成工業株式会
社製のビー・アイ・キー−（ＰＩＱ）（商品名）をスピ
ンナにより均一に回転塗布した後、熱処理して有機絶縁
層のポリイミド膜からなる層間絶縁層２を形成し、さら
に第１図（ｂ）に示すように通常のドライエツチング工
程により層間絶縁層２の所定の位置に壁面が当直な形状
を有する配線溝３を形成する。As shown in FIG. 1(a), for example, BI-Key (PIQ) (trade name) manufactured by Hitachi Chemical Co., Ltd. is placed on a substrate 1 such as a ceramic board or a thick film multilayer wiring board using a spinner. After uniformly spin-coating, heat treatment is performed to form an interlayer insulating layer 2 made of a polyimide film of an organic insulating layer, and further, as shown in FIG. A wiring groove 3 having a shape in which the wall surface is on duty is formed at the position.
ついで、第１図（ｃ）に示すように銅又はクロムおよび
銅から成る導体層４を蒸着法により基板１上に成膜する
。このとき、導体層４の中央の配線溝３部分には凹部５
が発生する。Next, as shown in FIG. 1(c), a conductive layer 4 made of copper or chromium and copper is formed on the substrate 1 by vapor deposition. At this time, a recess 5 is formed in the wiring groove 3 at the center of the conductor layer 4.
occurs.
しかるのち、上記導体層４上に例えば東京応化株式会社
製のオー・エム・アール（ＯＭＲ）−８５（商品名）を
スピンナにより回転塗布して、第１図（ｄ）に示すよう
にレジスト層６を形成する。このとき、ホトレジスト層
６は、第１図（ｄ）から明らかなように導体層４の凹部
５上では他の部分よりも極端に厚く形成される。Thereafter, for example, OMR-85 (trade name) manufactured by Tokyo Ohka Co., Ltd. is spin-coated on the conductor layer 4 using a spinner to form a resist layer as shown in FIG. 1(d). form 6. At this time, as is clear from FIG. 1(d), the photoresist layer 6 is formed extremely thicker on the recess 5 of the conductor layer 4 than on other parts.
ついで、平行平板型のドライエツチング装置により酸素
プラズマを用いてホトレジストＮ６の全面にドライエツ
チングする。このとき、同ｆｉＵ（ｓ）に示すように、
凹部５内のホトレジスト膜６は膜厚が厚いため残存する
。Next, the entire surface of the photoresist N6 is dry etched using oxygen plasma using a parallel plate type dry etching apparatus. At this time, as shown in fiU(s),
The photoresist film 6 in the recess 5 remains because it is thick.
しかるのち、例えば塩化第２銅系のエツチング液を用い
て、同図（ｆ）に示すように、配線溝３の内部以外の導
体層４を除去する。このエツチング工程において、導体
層４の凹部５に残存したホトレジスト層６がマスクとな
り、この部分の導体層はエツチングされず、配線溝内部
にのみ導体層を充填することができる。Thereafter, the conductor layer 4 other than the inside of the wiring trench 3 is removed using, for example, a cupric chloride-based etching solution, as shown in FIG. 2(f). In this etching step, the photoresist layer 6 remaining in the recess 5 of the conductor layer 4 serves as a mask, and the conductor layer in this portion is not etched, so that only the inside of the wiring groove can be filled with the conductor layer.
ついて、同図（ｇ）に示すように、ホトレジスト層６を
エツチングにより除去し、配線基板を形成する。Thereafter, as shown in FIG. 3(g), the photoresist layer 6 is removed by etching to form a wiring board.
本発明によれば、ドライエツチングにより形成した垂直
な壁面を有する配線溝内部に平坦な導体層を充填できる
ので、アスペクト比が高く膜厚の厚い配線を狭い配線ピ
ッチで形成することができ、これによって高密度の配線
基板を得ることができる。According to the present invention, it is possible to fill a flat conductor layer inside a wiring trench having vertical walls formed by dry etching, so that thick wiring with a high aspect ratio and film thickness can be formed with a narrow wiring pitch. A high-density wiring board can be obtained by this method.
第１図（ａ）乃至（ｇ）は本発明の一実施例である配線
基板の製造方法を示す工程図である。
１・・・多層配線基板等の基板、２・・・層間絶縁層、
３・・・配線溝、４・・・導体層、５・・・導体層の凹
部、６・・・ホトレジスト層。FIGS. 1(a) to 1(g) are process diagrams showing a method for manufacturing a wiring board according to an embodiment of the present invention. 1... Substrate such as a multilayer wiring board, 2... Interlayer insulation layer,
3... Wiring groove, 4... Conductor layer, 5... Concave portion of conductor layer, 6... Photoresist layer.
Claims (1)
うに導体層を形成する工程と、上記工程によって該配線
溝の中央に凹部が生じた上記導体層にレジスト膜を形成
する工程と、上記レジスト膜の全面をドライエッチング
して上記凹部にレジスト膜を残存させる工程と、上記配
線溝内以外の該導体層を除去する工程とを含むことを特
徴とする配線板の形成方法。 ２、上記配線溝をドライエッチングによって垂直な断面
形状に加工することを特徴とする特許請求の範囲第１項
記載の配線板の形成方法。 ３、上記導体層を指向性を有する成膜法によって形成す
ることを特徴とする特許請求の範囲第１項記載の配線板
の形成方法。[Claims] 1. After forming a wiring groove in an insulating layer, forming a conductor layer so as to fill the wiring groove, and forming a concave part in the center of the wiring groove in the conductor layer by the above process. The method is characterized by comprising the steps of forming a resist film, dry etching the entire surface of the resist film to leave the resist film in the recess, and removing the conductor layer other than within the wiring groove. How to form a wiring board. 2. The method of forming a wiring board according to claim 1, wherein the wiring groove is processed into a vertical cross-sectional shape by dry etching. 3. The method for forming a wiring board according to claim 1, wherein the conductor layer is formed by a directional film forming method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3790787A JPS63205992A (en) | 1987-02-23 | 1987-02-23 | Method of forming wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3790787A JPS63205992A (en) | 1987-02-23 | 1987-02-23 | Method of forming wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63205992A true JPS63205992A (en) | 1988-08-25 |
Family
ID=12510612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3790787A Pending JPS63205992A (en) | 1987-02-23 | 1987-02-23 | Method of forming wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63205992A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017076187A (en) * | 2015-10-13 | 2017-04-20 | 大日本印刷株式会社 | Method for producing metal pattern substrate, metal pattern substrate, and display device with touch position detection function |
| JP2018085394A (en) * | 2016-11-22 | 2018-05-31 | 京セラ株式会社 | Wiring board |
-
1987
- 1987-02-23 JP JP3790787A patent/JPS63205992A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017076187A (en) * | 2015-10-13 | 2017-04-20 | 大日本印刷株式会社 | Method for producing metal pattern substrate, metal pattern substrate, and display device with touch position detection function |
| JP2018085394A (en) * | 2016-11-22 | 2018-05-31 | 京セラ株式会社 | Wiring board |
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