JPS63181515A - Automatic delay time adjusting system - Google Patents
Automatic delay time adjusting systemInfo
- Publication number
- JPS63181515A JPS63181515A JP62013206A JP1320687A JPS63181515A JP S63181515 A JPS63181515 A JP S63181515A JP 62013206 A JP62013206 A JP 62013206A JP 1320687 A JP1320687 A JP 1320687A JP S63181515 A JPS63181515 A JP S63181515A
- Authority
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- Japan
- Prior art keywords
- transmission line
- time
- adjusted
- time difference
- delay time
- Prior art date
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- 230000005540 biological transmission Effects 0.000 claims abstract description 99
- 238000000034 method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000001902 propagating effect Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔概要〕
基準伝送路及び被調整伝送路の双方に往路と伝播時間が
等しい復路を設け、それぞれの送端及び戻り・端でのパ
ルスの時間差を検出し、これを基準伝送路及び被調整伝
送路の受端での時間差に比例する電圧に変換し、この電
圧で可変遅延回路を制御することにより、基準伝送路及
び被調整伝送路の受端でのクロックの到達時間が一敗す
るように被調整伝送路の遅延時間を自動的に調整する。[Detailed Description of the Invention] [Summary] A return path with equal propagation time as the outgoing path is provided on both the reference transmission line and the adjusted transmission line, and the time difference between the pulses at each sending end and return end is detected and calculated. By converting to a voltage proportional to the time difference at the receiving ends of the reference transmission line and the adjusted transmission line and controlling the variable delay circuit with this voltage, the arrival of the clock at the receiving ends of the reference transmission line and the adjusted transmission line is controlled. To automatically adjust the delay time of a transmission line to be adjusted so that time is lost.
本発明は、遅延時間自動調整方式、特に2か所以上に同
時刻にクロックが到着するように遅延時間を自動的に調
整する方式に関する。The present invention relates to an automatic delay time adjustment method, and particularly to a method for automatically adjusting delay time so that clocks arrive at two or more locations at the same time.
同期式論理回路におけるクロックは、1か所で発生し、
クロックを使用する複数の回路に同時刻に到着させなけ
ればならない。しかし、クロック発生回路からそれぞれ
のクロック使用回路までの距離や伝送路の持つ伝播速度
が等しくないため。The clock in a synchronous logic circuit is generated in one place,
The clock must arrive at the same time to multiple circuits that use it. However, this is because the distances from the clock generation circuit to each clock usage circuit and the propagation speeds of the transmission paths are not equal.
何らかの方法で遅延時間を調整する必要がある。You need to adjust the delay time in some way.
従来の遅延時間調整方式は。The conventional delay time adjustment method.
(1)伝送路の伝播速度が一定であると見做せる場合に
は1等長配線を行う。(1) If the propagation speed of the transmission path can be considered constant, use equal length wiring.
(2)遅延時間を計算によって求められる場合には、遅
延時間が等しくなるように回路設計を行う。(2) If the delay time is determined by calculation, design the circuit so that the delay times are equal.
(3)調整可能な遅延回路を設けておき、製造後。(3) After manufacturing, an adjustable delay circuit is provided.
人手により調整を行う。Adjustments are made manually.
などであり、遅延時間を自動的に調整する方式は。etc., and what is the method for automatically adjusting the delay time?
従来存在しなかった。It didn't exist before.
従来の(1)及び(2)の方式では、多大な設計工数を
必要とし、 (3)の方式では+ jF!整工数を必要
とするばかりでなく、製品ごとに調整しなければならな
いという問題があった。Conventional methods (1) and (2) require a large amount of design man-hours, and method (3) requires + jF! There is a problem in that not only does it require a lot of man-hours, but it also has to be adjusted for each product.
本発明は、基準伝送路及び被調整伝送路の双方に往路と
伝播時間が等しい復路を設け、それぞれの送端及び戻り
端でのパルスの時間差を検出し。In the present invention, a return path having the same propagation time as the outgoing path is provided on both the reference transmission path and the adjusted transmission path, and the time difference between the pulses at the respective sending and returning ends is detected.
これを基準伝送路及び被調整伝送路の受端での時間差に
比例する電圧に変換し、この電圧で可変遅延回路を制御
することにより、基準伝送路及び被調整伝送路の受端で
のクロックの到達時間が一致するように被調整伝送路の
遅延時間を自動的に調整するものである。By converting this into a voltage proportional to the time difference at the receiving ends of the reference transmission line and the adjusted transmission line, and controlling the variable delay circuit with this voltage, the clock at the receiving ends of the reference transmission line and the adjusted transmission line is The delay time of the adjusted transmission path is automatically adjusted so that the arrival times of the two match.
第1図は2本発明の基本構成を示す図である。FIG. 1 is a diagram showing the basic configuration of the present invention.
第1図において、Aは基準伝送路の送端、Bは基準伝送
路の受端、Cは基準伝送路の戻り端5Dは被調整伝送路
の送端、Eは被調整伝送路の受端。In Figure 1, A is the sending end of the reference transmission line, B is the receiving end of the reference transmission line, C is the return end of the reference transmission line, 5D is the sending end of the adjusted transmission line, and E is the receiving end of the adjusted transmission line. .
Fは被調整伝送路の戻り端、1はクロック発生回路、2
は遅延時間自動調整回路、3は第1時間検出器、4は第
2時間検出器、5は時間差比較器。F is the return end of the transmission line to be adjusted, 1 is the clock generation circuit, 2
3 is a first time detector, 4 is a second time detector, and 5 is a time difference comparator.
6は可変遅延回路である。6 is a variable delay circuit.
伝送路(A−B)は、基準伝送路であり、il!!常。The transmission line (A-B) is a reference transmission line, and il! ! Always.
伝播時間が最も長い伝送路を選択する。Select the transmission path with the longest propagation time.
伝送路(B −C)は、基準伝送路の復路であり。The transmission path (B-C) is a return path of the reference transmission path.
基準伝送路(A−B)と伝t!時間が同じになるように
設定する。Standard transmission line (A-B) and transmission! Set the times to be the same.
伝送路(D −E)は、被調整伝送路である。The transmission line (D-E) is a transmission line to be adjusted.
伝送路(E−F)は、被調整伝送路の復路であり、被調
整伝送路(D−E)と伝播時間が同じになるように設定
する。The transmission path (E-F) is a return path of the adjusted transmission path, and is set so that the propagation time is the same as that of the adjusted transmission path (D-E).
クロック発生回路1は、論理回路内で使用するクロック
を発生するための回路である。The clock generation circuit 1 is a circuit for generating clocks used within the logic circuit.
遅延時間自動調整回路2は、第1時間検出器3゜第2時
間検出器45時間差比較器5及び可変遅延回路6からな
る。The automatic delay time adjustment circuit 2 includes a first time detector 3, a second time detector 45, a time difference comparator 5, and a variable delay circuit 6.
第1時間検出器3は、基準伝送路(A−B)及び被調整
伝送路(D −E) ’の送端(A、 D)での時間
差(G)を検出する。The first time detector 3 detects the time difference (G) at the sending ends (A, D) of the reference transmission line (A-B) and the adjusted transmission line (D-E)'.
第2時間検出器4は、基準伝送路(A−B)及び被調整
伝送路(D −E)の復路(B−C,E−F)の戻り端
(C,F)での時間差(H)を検出する。The second time detector 4 detects a time difference (H ) is detected.
時間差比較器5は1時間差(G)及び(H)を比較して
、その差に相当する電圧を出力する。The time difference comparator 5 compares the one time difference (G) and (H) and outputs a voltage corresponding to the difference.
可変遅延回路6は1時間差比較器5の出力電圧により被
調整伝送路(D −E)の遅延時間を制御する。The variable delay circuit 6 controls the delay time of the transmission line to be adjusted (D-E) based on the output voltage of the one-time difference comparator 5.
〔作用〕
伝ti時間が最も長い伝送路を基準伝送路(A−B)と
して選定する。他の伝送路は、被調整伝送路<D−E)
として、送端(D)とクロック発生回路1との間に可変
遅延回路6を挿入する。[Operation] The transmission line with the longest propagation time is selected as the reference transmission line (A-B). Other transmission lines are adjusted transmission lines <D-E)
As such, a variable delay circuit 6 is inserted between the sending end (D) and the clock generation circuit 1.
基準伝送路(A−8)に基準伝送路(A−B)と伝播時
間が等しい復路(B−C)を設け、被調整伝送路(D−
E)に被調整伝送路(D−E)と伝19時間が等しい復
路(E−F)を設ける。A return path (B-C) having the same propagation time as the reference transmission path (A-B) is provided on the reference transmission path (A-8), and a return path (B-C) having the same propagation time as the standard transmission path (A-B) is provided.
E) is provided with a return path (E-F) having the same transmission time as the adjusted transmission path (D-E).
クロック発生回路lで発生されたクロックは。The clock generated by clock generation circuit l is.
基1表伝送路(A−B)を伝播して受端(B)に到達し
た後、復路(B−C)を伝播して戻り端(C)に到達す
る。一方1被調整伝送路(D −E)を伝播するクロッ
クは、可変遅延回路6により遅延された後、被調整伝送
路(D−E)を伝播して受端(E)に到達した後、復路
(E−F)を伝播して戻り端(F)に到達する。After propagating through the base 1 transmission line (A-B) and reaching the receiving end (B), it propagates along the return path (B-C) and reaching the return end (C). On the other hand, the clock propagating through the first adjusted transmission line (D-E) is delayed by the variable delay circuit 6, and after propagating through the adjusted transmission line (D-E) and reaching the receiving end (E), It propagates along the return path (E-F) and reaches the return end (F).
可変遅延回路6の遅延時間は、始め適当な値に設定して
おく。The delay time of the variable delay circuit 6 is initially set to an appropriate value.
第1時間検出器3は、基準伝送路(A−B)の送端(A
)及び被調整伝送路(D−E)の送端(D)のクロック
の排他的論理和(EX−OR)の否定(G=A(E)D
)をとる。The first time detector 3 is connected to the sending end (A-B) of the reference transmission path (A-B).
) and the exclusive OR (EX-OR) of the clock at the sending end (D) of the transmission line to be adjusted (D-E) (G=A(E)D
).
第2時間検出器4は、基準伝送路(A−B)の復路(B
−C)の戻り端(C)及び被調整伝送路(D−E)の
復路(E−F)の戻り端(F)のクロックの排他的論理
和(EX−1OR>の否定(H=C■F)をとる。The second time detector 4 detects the return path (B) of the reference transmission path (A-B).
Negation (H=C ■Take F).
時間差比較器5は、第1時間検出器3の出力(G)及び
第2時間検出器4の出力([I)の時間差を求めて、基
準伝送路(A−B)の受端(B)及び被調整伝送路(D
−E)の受端(E)の時間差に比例する電圧(J)を出
力する。The time difference comparator 5 calculates the time difference between the output (G) of the first time detector 3 and the output ([I) of the second time detector 4, and calculates the time difference between the output ([I]) of the first time detector 3 and the receiving end (B) of the reference transmission path (A-B). and adjusted transmission line (D
-E) outputs a voltage (J) proportional to the time difference at the receiving end (E).
可変遅延回路6は1時間差比較器5の出力電圧(J)に
より遅延時間を制御して、クロック発生回路lで発生さ
れたクロックが基準伝送路(A−B)の受端(B)及び
被調整伝送路(D−E)の受端(E)に同じ時間に到達
するように、自動的に調整する。The variable delay circuit 6 controls the delay time using the output voltage (J) of the 1-time difference comparator 5, so that the clock generated by the clock generation circuit 1 is transmitted to the receiving end (B) and the receiving end (B) of the reference transmission path (A-B). Automatic adjustment is made so that the receiving end (E) of the adjustment transmission line (D-E) is reached at the same time.
第2図は2つの伝送路の受端におけるタイミングが一致
している状態を示すタイムチャート、第3図は被調整伝
送路のタイミングが速い状態を示すタイムチャート、第
4図は被調整伝送路のタイミングが遅い状態を示すタイ
ムチャートである。Figure 2 is a time chart showing a state where the timings at the receiving ends of the two transmission lines match, Figure 3 is a time chart showing a state where the timing of the adjusted transmission line is fast, and Figure 4 is the adjusted transmission line. 3 is a time chart showing a state in which the timing is slow.
第5図は9本発明の1実施例構成を示す図である。 FIG. 5 is a diagram showing the configuration of one embodiment of the present invention.
第5図において、11はクロック発生回路、12は遅延
時間自動調整回路、13は位相比較器。In FIG. 5, 11 is a clock generation circuit, 12 is a delay time automatic adjustment circuit, and 13 is a phase comparator.
14は低域通過フィルタ、15は電圧制御遅延回路であ
る。14 is a low pass filter, and 15 is a voltage controlled delay circuit.
位相比較器13は、基準伝送路(A−B)及び被調整伝
送路(D −E)の送端信号(A、D)の排他的論理和
(E X −OR)の否定(N OT)をとることによ
り送端位相差信号(G=A+D)を作り、基準伝送路(
A−B)及び被調整伝送路(D−E)の各復路(B−C
,E−F)の戻り端信号(C,F)の排他的論理和(E
X−OR)の否定(NOT)をとることにより戻り端位
相差信号(H=C■F)を作る。The phase comparator 13 performs a negation (NOT) of the exclusive OR (EX-OR) of the sending end signals (A, D) of the reference transmission line (A-B) and the adjusted transmission line (D-E). A sending end phase difference signal (G=A+D) is created by taking
A-B) and each return path (B-C) of the adjusted transmission path (D-E)
, E-F) of the return end signals (C, F) (E
A return end phase difference signal (H=C■F) is generated by taking the negation (NOT) of (X-OR).
第6図に位相比較器の例を示す。FIG. 6 shows an example of a phase comparator.
低域通過フィルタ14は、G端子のLo−期間とI(端
子のLow期間の差に対応した電圧を出力端子Jに出力
する。The low-pass filter 14 outputs to the output terminal J a voltage corresponding to the difference between the Lo period of the G terminal and the Low period of the I terminal.
第7図に低域if1過フィルタの例を示す。FIG. 7 shows an example of a low-pass if1 filter.
電圧制御遅延回路15は、低域通過フィルタ14の出力
電圧(J)により遅延時間を制御して。The voltage-controlled delay circuit 15 controls the delay time using the output voltage (J) of the low-pass filter 14.
クロック発生回路11で発生されたクロックが基準伝送
路(A−B)の受端(B)及び被調整伝送路(D −E
)の受端(E)に同じ時間に到達するように、自動的に
調整する。The clock generated by the clock generation circuit 11 is transmitted to the receiving end (B) of the reference transmission line (A-B) and the adjusted transmission line (D-E).
) to reach the receiving end (E) at the same time.
第8図(a)、 (b)に電圧制御遅延回路の例を示
す。FIGS. 8(a) and 8(b) show examples of voltage-controlled delay circuits.
第8図(a)の電圧制御遅延回路は、制御電圧入力端子
(J)に加えられた電圧をA / I)コンバータによ
りデジタル信号に変換し、このデジタル信号を用いて遅
延素子を通過する段数をマルチプレクサが切り換えるこ
とにより、遅延時間の調整を行う。The voltage-controlled delay circuit shown in FIG. 8(a) converts the voltage applied to the control voltage input terminal (J) into a digital signal using an A/I converter, and uses this digital signal to determine the number of stages that pass through the delay element. The delay time is adjusted by switching the multiplexer.
第8図(b)の電圧制御遅延回路は、遅延素子ごとに切
替回路を保有しており、遅延素子の持つ遅延時間を後段
の2倍の遅延時間になるように設定する。この例の電圧
制御遅延回路は、第8図(a)の電圧制御遅延回路より
広範囲に遅延時間を変化させることができる。その反面
、切り替えを各段で受は持つため、全体の最小遅延時間
は。The voltage controlled delay circuit shown in FIG. 8(b) has a switching circuit for each delay element, and sets the delay time of the delay element to be twice the delay time of the subsequent stage. The voltage controlled delay circuit of this example can vary the delay time over a wider range than the voltage controlled delay circuit of FIG. 8(a). On the other hand, since the receiver has switching at each stage, the overall minimum delay time is.
第8図(a)の電圧制御遅延回路より大きくなる。It is larger than the voltage controlled delay circuit shown in FIG. 8(a).
以上に述べた各構成要素を結合した全回路図の例を第9
図(a)、 (b)に示す。An example of a complete circuit diagram combining each component described above is shown in the 9th section.
Shown in Figures (a) and (b).
第9図(a)の例では、遅延時間を大きくしなければな
らないときに低域通過フィルタの出力電圧が上昇するよ
うに働くので5電圧制御遅延回路は制′4′n電圧が大
きいときに遅延時間が太き(なるように設計する必要が
ある。しかし、全体が逆であれば問題はない。In the example of FIG. 9(a), the output voltage of the low-pass filter increases when the delay time has to be increased, so the 5-voltage control delay circuit works when the control voltage is large. It is necessary to design so that the delay time is large.However, there is no problem if the whole thing is reversed.
第9図(b)の例は、クロックの周期に比べて伝送路の
伝播遅延時間が長い場合に有効である。The example shown in FIG. 9(b) is effective when the propagation delay time of the transmission line is longer than the clock cycle.
始め、保持回路オフ、分周回路オンの状態で動作を開始
し9回路全体が定常状態に入り、遅延時間の自動調整が
済んだ時点で保持回路をオン5分周回路をオフ状態にす
ることにより、安定な動作が得られる。At the beginning, the operation starts with the holding circuit off and the frequency dividing circuit on. When all 9 circuits enter a steady state and the automatic adjustment of the delay time is completed, the holding circuit is turned on and the 5 frequency dividing circuit is turned off. This provides stable operation.
本発明によれば、従来不可能であった伝送路の遅延時間
の自動調整が可能になる。According to the present invention, it becomes possible to automatically adjust the delay time of a transmission path, which was previously impossible.
第1図は本発明の基本構成を示す図、第2図は2つの伝
送路の受端におけるタイミングが一致している状態を示
すタイムチャート、第3図は被調整伝送路のタイミング
が速い状態を示すタイムチャート第4図は被調整伝送路
のタイミングが遅い状態を示すタイムチャート、第5図
は本発明の1実施例構成を示す図、第6図は位相比較器
の例を示す図、第7図は低域通過フィルタの例を示す図
、第8図(a)、 (b)は電圧制御遅延回路の例を
示す図、第9図(a)、 (b)は遅延時間自動調整
回路の全体図である。
第1図にお41で。
A:基準伝送路の送端
B:基準伝送路の受端
C:基準伝送路の戻り端
D=被調整伝送路の送端
E:被調整伝送路の受端
F:被調整伝送路の戻り端
l:クロノク発生回路
2:遅延時間自動調整回路
3:第1時間検出器
4;第2時間検出器
5:時間差比較器
6:可変遅延回路Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a time chart showing a state in which the timings at the receiving ends of two transmission lines match, and Fig. 3 is a state in which the timing of the adjusted transmission line is fast. 4 is a time chart showing a state in which the timing of the transmission line to be adjusted is slow, FIG. 5 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 6 is a diagram showing an example of a phase comparator. Figure 7 shows an example of a low-pass filter, Figures 8 (a) and (b) show an example of a voltage-controlled delay circuit, and Figures 9 (a) and (b) show automatic delay time adjustment. It is an overall diagram of the circuit. 41 in Figure 1. A: Sending end of the reference transmission line B: Receiving end of the reference transmission line C: Return end of the reference transmission line D = Sending end of the adjusted transmission line E: Receiving end of the adjusted transmission line F: Return of the adjusted transmission line Terminal l: Chronograph generation circuit 2: Delay time automatic adjustment circuit 3: First time detector 4; Second time detector 5: Time difference comparator 6: Variable delay circuit
Claims (1)
整伝送路(D−E)及び遅延時間調節回路をそなえた遅
延時間調整方式において、基準伝送路(A−B)と伝播
時間が等しい復路(B−C)及び被調整伝送路(D−E
)と伝播時間が等しい復路(E−F)並びに第1時間検
出器(3)、第2時間検出器(4)、時間差比較器(5
)、及び可変遅延回路(6)からなる遅延時間自動調整
回路(2)をもうけ、 第1時間検出器(3)により基準伝送路(A−B)の送
端(A)と被調整伝送路(D−E)の送端(D)との時
間差(G)を検出し、 第2時間検出器(4)により基準伝送路(A−B)の戻
り端(C)と被調整伝送路(D−E)の戻り端(F)と
の時間差(H)を検出し、 時間差比較器(5)により上記時間差(G)及び(H)
の時間差を比較して、基準伝送路(A−B)及び被調整
伝送路(D−E)の受端(B、E)における時間差に比
例する電圧(J)を発生させ、この電圧(J)により可
変遅延回路(6)の遅延時間を制御して基準伝送路(A
−B)及び被調整伝送路(D−E)の受端(B、E)で
のクロックの到達時間が一致するように被調整伝送路(
D−E)の遅延時間を自動的に調整することを特徴とす
る遅延時間自動調整方式。[Claims] In a delay time adjustment method including a clock generation circuit (1), a reference transmission line (A-B), a transmission line to be adjusted (D-E), and a delay time adjustment circuit, the reference transmission line (A -B) and the return path (B-C) with equal propagation time and the adjusted transmission path (D-E
) and the return path (E-F) with the same propagation time, the first time detector (3), the second time detector (4), and the time difference comparator (5
), and a delay time automatic adjustment circuit (2) consisting of a variable delay circuit (6). (D-E) and the sending end (D) are detected, and the second time detector (4) detects the time difference (G) between the return end (C) of the reference transmission line (A-B) and the adjusted transmission line ( The time difference (H) with the return end (F) of D-E) is detected, and the time difference (G) and (H) are detected by the time difference comparator (5).
A voltage (J) proportional to the time difference at the receiving ends (B, E) of the reference transmission line (A-B) and the adjusted transmission line (D-E) is generated by comparing the time differences between the two. ) to control the delay time of the variable delay circuit (6) to control the reference transmission line (A
-B) and the adjusted transmission line (D-E) so that the clock arrival times at the receiving ends (B, E) of the adjusted transmission line (D-E) match.
A delay time automatic adjustment method characterized in that the delay time of D-E) is automatically adjusted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62013206A JPS63181515A (en) | 1987-01-22 | 1987-01-22 | Automatic delay time adjusting system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62013206A JPS63181515A (en) | 1987-01-22 | 1987-01-22 | Automatic delay time adjusting system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63181515A true JPS63181515A (en) | 1988-07-26 |
Family
ID=11826681
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62013206A Pending JPS63181515A (en) | 1987-01-22 | 1987-01-22 | Automatic delay time adjusting system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63181515A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06149408A (en) * | 1992-11-12 | 1994-05-27 | Nec Corp | Integrated circuit device |
JP2009008807A (en) * | 2007-06-27 | 2009-01-15 | Sharp Corp | Image comparison device, program, and image comparison method |
JP2016039423A (en) * | 2014-08-06 | 2016-03-22 | 日本電気株式会社 | Clock signal distribution circuit, clock signal distribution method, and clock signal distribution program |
CN106325360A (en) * | 2015-06-26 | 2017-01-11 | 盛微先进科技股份有限公司 | Apparatus and method for dynamic clock adjustment |
CN111077231A (en) * | 2019-12-16 | 2020-04-28 | 华南理工大学 | Ultrasonic detection method and equipment for transmitting reference phase discrimination |
-
1987
- 1987-01-22 JP JP62013206A patent/JPS63181515A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06149408A (en) * | 1992-11-12 | 1994-05-27 | Nec Corp | Integrated circuit device |
JP2009008807A (en) * | 2007-06-27 | 2009-01-15 | Sharp Corp | Image comparison device, program, and image comparison method |
JP2016039423A (en) * | 2014-08-06 | 2016-03-22 | 日本電気株式会社 | Clock signal distribution circuit, clock signal distribution method, and clock signal distribution program |
CN106325360A (en) * | 2015-06-26 | 2017-01-11 | 盛微先进科技股份有限公司 | Apparatus and method for dynamic clock adjustment |
CN111077231A (en) * | 2019-12-16 | 2020-04-28 | 华南理工大学 | Ultrasonic detection method and equipment for transmitting reference phase discrimination |
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