JPS63181469A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63181469A JPS63181469A JP62014716A JP1471687A JPS63181469A JP S63181469 A JPS63181469 A JP S63181469A JP 62014716 A JP62014716 A JP 62014716A JP 1471687 A JP1471687 A JP 1471687A JP S63181469 A JPS63181469 A JP S63181469A
- Authority
- JP
- Japan
- Prior art keywords
- internal circuit
- mos
- voltage
- type transistor
- ground line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000001681 protective effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、静電破壊を防ぐ保護素子を有した半導体装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having a protection element for preventing electrostatic damage.
従来の技術
近年、半導体装置は、大規模集積化に伴う微細化により
、従来以上の静電耐圧を有した半導体装置が要望されて
いる。2. Description of the Related Art In recent years, as semiconductor devices have become smaller due to large-scale integration, there has been a demand for semiconductor devices having electrostatic withstand voltage higher than that of conventional semiconductor devices.
以下に従来の静電破壊保護素子を有した半導体装置につ
いて述べる。A semiconductor device having a conventional electrostatic discharge protection element will be described below.
第３図は、従来の半導体装置の静電破壊保護素子の構成
を示すものである。第３図において、１は外部信号入力
端子、２は保護抵抗、３はＭ ＯＳ型トランジスタ、４
は内部回路ブロック、５は等価的接地線配線抵抗を示し
ている。FIG. 3 shows the structure of a conventional electrostatic breakdown protection element for a semiconductor device. In Fig. 3, 1 is an external signal input terminal, 2 is a protection resistor, 3 is an MOS type transistor, and 4 is an external signal input terminal.
5 represents an internal circuit block, and 5 represents an equivalent ground line wiring resistance.
以上の様に構成された半導体装置について、以下その動
作について説明する。The operation of the semiconductor device configured as described above will be described below.
まず、ＭＯ８型トランジスタ３のドレイン部３１の、電
圧電流特性を第４１図に示す。ドレイン部３１に正の電
圧が印加された場合は、ブレークダウン電圧Ｖｌに達す
るまで電流は流れない。また、負の電圧が印加された場
合は、ドレイン・基板間のＰＮ接合のビルトイン電圧Ｖ
２に達した時点で電流が流れだす。従って通常の使用に
おいては、外部信号はビルトイン電圧Ｖ２とブレークダ
ウン電圧Ｖ、との間で印加されるので、ＭＯ８型トラン
ジスタ３は動作しない。しかし、外部信号入力端子１に
、急峻な、サージ電圧が、印加された場合は、前記各電
圧Ｖ、、Ｖ２を越えるため、ＭＯ８型トランジスタ３に
電流が流れ、そのドレイン部３１の電圧がブレークダウ
ン電圧Ｖ１もしくはビルトイン電圧ｖ２近傍に抑えられ
、内部回路に過大なサージ電圧が印加されない。これに
より、内部回路のサージ電圧による破壊を防止する事が
できる。First, FIG. 41 shows the voltage-current characteristics of the drain section 31 of the MO8 transistor 3. When a positive voltage is applied to the drain portion 31, no current flows until the breakdown voltage Vl is reached. In addition, when a negative voltage is applied, the built-in voltage V of the PN junction between the drain and the substrate
When it reaches 2, the current starts flowing. Therefore, in normal use, an external signal is applied between the built-in voltage V2 and the breakdown voltage V, so that the MO8 type transistor 3 does not operate. However, when a steep surge voltage is applied to the external signal input terminal 1, the voltages V, V2 are exceeded, so a current flows through the MO8 type transistor 3, and the voltage at its drain part 31 breaks. The down voltage is suppressed to around V1 or built-in voltage V2, and no excessive surge voltage is applied to the internal circuit. This can prevent damage to the internal circuit due to surge voltage.
発明が解決しようとする問題点
しかしながら上記の従来の構成では、外部信号入力端子
１と内部回路４とが半導体装置内で離れている場合には
、等価的接地線配線抵抗５が無視できない大きさとなり
、過大なサージ電圧が印加されたときにＭＯＳ型トラン
ジスタ３に流れる電流ｉと、等価的接地線配線抵抗５の
抵抗値Ｒとの積で表わされる電位分だけ、ＭＯＳ型トラ
ンジスタ３のソース部３２が変動し、サージ電圧をＭＯ
Ｓトランジスタ３で十分抑制できないという欠点を有し
ていた。その様子を第５図に示す。（ａ）は、外部信号
入力端子に印加されたサージ電圧波形であり、（ｂ）は
、第３図中のＭＯＳ型トランジスタ３のドレイン部３１
における電圧波形である。通常、等価的接地線配線抵抗
５が無視できる程小さい場合は、図中点線で示されるよ
うに、印加されたサージ電圧は、ブレークダウン電圧ｖ
１ならびにビルトイン電圧Ｖ２の間に、十分抑制される
。しかし、接地線配線抵抗が大きくなってくると、ＭＯ
Ｓ型トランジスタ３のソース部３２の電位が、正のサー
ジ電圧の場合は、正の方向に、負のサージ電圧印加の場
合は、負の方向に、それぞれ、図中Ｖ３で示される分だ
け変動し、したがって、内部回路４に印加される電圧が
増大する。これが、半導体装置のサージ耐圧を低下させ
る要因となるのである。Problems to be Solved by the Invention However, in the conventional configuration described above, when the external signal input terminal 1 and the internal circuit 4 are separated within the semiconductor device, the equivalent ground line wiring resistance 5 becomes too large to be ignored. When an excessive surge voltage is applied, the source portion of the MOS transistor 3 is increased by the potential represented by the product of the current i flowing through the MOS transistor 3 and the resistance value R of the equivalent ground line wiring resistance 5. 32 fluctuates and the surge voltage is MO
This has the disadvantage that the S transistor 3 cannot sufficiently suppress the noise. The situation is shown in FIG. (a) shows the surge voltage waveform applied to the external signal input terminal, and (b) shows the drain part 31 of the MOS transistor 3 in FIG.
This is the voltage waveform at . Normally, when the equivalent ground line wiring resistance 5 is negligibly small, the applied surge voltage is the breakdown voltage v
1 as well as the built-in voltage V2. However, as the ground line wiring resistance increases, the MO
The potential of the source part 32 of the S-type transistor 3 changes in the positive direction when a positive surge voltage is applied, and in the negative direction when a negative surge voltage is applied, respectively, by an amount indicated by V3 in the figure. Therefore, the voltage applied to the internal circuit 4 increases. This becomes a factor that lowers the surge withstand voltage of the semiconductor device.
本発明は、上記従来の問題点を解決するもので、集積度
増大によるチップ寸法の増加によって、接地線配線抵抗
が増大しても、安全に静電破壊から保護する半導体装置
を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and aims to provide a semiconductor device that can be safely protected from electrostatic damage even if the ground line wiring resistance increases due to an increase in chip size due to an increase in the degree of integration. purpose.
問題点を解決するための手段
この目的を達成するために、本発明の半導体装置は、外
部信号印加端子の近傍と、この外部信号が入力される内
部回路近傍との、複数箇所に静電破壊保護素子を有し、
これらのうち、内部回路近傍の静電破壊保護素子は、こ
の内部回路に対し、接地線配線抵抗を無視できる近接箇
所に設けた構成である。Means for Solving the Problems In order to achieve this object, the semiconductor device of the present invention prevents electrostatic damage at multiple locations, including near the external signal application terminal and near the internal circuit to which this external signal is input. has a protective element,
Among these, the electrostatic discharge protection element near the internal circuit is provided at a location close to the internal circuit where the ground line wiring resistance can be ignored.
作用
この構成によって、接地線電位の変動による、サージ耐
圧の低下を避けることが可能となり、サージから、半導
体装置を有効に保護することができる。Effect: With this configuration, it is possible to avoid a drop in the surge withstand voltage due to fluctuations in the ground line potential, and it is possible to effectively protect the semiconductor device from surges.
実施例
以下本発明の実施例について、図面を参照しながら説明
する。EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.
第１図は、本発明の第１の実施例における半導体装置の
回路図を示したものである。第１図において、１は外部
信号入力端子、２は保護抵抗、３は外部信号入力端子近
傍のＭＯＳ型トランジスタ、４は半導体内部回路ブロッ
ク、５は等価的接地線配線抵抗、６は半導体内部回路の
接地線に近接して接続されたＭＯＳ型トランジスタであ
る。FIG. 1 shows a circuit diagram of a semiconductor device according to a first embodiment of the present invention. In Fig. 1, 1 is an external signal input terminal, 2 is a protection resistor, 3 is a MOS transistor near the external signal input terminal, 4 is a semiconductor internal circuit block, 5 is an equivalent ground line wiring resistance, and 6 is a semiconductor internal circuit. This is a MOS type transistor connected closely to the ground line of the MOS transistor.
以上のように構成された半導体装置について、以下その
動作を説明する。The operation of the semiconductor device configured as described above will be described below.
外部信号印加端子１にサージ電圧が印加され、このとき
、等価的接地線配線抵抗５によって、外部信号入力端子
近傍のＭＯＳ型トランジスタ３のドレイン部３２が変動
し、ＭＯＳ型トランジスタ３で、充分に抑制されないま
ま、高電圧が内部回路４に印加されても、ＭＯＳ型トラ
ンジスタ６のドレイン部４２の電圧は、同ＭＯ８型トラ
ンジスタ６によって抑制されるために、内部回路４は、
サージ破壊から保護される。さらに、ＭＯＳ型トランジ
スタ６のソース部４１が変動しやすい状態であっても、
ＭＯＳトランジスタ６の接地線は、内部回路４の接地線
と、同じように変動するため、内部回路４は、サージ電
圧から保護される。A surge voltage is applied to the external signal application terminal 1, and at this time, the drain portion 32 of the MOS transistor 3 near the external signal input terminal fluctuates due to the equivalent ground line wiring resistance 5, and the MOS transistor 3 is sufficiently Even if a high voltage is applied to the internal circuit 4 without being suppressed, the voltage at the drain part 42 of the MOS type transistor 6 is suppressed by the MO8 type transistor 6, so that the internal circuit 4
Protected from surge damage. Furthermore, even if the source part 41 of the MOS transistor 6 is in a state where it is easily fluctuated,
Since the ground line of MOS transistor 6 fluctuates in the same way as the ground line of internal circuit 4, internal circuit 4 is protected from surge voltage.
以上のように本実施例によれば、入力信号が印加される
内部回路に、接地線を共有したＭＯＳ型トランジスタを
設けたことにより、接地線配線抵抗が増大した場合でも
、有効にサージ電圧から内部回路を保護できる。As described above, according to this embodiment, by providing a MOS transistor that shares a ground line in the internal circuit to which an input signal is applied, even if the ground line wiring resistance increases, it can effectively prevent surge voltage. Can protect internal circuits.
以下本発明の第２の実施例について図面を参照しながら
説明する。A second embodiment of the present invention will be described below with reference to the drawings.
第２図は、本発明を半導体記憶装置において実施した例
である。同図において、各符号１．２゜３．４．５．６
は第１図の構成要素上対応するものであり、加えて７は
、外部接地端子、８は記憶部を示す。FIG. 2 shows an example in which the present invention is implemented in a semiconductor memory device. In the same figure, each symbol is 1.2°3.4.5.6
The components correspond to those shown in FIG. 1, and in addition, 7 indicates an external grounding terminal, and 8 indicates a storage section.
上記のように構成された半導体装置について、以下に説
明する。The semiconductor device configured as described above will be described below.
第２図に示すように、半導体記憶装置では中心部の大部
分が記憶部８から成る。そのため、接地線は周辺部に沿
い長い距離にわたり配線される。As shown in FIG. 2, most of the central portion of the semiconductor memory device consists of a memory section 8. Therefore, the ground wire is routed over a long distance along the periphery.
外部接地端子７は、内部回路ブロック４の近傍に設け、
さらに、これに近接して、ＭＯ８型トランジスタ６を配
し、外部信号入力端子ｌに誘起されたサージ電圧が、Ｍ
Ｏ３型トランジスタ３により、充分に抑制されないまま
内部回路ブロック４に印加されるのをＭＯ８型トランジ
スタ６によって防止している。ここで、ＭＯ３型トラン
ジスタ６は、電圧保護として用いられるため、電流容量
は大きくとる必要がない。従って内部回路ブロック４内
に配することもできる。The external ground terminal 7 is provided near the internal circuit block 4,
Further, an MO8 type transistor 6 is disposed close to this, so that the surge voltage induced at the external signal input terminal l is
The MO8 type transistor 6 prevents the voltage from being applied to the internal circuit block 4 without being sufficiently suppressed by the O3 type transistor 3. Here, since the MO3 type transistor 6 is used for voltage protection, it is not necessary to have a large current capacity. Therefore, it can also be placed within the internal circuit block 4.
なお、第１．第２の実施例において、保護素子としてＭ
Ｏ８型トランジスタ３．６の２つを示したが、その間に
さらに複数の保護素子を入れてもよい。さらにこの保護
素子は、ＭＯ８型トランジスタでなくても、同等の機能
をもつ回路素子で良い。In addition, 1. In the second embodiment, as a protection element M
Although two O8 type transistors 3.6 are shown, a plurality of protection elements may be further inserted between them. Furthermore, this protection element does not have to be an MO8 type transistor, but may be a circuit element having an equivalent function.
発明の効果
以上のように、本発明は、静電破壊保護素子を外部信号
印加端子の近傍と、半導体装置内部回路近傍で接地線配
線抵抗が無視しうる近い箇所との複数箇所に設けること
により、接地電位が配線抵抗のために変動しても、極め
て安定に静電破壊よりの保護が可能となる。また、内部
回路近傍の保護素子は、電圧保護を目的とするため、寸
法は、通常の内部回路と同程度で良いため、回路ブロッ
ク内に配置することが可能であり、本発明を用いること
による寸法の増加は皆無である。従って本発明は極めて
広い適用範囲を持ち、その実用的効果は大なるものがあ
る。Effects of the Invention As described above, the present invention provides electrostatic damage protection elements at multiple locations near the external signal application terminal and near the internal circuit of the semiconductor device where the ground line wiring resistance can be ignored. Even if the ground potential fluctuates due to wiring resistance, protection against electrostatic damage can be achieved in an extremely stable manner. In addition, since the protection element near the internal circuit is intended for voltage protection, its dimensions may be the same as that of a normal internal circuit, so it can be placed within the circuit block, and by using the present invention, There is no increase in size. Therefore, the present invention has an extremely wide range of application and has great practical effects.
第１図は本発明の第１の実施例半導体装置の回路図、第
２図は本発明の第２の実施例半導体記憶装置のブロック
図、第３図は従来の半導体装置の回路図、第４図はゲー
ト部をソース部に接続したＭＯ８型トランジスタのドレ
イン電圧電流特性図、第５図はサージ電圧印加時の各部
波形図である。
１・・・・・・外部信号印加端子、２・・・・・・保護
抵抗、３・・・・・・ＭＯ８型トランジスタ、４・・・
・・・内部回路、５・・・・・・接地線配線抵抗、６・
・・・・・ＭＯ８型トランジスタ、７・・・・・・外部
接地端子、８・・・・・・記憶部。
代理人の氏名 弁理士 中尾敏男 ほか１２第 １ 図
第２図
ｆ
第３図
第４図
第５［！１1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a semiconductor memory device according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional semiconductor device. FIG. 4 is a drain voltage-current characteristic diagram of an MO8 type transistor in which the gate portion is connected to the source portion, and FIG. 5 is a waveform diagram of various parts when a surge voltage is applied. 1... External signal application terminal, 2... Protection resistor, 3... MO8 type transistor, 4...
... Internal circuit, 5 ... Ground wire wiring resistance, 6.
. . . MO8 type transistor, 7 . . . External ground terminal, 8 . . . Memory section. Name of agent Patent attorney Toshio Nakao et al. 12 Figure 2 Figure f Figure 3 Figure 4 Figure 5 [! 1
Claims (1)
る内部回路近傍との、複数箇所に静電破壊保護素子を有
し、かつ、前記内部回路近傍の静電破壊保護素子は、こ
の内部回路に対し、接地線配線抵抗を無視できる近接箇
所に設けたことを特徴とする半導体装置。ESD protection devices are provided at multiple locations, including near the external signal application terminal and near the internal circuit to which this external signal is input, and the electrostatic damage protection device near the internal circuit is connected to the internal circuit. In contrast, the semiconductor device is characterized in that the ground line wiring resistance is provided in a close location where the wiring resistance can be ignored.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62014716A JPH0724310B2 (en) | 1987-01-23 | 1987-01-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62014716A JPH0724310B2 (en) | 1987-01-23 | 1987-01-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63181469A true JPS63181469A (en) | 1988-07-26 |
| JPH0724310B2 JPH0724310B2 (en) | 1995-03-15 |
Family
ID=11868868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62014716A Expired - Lifetime JPH0724310B2 (en) | 1987-01-23 | 1987-01-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0724310B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008227369A (en) * | 2007-03-15 | 2008-09-25 | Asahi Kasei Electronics Co Ltd | Electrostatic breakage protection circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181044A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Input protecting circuit |
| JPS6010767A (en) * | 1983-06-30 | 1985-01-19 | Fujitsu Ltd | Semiconductor device |
| JPS60115253A (en) * | 1983-11-28 | 1985-06-21 | Nec Corp | Semiconductor integrated circuit device |
| JPS61264749A (en) * | 1985-05-13 | 1986-11-22 | エツセ・ジ・エツセ・ミクロエレツトロニ−カ・エツセ・ピ・ア | Dynamic protective integrator |
-
1987
- 1987-01-23 JP JP62014716A patent/JPH0724310B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181044A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Input protecting circuit |
| JPS6010767A (en) * | 1983-06-30 | 1985-01-19 | Fujitsu Ltd | Semiconductor device |
| JPS60115253A (en) * | 1983-11-28 | 1985-06-21 | Nec Corp | Semiconductor integrated circuit device |
| JPS61264749A (en) * | 1985-05-13 | 1986-11-22 | エツセ・ジ・エツセ・ミクロエレツトロニ−カ・エツセ・ピ・ア | Dynamic protective integrator |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008227369A (en) * | 2007-03-15 | 2008-09-25 | Asahi Kasei Electronics Co Ltd | Electrostatic breakage protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0724310B2 (en) | 1995-03-15 |
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