JPS63181451A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63181451A JPS63181451A JP62012525A JP1252587A JPS63181451A JP S63181451 A JPS63181451 A JP S63181451A JP 62012525 A JP62012525 A JP 62012525A JP 1252587 A JP1252587 A JP 1252587A JP S63181451 A JPS63181451 A JP S63181451A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- chip
- semiconductor device
- wiring board
- rom
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 29
- 229920005989 resin Polymers 0.000 claims abstract description 57
- 239000011347 resin Substances 0.000 claims abstract description 57
- 239000003822 epoxy resin Substances 0.000 claims abstract description 14
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 14
- 229920001721 polyimide Polymers 0.000 claims abstract description 8
- 239000009719 polyimide resin Substances 0.000 claims abstract description 6
- 239000000843 powder Substances 0.000 claims description 3
- 238000007789 sealing Methods 0.000 abstract description 26
- 238000000034 method Methods 0.000 abstract description 9
- 239000000853 adhesive Substances 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052799 carbon Inorganic materials 0.000 abstract description 2
- 239000000945 filler Substances 0.000 abstract description 2
- 239000004033 plastic Substances 0.000 abstract 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005304 joining Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体製造装置に係り、特にＩＣカード、ＩＣ
カートリッジ、時計、電卓などの電子装置に搭載される
超薄形の半導体装置とその製造方法に係り、より詳しく
は、ＩＣチップの封止手段に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor manufacturing equipment, and particularly to IC cards, IC
The present invention relates to an ultra-thin semiconductor device mounted on an electronic device such as a cartridge, a watch, or a calculator, and a method for manufacturing the same, and more specifically relates to a sealing means for an IC chip.
第７図に、従来よりＩＣカードに搭載されているこの種
半導体装置の１例を示す（特開昭６ｌ−３４６８７）。FIG. 7 shows an example of this type of semiconductor device conventionally mounted on an IC card (Japanese Patent Laid-Open No. 61-34687).
第７図は従来知られている半導体装置の断面図であって
、４１は配線基板、４２はＩＣチップ、４３は封止枠体
、４４は封止樹脂を示している。FIG. 7 is a sectional view of a conventionally known semiconductor device, in which reference numeral 41 indicates a wiring board, 42 an IC chip, 43 a sealing frame, and 44 a sealing resin.
配線基板４１の片面にはＩＣカードリーダライター（図
示せず）に付設された電極と電気的接続を得るための接
触端子４５がバターニングされており、また、他方の面
には後に詳述するＩＣチップ４２を接続するための接合
端子を有する配線パターン４６がバターニングされてい
る。また、この配線基板４１の前記配線パターン４６の
形成面には、前記ＩＣチップ４２を埋設するためのＩＣ
埋設部４８が凹設されている。One side of the wiring board 41 is patterned with contact terminals 45 for electrical connection with electrodes attached to an IC card reader/writer (not shown), and the other side is patterned with contact terminals 45, which will be described in detail later. A wiring pattern 46 having bonding terminals for connecting the IC chip 42 is patterned. Further, on the surface of the wiring board 41 on which the wiring pattern 46 is formed, an IC for embedding the IC chip 42 is provided.
The buried portion 48 is recessed.
ＩＣチップ４２は、例えばＩＣ化されたデータ処理部と
ＩＣ化されたメモリ部とから成り、表面の所定の位置に
電極４９が形成されている。このＩＣチップ４２は、前
記ｒｃ埋設部４８の底面４８ａに固定され、前記電極４
９と前記配線基板４１にパターニングされた配線パター
ン４６中の接合端子をリード５０で接続することによっ
て、所要の半導体回路が構成される。The IC chip 42 is composed of, for example, an IC data processing section and an IC memory section, and electrodes 49 are formed at predetermined positions on the surface. This IC chip 42 is fixed to the bottom surface 48a of the rc buried portion 48, and the electrode 4
9 and a bonding terminal in a wiring pattern 46 patterned on the wiring board 41 by a lead 50, a required semiconductor circuit is constructed.
前記封止枠体４３は前記ＩＣチップ４２を前記配線基板
４１のＩＣ埋設部４８内に適切に樹脂封止するために封
止領域を規制するものであって、例えばステンレス等の
硬質金属などによって形成され、前記配線基板４１の前
記ｒｃ埋設部４８の周囲に配設される。The sealing frame 43 regulates the sealing area in order to appropriately seal the IC chip 42 in the IC embedded portion 48 of the wiring board 41 with resin, and is made of, for example, a hard metal such as stainless steel. and is arranged around the rc buried portion 48 of the wiring board 41.
封止樹脂４４は、例えばエポキシ樹脂などの熱硬化性の
樹脂が用いられ、前記封止枠体４３及びＩＣ埋設部４８
内に充填され、前記配線基板４１、ＩＣチップ４２、封
止枠体４３、リード５０を一体に封止する。The sealing resin 44 is made of thermosetting resin such as epoxy resin, and is used for the sealing frame 43 and the IC embedding portion 48.
The wiring board 41, the IC chip 42, the sealing frame 43, and the leads 50 are sealed together.
以下、前記半導体装置の製造方法の一例を第８図の工程
説明図、及び第９図乃至１０図に基づいて説明する。Hereinafter, an example of the method for manufacturing the semiconductor device will be described based on the process diagram of FIG. 8 and FIGS. 9 and 10.
まず、第８図及び第９図に示すように、片面に所望の接
触端子４５と、他面に複数の接合端子とこれら接合端子
間などで形成される電気回路を含む配線パターン４６が
パターニングされ、所定の位置にＩＣ埋設部４８が凹設
された配線基ｔｒＩｉ４１の当該ＩＣ埋設部４８の底面
４８ａにＩＣチップ４２を固定し、前記配線パターン４
６中の接合端子と前記ＩＣチップ４２の電極４９とをリ
ード５゜により接続する。First, as shown in FIGS. 8 and 9, a wiring pattern 46 including a desired contact terminal 45 on one side and a plurality of bonding terminals and an electric circuit formed between these bonding terminals on the other side is patterned. , the IC chip 42 is fixed to the bottom surface 48a of the IC embedding part 48 of the wiring board trIi41 in which the IC embedding part 48 is recessed in a predetermined position, and the wiring pattern 4
The bonding terminal 6 and the electrode 49 of the IC chip 42 are connected by a lead 5°.
次いで、第８図及び第１０図に示すように、配線基板４
１に凹設されたＩＣ埋設部４８の周囲に封止枠体４３を
固定し、前記ＩＣチップ４２及び電極４９とリード５０
の接続部などが充分に封止されるように、封止枠４３及
びＩＣ埋設部４８によって形成される空間内にエポキシ
樹脂４４をやや多目にボッティングする。Next, as shown in FIGS. 8 and 10, the wiring board 4
A sealing frame 43 is fixed around the IC embedding part 48 recessed in the IC chip 42, the electrodes 49, and the leads 50.
A rather large amount of epoxy resin 44 is potted into the space formed by the sealing frame 43 and the IC embedding part 48 so that the connection parts and the like are sufficiently sealed.
エポキシ樹脂４４をキユアリングしたのち、第８図及び
第１１図に示すように、封止枠体４３の上面から膨出し
て固化したエポキシ樹脂４４の表面を研磨し、所要の厚
さｄを有する半導体装置を得る。After curing the epoxy resin 44, as shown in FIGS. 8 and 11, the surface of the epoxy resin 44 that has bulged from the upper surface of the sealing frame 43 and solidified is polished, and a semiconductor having a required thickness d is polished. Get the equipment.
しかし、以上の構成による半導体装置は、封止樹脂とし
てエポキシ樹脂等の熱硬化性樹脂が用いられているため
、硬化時に封止樹脂が膨張または収縮するなど寸法精度
が悪く、設計値通りの厚さｄの半導体装置の作製するた
めには、上記の如くキユアリング時に生ずる樹脂の熱変
形を考慮して予じめ必要量よりもやや多目の樹脂をボッ
ティングしく第１０図参照）、キユアリング後封止樹脂
（エポキシ樹脂）の表面を所定厚さになるように研摩加
工しなくてはならない（第１１図参照。）このため、研
摩加工時にかかる負荷によってＩＣチップが損傷したり
、リードが断線するといった不具合を生じ易く、歩留り
及び製品の信顛性が低いという問題がある。さらには、
樹脂の硬化に長時間を要し、かつ製造工程が複雑である
ため、生産性が悪いという問題もある。However, since the semiconductor device with the above configuration uses a thermosetting resin such as epoxy resin as the encapsulating resin, the dimensional accuracy is poor due to the encapsulating resin expanding or contracting during curing, and the thickness is not as designed. In order to fabricate a semiconductor device of 300 d, as mentioned above, in consideration of the thermal deformation of the resin that occurs during curing, it is necessary to bottle a slightly larger amount of resin than the required amount in advance (see Figure 10), and after curing. The surface of the sealing resin (epoxy resin) must be polished to a specified thickness (see Figure 11). Therefore, the load applied during polishing may damage the IC chip or break the leads. There are problems in that the yield rate and product reliability are low. Furthermore,
There is also the problem of poor productivity because it takes a long time to cure the resin and the manufacturing process is complicated.
この問題を解決するものとして特開昭６１−１０２２９
７がある。この構成を第１２図によって説明する。As a solution to this problem, Japanese Patent Application Laid-Open No. 61-10229
There are 7. This configuration will be explained with reference to FIG.
第１２図において、５１は光硬化性樹脂を示し、その他
第７図に示したと同様の部材については同一の符号をも
って表示されている。即ち、第１２図の半導体装置は、
封止樹脂としてエポキシ樹脂に代えて、紫外線の照射に
よって硬化する光硬化性樹脂５１を用いたことを特徴と
する。In FIG. 12, numeral 51 indicates a photocurable resin, and other members similar to those shown in FIG. 7 are designated by the same reference numerals. That is, the semiconductor device in FIG.
A feature is that a photocurable resin 51 that is cured by irradiation with ultraviolet rays is used as the sealing resin instead of an epoxy resin.
この半導体装置は、封止樹脂として硬化時間が短かく、
かつ硬化の際の変形が小さい光硬化性樹脂５１を用いた
ので、エポキシ樹脂を用いた場合に比べて硬化作業の迅
速化を図ることができると共に、リード５０の断線やシ
ョートといった不具合を起しにくいという利点がある。This semiconductor device has a short curing time as a sealing resin,
In addition, since the photocurable resin 51 is used, which is less deformed during curing, the curing work can be done more quickly than when epoxy resin is used, and problems such as breakage and short circuits of the leads 50 can occur. It has the advantage of being difficult.
第１２図に示した半導体装置は、第１３図に示すように
、カード本体５３の表面の一部に凹設された半導体装置
埋設部５４内に嵌挿され、接着により固定される。ここ
に、符号５２が半導体装置を示す。また、第１３図にお
いて、符号５５は暗証番号などを記録する磁気ストライ
ブを示す。As shown in FIG. 13, the semiconductor device shown in FIG. 12 is inserted into a semiconductor device buried portion 54 recessed in a part of the surface of the card body 53 and fixed by adhesive. Here, reference numeral 52 indicates a semiconductor device. Further, in FIG. 13, reference numeral 55 indicates a magnetic stripe for recording a personal identification number and the like.
しかし、従来の半導体装置にあっては、光硬化性樹脂を
用い、この硬化に際して紫外線を照射する必要があるた
め、紫外線によって記憶内容が消去されるＵＶ−ＥＰＲ
ＯＭをＩＣチップとして実装することができないという
問題があった。However, in conventional semiconductor devices, a photocurable resin is used and it is necessary to irradiate it with ultraviolet rays during curing.
There was a problem that the OM could not be mounted as an IC chip.
本発明の目的は、紫外線により硬化する樹脂を用いなが
ら、記憶内容を消去することなくＵＶＥＰＲＯＮの実装
が可能な半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device in which UVEPRON can be mounted without erasing the memory contents while using a resin that is cured by ultraviolet rays.
上記問題点を解決するため、本発明は、配線基板にＩＣ
チップを搭載し、前記配線基板及びＩＣチップ、それに
前記配線基板の接合端子と前記ＩＣチップの電極とを接
続するリードを一体に光硬化性樹脂を封止して成る半導
体装置において、紫外線照射によって記憶内容の消去が
可能なＲＯＭを前記ＩＣチップとして用いると共に、該
ＩＣチップの少くとも消去窓部を紫外線不透過性樹脂で
被覆しである。In order to solve the above problems, the present invention provides an IC on a wiring board.
In a semiconductor device in which a chip is mounted, the wiring board, the IC chip, and the leads connecting the bonding terminals of the wiring board and the electrodes of the IC chip are integrally sealed with a photocurable resin, A ROM whose stored contents can be erased is used as the IC chip, and at least an erasing window portion of the IC chip is coated with an ultraviolet opaque resin.
上記手段によると、ＩＣチップの表面部に被覆された紫
外線不透過性樹脂は、光硬化性樹脂を通過してくる紫外
線を減衰できるため、紫外線による製造工程におけるＩ
Ｃチップの記憶消去を招くことなく半導体装置を構成で
きる。According to the above means, the ultraviolet opaque resin coated on the surface of the IC chip can attenuate ultraviolet rays passing through the photocurable resin, so that
A semiconductor device can be constructed without causing memory erasure of the C chip.
以下、本発明の一実施例を図面に基づいて説明する。 Hereinafter, one embodiment of the present invention will be described based on the drawings.
第１図は本発明の一実施例による半導体装置の断面図で
ある。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
予め接合端子４がバターニングされた配線基板５の所定
位置に凹部が形成され、この凹部内にＵＶ−ＥＰＲＯＭ
チップ（以下、ＲＯＭチップという）３がエポキシ樹脂
等による接着剤によって固着される。ＲＯＭチップ３の
端子部と接合端子４のパターンの所定部分とはＡｕ線等
によるリード線７が接続される。ＲＯＭチップ３及びリ
ード線接続部を除いて接合端子４上に封止枠６が固定さ
れている。A recess is formed at a predetermined position of the wiring board 5 on which the bonding terminal 4 has been patterned in advance, and a UV-EPROM is inserted into the recess.
A chip (hereinafter referred to as a ROM chip) 3 is fixed with an adhesive such as epoxy resin. The terminal portion of the ROM chip 3 and a predetermined portion of the pattern of the bonding terminal 4 are connected to a lead wire 7 made of an Au wire or the like. A sealing frame 6 is fixed on the bonding terminal 4 except for the ROM chip 3 and the lead wire connection portion.
ＲＯＭチップ３の外表面には紫外光を遮断するための紫
外線不透過性樹脂層１が被覆されている。The outer surface of the ROM chip 3 is coated with an ultraviolet opaque resin layer 1 for blocking ultraviolet light.
この紫外線不透過性樹脂Ｎ１としては半透明のポリイミ
ド樹脂、カーボンフィラーを混入したエポキシ樹脂、遮
光性粉末（アルミナ、ケイ砂、金属粉等）を混入したエ
ポキシ樹脂等が用いられる。As the ultraviolet opaque resin N1, a translucent polyimide resin, an epoxy resin mixed with carbon filler, an epoxy resin mixed with light-shielding powder (alumina, silica sand, metal powder, etc.), etc. are used.
さらに、封止枠６で形成された空間内には、感光性樹脂
層２がボッティングされる。Furthermore, the photosensitive resin layer 2 is potted into the space formed by the sealing frame 6.
次に、以上の構成による半導体装置の製造工程を説明す
る。Next, the manufacturing process of the semiconductor device with the above configuration will be explained.
先ず、片面に所定のパターン形状の接合端子４が形成さ
れた配線基板５の凹部内にＲＯＭチップ３を樹脂接着剤
を用いて固定する。First, the ROM chip 3 is fixed in a recessed portion of a wiring board 5, on one side of which is formed a bonding terminal 4 in a predetermined pattern, using a resin adhesive.
ついで、ＲＯＭチップ３を開口の中心に位置させて封止
枠６を固定したのち、ＲＯＭチップ３と接合端子４間に
リード線７をポールボンディングによって接続する。Next, after the ROM chip 3 is positioned at the center of the opening and the sealing frame 6 is fixed, a lead wire 7 is connected between the ROM chip 3 and the bonding terminal 4 by pole bonding.
次に、ＲＯＭチップ３の表面に、厚さ５μｍ以上に紫外
線不透過性樹脂を被覆し、約１００℃の温度によって約
１時間加熱して硬化させ、紫外線不透過性樹脂層１を形
成する。Next, the surface of the ROM chip 3 is coated with an ultraviolet opaque resin to a thickness of 5 μm or more, and the resin is cured by heating at a temperature of about 100° C. for about 1 hour to form the ultraviolet opaque resin layer 1.
次に、ＲＯＭチップ３の上部に封止枠６によって形成さ
れた空間内に、紫外光によって硬化が促進される光硬化
性樹脂をボッティングする。このとき、封止枠６の上面
と同一平面が得られるように透明板（紫外光を透過しや
すい材料によるもの）でボッティングした樹脂を押える
ようにして余分の樹脂を流出させ、この状態のままで上
方から、例えば波長３６５ｎｍの紫外線を約６０秒、前
記透明板を介して照射する。この照射によって樹脂が硬
化した時点で透明板をはがすことにより、感光性樹脂Ｎ
２が形成される。Next, in the space formed by the sealing frame 6 above the ROM chip 3, a photocurable resin whose curing is promoted by ultraviolet light is potted. At this time, the excess resin is flowed out by pressing the potted resin with a transparent plate (made of a material that easily transmits ultraviolet light) so that the top surface of the sealing frame 6 is flush with the top surface of the sealing frame 6. For example, ultraviolet light having a wavelength of 365 nm is irradiated from above through the transparent plate for about 60 seconds. When the resin is cured by this irradiation, the transparent plate is peeled off and the photosensitive resin N
2 is formed.
第２図は本発明の他の実施例を示す断面図であり、第３
図はリード線接続部の詳細を示す拡大断面図である。本
実施例は、ＲＯＭチップ３にスクライブ分割される前の
ウェハーの段階でポリイミド樹脂をウェハーの表面（素
子形成面）に、厚さ１０８ｍ以下にスピン塗布する。つ
いで約１００℃で約１時間加熱して硬化させたのち、ホ
トリゾグラフィープロセスによって接合し、電極部（ア
ルミパッド）上部のポリイミド層をエツチングによって
除去したのち、ポリイミド層をマスクとして第３図に示
すようにパッシベーション層８をエツチング除去し、ア
ルミの接合電極部９を露出させる構成としたものである
。この接合電極部９にリード線７が接続される。FIG. 2 is a sectional view showing another embodiment of the present invention;
The figure is an enlarged sectional view showing details of the lead wire connection section. In this embodiment, before the wafer is scribed and divided into ROM chips 3, polyimide resin is spin coated on the surface of the wafer (element forming surface) to a thickness of 108 m or less. Then, after curing by heating at about 100°C for about 1 hour, they were bonded using a photolithography process, and the polyimide layer on the upper part of the electrode part (aluminum pad) was removed by etching, and the polyimide layer was used as a mask as shown in Fig. As shown, the passivation layer 8 is removed by etching to expose the aluminum bonding electrode portion 9. A lead wire 7 is connected to this bonding electrode portion 9 .
このようにして作られたウェハーをスクライブして、個
々のチップに分割したのち、第１図の実施例と同様の工
程を経て第２図及び第３図のように、ＲＯＭチップ３を
配線基板５に接着して固定する。ついでリード線７をボ
ンディングによって接続し、封止枠６を固定したのち、
感光性樹脂層２を形成する。After scribing the wafer made in this way and dividing it into individual chips, the ROM chip 3 is attached to a wiring board as shown in FIGS. 2 and 3 through the same process as in the embodiment shown in FIG. Glue and fix to 5. Then, after connecting the lead wire 7 by bonding and fixing the sealing frame 6,
A photosensitive resin layer 2 is formed.
第４図は本発明の第３の実施例を示す断面図である。本
実施例は、前記各実施例がＲＯＭチップ３と接合端子４
との接続をリード線７によって行なっていたのに対し、
ＴＡＢ法（テープ・オートメーテツド・ボンディング法
）によって行なうようにしたものである。即ち、Ｃｕに
Ｓｎメッキを施した接続リード１１を、ＲＯＭチップ３
に形成したＡｎによる接合バンプ１０を介して接合端子
４とＲＯＭチップ３に接続するようにしたものである。FIG. 4 is a sectional view showing a third embodiment of the present invention. In this embodiment, each of the above embodiments has a ROM chip 3 and a connecting terminal 4.
Whereas the connection was made by lead wire 7,
This is done by the TAB method (tape automated bonding method). That is, the connection lead 11 made of Cu plated with Sn is connected to the ROM chip 3.
The bonding terminal 4 is connected to the ROM chip 3 via a bonding bump 10 formed of An.
第５図は本発明の第４の実施例を示す断面図であり、第
６図はリード接続部の詳細を示す拡大断面図である。本
実施例は、ＲＯＭチップ３の表面（素子形成面）に厚さ
１０μｍ以下のポリイミド樹脂層ｌを形成し、このポリ
イミド樹脂層１に接合電極９が露出する孔を開口させ、
接続リード１１の先端に形成しである金バンプ１０と露
出させた接合電極９とを熱圧着させて接続する構成にし
たものである。FIG. 5 is a sectional view showing a fourth embodiment of the present invention, and FIG. 6 is an enlarged sectional view showing details of the lead connection portion. In this embodiment, a polyimide resin layer l having a thickness of 10 μm or less is formed on the surface (element forming surface) of a ROM chip 3, and a hole is opened in this polyimide resin layer 1 through which a bonding electrode 9 is exposed.
The gold bump 10 formed at the tip of the connection lead 11 and the exposed bonding electrode 9 are connected by thermocompression bonding.
以上の如き構造としたことにより、ＲＯＭチップを搭載
した配線基板全体に感光性樹脂をボッティングし、マス
クを用いて必要部分のみに露光し、未硬化樹脂を除去し
て微小かつ精密な構造に仕上げることができる。また、
ボッティングした感光性樹脂の表面を透明な平板で押え
、樹脂硬化後に平板を取外すことにより、硬化樹脂の表
面を滑らかな平面に仕上げることができる。With the above structure, photosensitive resin is potted onto the entire wiring board on which the ROM chip is mounted, and only the necessary parts are exposed using a mask, and the uncured resin is removed to create a minute and precise structure. can be finished. Also,
By pressing the surface of the potted photosensitive resin with a transparent flat plate and removing the flat plate after the resin has hardened, the surface of the cured resin can be finished into a smooth flat surface.
以上より明らかなように、本発明によれば、ＲＯＭチッ
プの表面に紫外線不透過性樹脂層を設けるようにしたた
め、感光性樹脂を紫外線によって硬化させても、ＲＯＭ
チップへの紫外線が遮断されるため、ＲＯＭチップにＵ
Ｖ−ＥＰＲＯＭを用いても記憶内容が消去されることは
ない。したがってＵＶ−ＥＰＲＯＭチップの樹脂封止に
対しても感光性樹脂を用いることが可能である。As is clear from the above, according to the present invention, since the ultraviolet opaque resin layer is provided on the surface of the ROM chip, even if the photosensitive resin is cured by ultraviolet rays, the ROM
Since ultraviolet rays to the chip are blocked, the ROM chip
Even if a V-EPROM is used, the stored contents will not be erased. Therefore, it is possible to use photosensitive resin for resin sealing of UV-EPROM chips.
第１図は本発明の一実施例を示す断面図、第２図は本発
明の第２実施例を示す断面図、第３図は第２図における
リード接続部の拡大断面図、第４図は本発明の第３実施
例を示す断面図、第５図は本発明の第４実施例を示す断
面図、第６図は第５図のリード接続部の拡大断面図、第
７図は従来知られているＩＣカード用半導体装置の第１
例を示す断面図、第８図は従来の半導体装置の製造工程
を説明する工程説明図、第９図は配線基板とＩＣチップ
の接続状態を示す断面図、第１０図は空間に熱硬化性樹
脂をボッティングした状態を示す断面図、第１１図は余
剰の熱硬化性樹脂を研摩する状態を示す断面図、第１２
図は従来知られているＩＣカード用半導体装置の他の例
を示す断面図、第１３図はＩＣカードの平面図である。
１・・・・・・紫外線不透性樹脂層、２・・・・・・感
光性樹脂層、３・・・・・・ＲＯＭチップ、４・・・・
・・接合端子、５・・・・・・配線基板、６・・・・・
・封止枠、７・・・・・・リード線、８・・・・・・パ
ッシベーション層、９・・・・・・接合電極、１゜・・
・・・・接合バンブ、１１・・・・・・接続リード。
−〜に’ｌ ？１１’）ψトの■
褌９＝
第７図
第８図
第９図
偽１０図
第 １１図FIG. 1 is a sectional view showing one embodiment of the present invention, FIG. 2 is a sectional view showing a second embodiment of the invention, FIG. 3 is an enlarged sectional view of the lead connection part in FIG. 2, and FIG. is a sectional view showing a third embodiment of the present invention, FIG. 5 is a sectional view showing a fourth embodiment of the invention, FIG. 6 is an enlarged sectional view of the lead connection portion of FIG. 5, and FIG. 7 is a conventional one. The first known semiconductor device for IC cards
A cross-sectional view showing an example, FIG. 8 is a process explanatory diagram explaining the conventional manufacturing process of a semiconductor device, FIG. 9 is a cross-sectional view showing a connection state between a wiring board and an IC chip, and FIG. 10 is a thermosetting material in the space. FIG. 11 is a cross-sectional view showing a state in which the resin has been botted; FIG. 11 is a cross-sectional view showing a state in which excess thermosetting resin is polished; FIG.
The figure is a sectional view showing another example of a conventionally known semiconductor device for an IC card, and FIG. 13 is a plan view of the IC card. 1... Ultraviolet opaque resin layer, 2... Photosensitive resin layer, 3... ROM chip, 4...
...Joining terminal, 5...Wiring board, 6...
・Sealing frame, 7...Lead wire, 8...Passivation layer, 9...Joining electrode, 1°...
...Joining bump, 11... Connection lead. - to'l? 11') ψt ■ Loincloth 9 = Fig. 7 Fig. 8 Fig. 9 False Fig. 10 Fig. 11
Claims (3)
びＩＣチップ、それに前記配線基板の接合端子と前記Ｉ
Ｃチップの電極とを接続するリードを一体に光硬化性樹
脂を封止して成る半導体装置において、紫外線照射によ
つて記憶内容の消去が可能なＲＯＭを前記ＩＣチップと
して用いると共に、該ＩＣチップの少なくとも消去窓部
を紫外線不透過性樹脂で被覆したことを特徴とする半導
体装置。(1) An IC chip is mounted on a wiring board, and the wiring board, the IC chip, the bonding terminal of the wiring board, and the I
In a semiconductor device in which a lead connecting to an electrode of a C chip is integrally sealed with a photocurable resin, a ROM whose memory contents can be erased by ultraviolet irradiation is used as the IC chip, and the IC chip A semiconductor device characterized in that at least an erasing window portion of the semiconductor device is coated with an ultraviolet opaque resin.
ることを特徴とする特許請求の範囲第（１）項に記載の
半導体装置。(2) The semiconductor device according to claim (1), wherein the ultraviolet opaque resin is a polyimide resin.
線不透過粉末を混入したものであることを特徴とする特
許請求の範囲第（１）項に記載の半導体装置。(3) The semiconductor device according to claim (1), wherein the ultraviolet opaque resin is an epoxy resin mixed with ultraviolet opaque powder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62012525A JPS63181451A (en) | 1987-01-23 | 1987-01-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62012525A JPS63181451A (en) | 1987-01-23 | 1987-01-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63181451A true JPS63181451A (en) | 1988-07-26 |
Family
ID=11807753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62012525A Pending JPS63181451A (en) | 1987-01-23 | 1987-01-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63181451A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH033257A (en) * | 1989-05-30 | 1991-01-09 | Mitsubishi Electric Corp | Semiconductor device |
| JP2008108828A (en) * | 2006-10-24 | 2008-05-08 | Nitto Denko Corp | Dicing die bond film |
| JP2012099826A (en) * | 2011-12-05 | 2012-05-24 | Nitto Denko Corp | Method of manufacturing dicing die-bonding film |
-
1987
- 1987-01-23 JP JP62012525A patent/JPS63181451A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH033257A (en) * | 1989-05-30 | 1991-01-09 | Mitsubishi Electric Corp | Semiconductor device |
| JP2008108828A (en) * | 2006-10-24 | 2008-05-08 | Nitto Denko Corp | Dicing die bond film |
| JP2012099826A (en) * | 2011-12-05 | 2012-05-24 | Nitto Denko Corp | Method of manufacturing dicing die-bonding film |
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