JP2547565B2 - Manufacturing method of hybrid integrated circuit - Google Patents
Manufacturing method of hybrid integrated circuitInfo
- Publication number
- JP2547565B2 JP2547565B2 JP62095565A JP9556587A JP2547565B2 JP 2547565 B2 JP2547565 B2 JP 2547565B2 JP 62095565 A JP62095565 A JP 62095565A JP 9556587 A JP9556587 A JP 9556587A JP 2547565 B2 JP2547565 B2 JP 2547565B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- programmable
- conductive path
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は混成集積回路の製造方法に関する。The present invention relates to a method for manufacturing a hybrid integrated circuit.
（ロ）従来の技術 アルミニウム等の金属基板上に混成集積回路を形成す
ることは既に特公昭46−13234号公報に提案されてい
る。斯る技術はアルミニウム基板表面に陽極酸化により
酸化アルミニウム薄層の絶縁膜が形成され、その絶縁膜
上に導電路および抵抗体が形成されて導電路上にトラン
ジスタ、集積回路等の回路素子を固着して混成集積回路
を提供するものであった。(B) Prior Art The formation of a hybrid integrated circuit on a metal substrate such as aluminum has already been proposed in Japanese Patent Publication No. 46-13234. In such a technique, a thin insulating film of aluminum oxide is formed on the surface of an aluminum substrate by anodic oxidation, and a conductive path and a resistor are formed on the insulating film to fix circuit elements such as transistors and integrated circuits on the conductive path. To provide a hybrid integrated circuit.
またハイブリッドLSIとして用いる場合は、マイコン
チップあるいはROM、マイクロプロセッサ等のLSIチップ
を固着して大容量の混成集積回路として用いる場合もあ
る。この様な場合、所定のデータが書き込まれているRO
MはマスクROMが用いられるのが普通である。しかしマス
クROMはマスクによってデータであるプログラムコード
を形成するので製造期間が長くなり、又はマスク代が高
価であるため、少量生産あるいは試作品の際において
は、あらかじめ樹脂でパッケージングされた書き込み消
去可能であるEPROMあるいは書き込み可能であるPROMが
用いられている。When used as a hybrid LSI, a microcomputer chip or an LSI chip such as a ROM or a microprocessor may be fixed and used as a large-capacity hybrid integrated circuit. In such a case, the RO with the prescribed data written
A mask ROM is usually used for M. However, since the mask ROM forms the program code that is the data by the mask, the manufacturing period becomes long, or the mask cost is expensive. EPROM or writable PROM is used.
（ハ）発明が解決しようとする問題点 しかしながら、EPROMあるいはPROMは従来樹脂でパッ
ケージングされているため厚膜ICのパッケージと重複す
るので小型化に制約があった。またパッケージングされ
たEPROM等の素子は外部端子が導出されているので試作
品段階において、端子から容易にプログラムデータが解
読でき機密保持ができない問題点があった。(C) Problems to be Solved by the Invention However, since the EPROM or PROM is packaged with a conventional resin and overlaps with the thick film IC package, there is a limitation in miniaturization. In addition, since the external terminals of the packaged elements such as EPROM are derived, there is a problem that the program data can be easily decoded from the terminals and the confidentiality cannot be maintained at the prototype stage.
（ニ）問題点を解決するための手段 本発明は上述した問題点に鑑みて為されたものであ
り、第１図Ａに示す如く、混成集積回路基板（１）上に
所望形状の導電路（３）を形成し、第１図Ｂに示す如
く、RORライタ（10）であらかじめ所望のデータをプロ
グラム可能な半導体素子（４）あるいはプログラム可能
な領域を有する半導体素子（５）に書き込み、第１図Ｃ
に示す如く、導電路（３）上にプログラム可能な半導体
素子（４）あるいはプログラム可能な領域を有する半導
体素子（５）を固着し、その接続を導電路（３）上に設
けられた他の半導体素子（12）のワイヤ（８）接続時に
同時に行った後、第１図Ｄに示す如く、プログラム可能
な半導体素子（４）あるいはプログラム可能な領域を有
する半導体素子（５）を樹脂（６）で封止して解決す
る。(D) Means for Solving the Problems The present invention has been made in view of the above problems, and as shown in FIG. 1A, a conductive path having a desired shape is formed on the hybrid integrated circuit board (1). (3) is formed, and as shown in FIG. 1B, desired data is written in advance to the programmable semiconductor element (4) or the semiconductor element (5) having a programmable area by the ROR writer (10). 1 Figure C
As shown in FIG. 3, a programmable semiconductor element (4) or a semiconductor element (5) having a programmable region is fixed on the conductive path (3), and its connection is made on another conductive element (3). Simultaneously with the wire (8) connection of the semiconductor element (12), the programmable semiconductor element (4) or the semiconductor element (5) having a programmable region is bonded to the resin (6) as shown in FIG. 1D. Seal and solve.
（ホ）作 用 この様に本考案に依れば、プログラム可能な半導体素
子（４）あるいはプログラム可能な領域を有する半導体
素子（５）をベア・チップ（裸の状態のチップ）の状態
で混成集積回路基板（１）上の導電路（３）に固着し導
電路（３）上に設けられた他の半導体素子（12）のワイ
ヤ接続時に導電路（３）と接続し半導体素子（４）
（５）を樹脂（６）で封止することにより、プログラム
可能あるいは領域を有する半導体素子（４）（５）から
外部端子が導出されないのでプログラムコード（デー
タ）を容易に読み出すことができないものである。(E) Operation As described above, according to the present invention, the programmable semiconductor element (4) or the semiconductor element (5) having the programmable region is mixed in a bare chip (bare chip) state. The semiconductor element (4) is fixed to the conductive path (3) on the integrated circuit board (1) and is connected to the conductive path (3) at the time of wire connection of another semiconductor element (12) provided on the conductive path (3).
By encapsulating (5) with resin (6), the external terminals are not led out from the programmable or region-containing semiconductor elements (4) and (5), so that the program code (data) cannot be read easily. is there.
（ヘ）実施例 以下に第１図Ａ乃至第１図Ｅに示した実施例に基づい
て本発明を説明する。(F) Embodiments The present invention will be described below based on the embodiments shown in FIGS. 1A to 1E.
先ず、第１図Ａに示す如く、混成集積回路基板（１）
上に所望形状の導電路（３）を形成する。混成集積回路
基板（１）はセラミックスあるいは金属が用いられ、本
実施例では放熱性及び機械的強度の優れたアルミニウム
の金属基板を用いる。そのアルミニウム基板表面には絶
縁性を持たせるために陽極酸化により酸化アルミニウム
膜が形成される。その酸化アルミニウム膜の一表面には
エポキシあるいはポリイミド等の樹脂により絶縁樹脂膜
（２）が形成される。絶縁樹脂膜（２）上には銅箔が貼
着され、その銅箔を所望のパターンにエッチングして所
望形状の導電路（３）が形成される。First, as shown in FIG. 1A, a hybrid integrated circuit board (1)
A conductive path (3) having a desired shape is formed thereon. Ceramic or metal is used for the hybrid integrated circuit substrate (1), and in this embodiment, a metal substrate of aluminum having excellent heat dissipation and mechanical strength is used. An aluminum oxide film is formed on the surface of the aluminum substrate by anodic oxidation so as to have an insulating property. An insulating resin film (2) is formed on one surface of the aluminum oxide film with a resin such as epoxy or polyimide. A copper foil is attached on the insulating resin film (2), and the copper foil is etched into a desired pattern to form a conductive path (3) having a desired shape.
導電路（３）上に固着されるプログラム可能な半導体
素子（４）たとえばEPROMあるいはプログラム可能な領
域を有する半導体素子（５）たとえばマイコンは、第１
図Ｂに示す如く、導電路（３）固着前にROMライタ（1
0）によって所定のプログラムコードあるいは各ユーザ
に対応した所定の情報が書き込まれる。このとき、プロ
グラム可能あるいは領域を有する半導体素子（４）
（５）はウェハ状態かあるいは個別に分離した後に書き
込む。ここでは分離しステージ（11）上に載置して半導
体素子（４）のパッドにROMライタ（10）の針（９）を
当接してデータを書き込む。A programmable semiconductor element (4), for example an EPROM or a semiconductor element (5), for example a microcomputer, having a programmable region fixed on the conductive path (3) is
As shown in Fig. B, the ROM writer (1
By 0), a predetermined program code or predetermined information corresponding to each user is written. At this time, a semiconductor device (4) which is programmable or has a region
(5) is written in the wafer state or after being separated individually. Here, they are separated and placed on the stage (11), and the needle (9) of the ROM writer (10) is brought into contact with the pad of the semiconductor element (4) to write data.
データ書き込み後、第１図Ｃに示す如く、プログラム
可能あるいは領域を有する半導体素子（４）（５）を導
電路（３）上に固着する。更に導電路（３）上にはプロ
グラム可能あるいは領域を有する半導体素子（４）
（５）で外部機器をインターフェイスするトランジス
タ、チップ抵抗、チップコンデンサ等の半導体素子（1
2）が固着されている。導電路（３）上に固着したプロ
グラム可能あるいは領域を有する半導体素子（４）
（５）の接続は導電路（３）上に設けられている他の半
導体素子（12）のワイヤ（８）接続（超音波ボンディン
グ）時に同時に行う。また導電路（３）が延在される基
板（１）の一周端辺には外部回路と接続するための外部
リード（13）が複数本固着される。After writing the data, as shown in FIG. 1C, the semiconductor elements (4) and (5) which are programmable or have regions are fixed on the conductive paths (3). Furthermore, a semiconductor element (4) having a programmable or region on the conductive path (3)
Semiconductor elements such as transistors, chip resistors, and chip capacitors that interface external devices with (5) (1
2) is stuck. Semiconductor device (4) having programmable or regions fixed on conductive paths (3)
The connection of (5) is made at the same time when the wire (8) of another semiconductor element (12) provided on the conductive path (3) is connected (ultrasonic bonding). Further, a plurality of external leads (13) for connecting to an external circuit are fixed to one peripheral edge of the substrate (1) on which the conductive paths (3) extend.
外部リード（13）固着後、第１図Ｄに示す如く、プロ
グラム可能あるいは領域を有する半導体素子（４）
（５）上にエポキシ樹脂あるいはシリコン樹脂等の樹脂
（６）を塗布して半導体素子（４）（５）を封止した
後、第１図Ｅに示す如く、半導体素子（４）（５）（1
2）を密封するために箱状のケース材（７）を基板
（１）に固着して外部リード（13）の固着部分を樹脂
（14）で補強して一体化する。After fixing the external leads (13), as shown in FIG. 1D, a semiconductor element (4) having a programmable or region
After the resin (6) such as an epoxy resin or a silicon resin is applied on (5) to seal the semiconductor elements (4) and (5), as shown in FIG. 1E, the semiconductor elements (4) and (5) (1
In order to seal 2), a box-shaped case material (7) is fixed to the substrate (1), and a fixed portion of the external lead (13) is reinforced with a resin (14) to be integrated.
（ト）発明の効果 以上に詳述した如く、本発明に依れば、混成集積回路
基板上にベア・チップの状態でEPROM、マイコン等のプ
ログラム可能あるいはプログラム可能な領域を有する半
導体素子を直接固着し、その接続を他の半導体素子の接
続と同時に行うことにより、従来の製造工程をそのまま
利用して、書き込まれたプログラムデータを容易に解読
することができない機密保持のすぐれた大容量の混成集
積回路を提供することができる。(G) Effects of the Invention As described in detail above, according to the present invention, a semiconductor element having a programmable or programmable area such as an EPROM or a microcomputer is directly formed on a hybrid integrated circuit substrate in a bare chip state. By fixing and connecting it at the same time as connecting other semiconductor elements, the conventional manufacturing process can be used as it is, and written program data cannot be easily decoded. An integrated circuit can be provided.
第１図Ａ乃至第１図Ｅは本発明の実施例を示す断面図で
ある。 （１）は混成集積回路基板、（２）は絶縁樹脂膜、
（３）は導電路、（４）（５）（12）は半導体素子、
（６）は樹脂、（７）はケース。1A to 1E are sectional views showing an embodiment of the present invention. (1) is a hybrid integrated circuit board, (2) is an insulating resin film,
(3) is a conductive path, (4), (5) and (12) are semiconductor elements,
(6) is a resin, (7) is a case.
Claims (1)
電路を形成し、所望のデータを書き込んだプログラム可
能なベアチップ型の半導体素子あるいはプログラム可能
な領域を有するベアチップ型の半導体素子を前記導電路
に固着し、前記固着後前記プログラム可能な半導体素子
あるいはプログラム可能な領域を有する半導体素子の接
続を前記導電路上に設けられた外部機器をインターフェ
イスする他の半導体素子のワイヤ接続時に行い、前記プ
ログラム可能な半導体素子あるいはプログラム可能な領
域を有する半導体素子の上に樹脂を塗布し、前記ケース
材を基板に固着し、前記塗布された樹脂をのぞき中空状
態で密封することを特徴とする混成集積回路の製造方
法。1. A programmable bare-chip type semiconductor element having a desired shape of a conductive path formed on an insulated metal substrate and having desired data written therein, or a bare-chip type semiconductor element having a programmable area is provided. After the fixing, the programmable semiconductor element or the semiconductor element having a programmable region is connected to the conductive path at the time of wire connection of another semiconductor element that interfaces with an external device provided on the conductive path, and A hybrid integrated device characterized in that a resin is applied onto a programmable semiconductor element or a semiconductor element having a programmable region, the case material is fixed to a substrate, and the applied resin is removed and sealed in a hollow state. Circuit manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62095565A JP2547565B2 (en) | 1987-04-17 | 1987-04-17 | Manufacturing method of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62095565A JP2547565B2 (en) | 1987-04-17 | 1987-04-17 | Manufacturing method of hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63261734A JPS63261734A (en) | 1988-10-28 |
| JP2547565B2 true JP2547565B2 (en) | 1996-10-23 |
Family
ID=14141112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62095565A Expired - Lifetime JP2547565B2 (en) | 1987-04-17 | 1987-04-17 | Manufacturing method of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2547565B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5937737U (en) * | 1982-09-03 | 1984-03-09 | 凸版印刷株式会社 | integrated circuit board |
-
1987
- 1987-04-17 JP JP62095565A patent/JP2547565B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63261734A (en) | 1988-10-28 |
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