JPS63146398U - - Google Patents
Info
- Publication number
- JPS63146398U JPS63146398U JP3785787U JP3785787U JPS63146398U JP S63146398 U JPS63146398 U JP S63146398U JP 3785787 U JP3785787 U JP 3785787U JP 3785787 U JP3785787 U JP 3785787U JP S63146398 U JPS63146398 U JP S63146398U
- Authority
- JP
- Japan
- Prior art keywords
- line
- chip select
- output enable
- memory card
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第1図は本考案の一実施例としてのメモリカー
ドの構成を説明する図、および第2図は従来例の
メモリカードの構成を説明する図である。
図において、1……アドレス選択線、2……ラ
イトイネーブル線、3……チツプセレクト線、4
……アウトプツトイネーブル線、5……電源線、
6……接地線、7……データ入出力線、8,9…
…抵抗、10,11……メモリカード、12……
記憶素子。
FIG. 1 is a diagram illustrating the configuration of a memory card as an embodiment of the present invention, and FIG. 2 is a diagram illustrating the configuration of a conventional memory card. In the figure, 1...address selection line, 2...write enable line, 3...chip select line, 4
...Output enable line, 5...Power line,
6...Grounding wire, 7...Data input/output line, 8, 9...
...Resistor, 10, 11...Memory card, 12...
memory element.
Claims (1)
続されるアドレス選択線1、ライトイネーブル線
2、チツプセレクト線3、アウトプツトイネーブ
ル線4、電源線5、接地線6、およびデータ入出
力線7を具備するメモリカード10において、 該チツプセレクト線3および該アウトプツトイ
ネーブル線4の印加電圧が不確定になつた時該メ
モリカード10の動作を停止するように、該チツ
プセレクト線3および該アウトプツトイネーブル
線4の少なくとも一方を抵抗8,9を介して電源
線5または接地線6へ接続したことを特徴とする
メモリカード。[Claims for Utility Model Registration] Address selection line 1, write enable line 2, chip select line 3, output enable line 4, power supply line 5, and ground that are inserted into and used in an information processing device and connected to the device. In a memory card 10 having a line 6 and a data input/output line 7, the operation of the memory card 10 is stopped when the voltages applied to the chip select line 3 and the output enable line 4 become uncertain. , at least one of the chip select line 3 and the output enable line 4 is connected to a power supply line 5 or a ground line 6 via resistors 8 and 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3785787U JPS63146398U (en) | 1987-03-17 | 1987-03-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3785787U JPS63146398U (en) | 1987-03-17 | 1987-03-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63146398U true JPS63146398U (en) | 1988-09-27 |
Family
ID=30849558
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3785787U Pending JPS63146398U (en) | 1987-03-17 | 1987-03-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63146398U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5769588A (en) * | 1980-10-16 | 1982-04-28 | Nec Corp | Memort circuit |
-
1987
- 1987-03-17 JP JP3785787U patent/JPS63146398U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5769588A (en) * | 1980-10-16 | 1982-04-28 | Nec Corp | Memort circuit |
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