JPS6314476A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6314476A JPS6314476A JP15854386A JP15854386A JPS6314476A JP S6314476 A JPS6314476 A JP S6314476A JP 15854386 A JP15854386 A JP 15854386A JP 15854386 A JP15854386 A JP 15854386A JP S6314476 A JPS6314476 A JP S6314476A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- highly doped
- region
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000012535 impurity Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 abstract description 4
- 238000000926 separation method Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 210000000988 bone and bone Anatomy 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にバイポーラＩＣにおけ
る高耐圧縦型トランジスタの改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to improvements in high voltage vertical transistors in bipolar ICs.
近年、ＯＡ（オフィスオートメーション）、ＦＡ（ファ
クトリ−オートメーション）に用いられる機器のモータ
制御、ディスプレイドライブ、電子バラスト等に高耐圧
バイポーラＩＣを使用することが強く望まれており、以
下に示すようなバイポーラＩＣにおいて高耐圧化が試み
られている。In recent years, there has been a strong desire to use high-voltage bipolar ICs for motor control, display drives, electronic ballasts, etc. of equipment used in OA (office automation) and FA (factory automation). Attempts are being made to increase the voltage resistance of ICs.
従来のバイポーラＩＣにおける縦型ｎｐｎ）ランジスタ
の製造方法を第３図（ａ）〜（８１を用いて説明する。A method of manufacturing a vertical NPN transistor in a conventional bipolar IC will be described with reference to FIGS. 3(a) to (81).
まず、ｐ形半導体基板１の表面部に高濃度ｎ最下部コレ
ククＮ２と高濃度ｐ彫工面分離層３とを譬形成する（第
３図（ａ））。次に該基板１上に低濃度ｎ形エピタキシ
ャルＮ５を成長させる（第３図山））、続いて該エピタ
キシャル層５に、高濃度ｐ形上面分ＡＩ層６を高濃度ｐ
彫工面分離層３に到達するように形成し、さらに高濃度
ｎ形コレクタ層７を高濃度ｎ彫工部コレクタ層２に到達
するように形成する（第３図（Ｃ））、次にｎ形エピタ
キシャル層５にｐ形拡散を行ってｎｐｎ）ランジスタの
ベース領域８を形成し、その後、該ベース領域８にｎ形
拡散を行ってエミッタ領域９を形成しく第３図（ｄ））
、最後に上記各領域９．８．７にそれぞれエミッタ電極
１０．ベース電極１１．コレクタ電極１２を被着して、
ｎｐｎトランジスタを得る（第３図（ｅ））。First, a highly doped n-bottom layer N2 and a highly doped p carved surface separation layer 3 are formed on the surface of the p-type semiconductor substrate 1 (FIG. 3(a)). Next, a lightly doped n-type epitaxial layer N5 is grown on the substrate 1 (Fig.
A high concentration n-type collector layer 7 is formed so as to reach the carved surface separation layer 3 (FIG. 3(C)), and then a high concentration n-type collector layer 7 is formed so as to reach the high concentration n-type collector layer 2 (FIG. 3(C)). A p-type diffusion is performed on the epitaxial layer 5 to form a base region 8 of an npn transistor, and then an n-type diffusion is performed on the base region 8 to form an emitter region 9 (FIG. 3(d)).
, and finally emitter electrodes 10 . Base electrode 11. By depositing the collector electrode 12,
An npn transistor is obtained (FIG. 3(e)).
従来のバイポーラＩＣにおけるトランジスタはかかる構
造になっているので、低耐圧トランジスタとして用いる
場合には問題なかったが、高耐圧トランジスタとして用
いる場合には、高耐圧化を図るため、エピタキシャル成
長層５の比抵抗を高く、かつ厚さを厚くしなければなら
なかった。また、単に該層５の比抵抗を高く、厚さを厚
くしたものでは、ベース領域８直下で規定の比抵抗が得
られず、エピタキシャル層５の比抵抗及びエピタキシャ
ル層５の厚さで決まる耐圧よりかなり低い値で降伏を起
こし高耐圧化できないという欠点があった。The transistors in conventional bipolar ICs have such a structure, so there was no problem when used as a low voltage transistor, but when used as a high voltage transistor, the specific resistance of the epitaxial growth layer 5 was had to be made higher and thicker. Furthermore, if the specific resistance of the layer 5 is simply increased and the thickness is increased, a specified specific resistance cannot be obtained directly under the base region 8, and the breakdown voltage determined by the specific resistance of the epitaxial layer 5 and the thickness of the epitaxial layer 5 is It has the disadvantage that breakdown occurs at a much lower value than that, making it impossible to achieve a high withstand voltage.
すなわち、エピタキシャル層５の成長時には、オートド
ーピング、アウトディフュージョンによって、高濃度ｎ
彫工部コレクタ１１２がエピタキシャル層５へ浮き上が
り、エピタキシャル層の厚さは実際には第４図（ａ）に
示すようにｄ５ａになる。That is, when growing the epitaxial layer 5, a high concentration of n is formed by autodoping and outdiffusion.
The carved portion collector 112 is lifted up to the epitaxial layer 5, and the thickness of the epitaxial layer actually becomes d5a as shown in FIG. 4(a).
ここで点線１３はエピタキシャル層成長前の不純物濃度
分布、実ｖＡ１４はエピタキシャル層成長後の不純物濃
度分布、ｄ、は基板１の上面からエピタキシャル層５の
上面までの距離、ｄ２は基板１の上面からコレクタ層２
の底面までの距離である。Here, the dotted line 13 is the impurity concentration distribution before the epitaxial layer growth, the actual vA14 is the impurity concentration distribution after the epitaxial layer growth, d is the distance from the top surface of the substrate 1 to the top surface of the epitaxial layer 5, and d2 is the distance from the top surface of the substrate 1. Collector layer 2
is the distance to the bottom of the
また高濃度ｐ形上面分離層６．高濃度ｎ形コレクタ層７
の形成時には、長時間の拡散により高濃度ｎ彫工部コレ
クタ層２はさらにエピタキシャル層５へ浮き上り、エピ
タキシャル層の厚さは第φ図（ｂｌに示すように実際に
はｄ５ｂになる。ここで実線１５は高濃度ｐ形上面分離
Ｎ７．高濃度ｎ形コレクタｊ！ｉ ２形成後の不純物濃
度分布である。このため、上述のように高耐圧化できな
いという欠点があった。Also, a high concentration p-type top separation layer 6. High concentration n-type collector layer 7
During the formation of , the high concentration N engraving collector layer 2 further rises to the epitaxial layer 5 due to long-term diffusion, and the thickness of the epitaxial layer is actually d5b as shown in Figure φ (bl). The solid line 15 is the impurity concentration distribution after the formation of the high concentration p-type upper surface separation N7 and the high concentration n-type collector j!i 2.Therefore, as mentioned above, there was a drawback that a high breakdown voltage could not be achieved.
本発明は上記のような欠点を解消するためになされたも
ので、その縦型トランジスタが高耐圧化されたバイポー
ラＩＣを得ることを目的とする。The present invention was made to eliminate the above-mentioned drawbacks, and an object of the present invention is to obtain a bipolar IC whose vertical transistor has a high breakdown voltage.
本発明にかかる半導体装置はｐ形半導体基板の所定の領
域に高濃度下部コレクタｎ型領域を形成し、さらに該領
域の所定の領域に高濃度ｐ型領域を形成したものである
。A semiconductor device according to the present invention has a highly doped lower collector n-type region formed in a predetermined region of a p-type semiconductor substrate, and further has a highly doped p-type region formed in a predetermined region of the region.
本発明においては、ｐ形基板の高濃度下部ｎ形コレクタ
層の所定の令頁域に高濃度ｐ影領域を形成したから、エ
ピタキシャル層の成長時及び高濃度上面ｐ形骨離層、高
濃度ｎ形コレクタ層の形成時における高濃度下部ｎ形コ
レクタ層のエピタキシャル層への浮き上りを高濃度ｐ影
領域によって制えることができ、これにより規定のエビ
タキシャる。In the present invention, since a high concentration p shadow region is formed in a predetermined narrow area of the high concentration lower n type collector layer of the p type substrate, during the growth of the epitaxial layer and the high concentration upper surface p type bone delamination, the high concentration During the formation of the n-type collector layer, the floating of the highly doped lower n-type collector layer to the epitaxial layer can be suppressed by the highly doped p-shade region, thereby achieving a prescribed epitaxy.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図（ｆ）は本発明の一実施例による半導体装置の構
造を示し、図において、第３図（ｅｌと同一符号は同一
のものを示し、４は高濃度下部ｎ形コレクタ層の所定の
領域に形成された高濃度ｐ影領域である。FIG. 1(f) shows the structure of a semiconductor device according to an embodiment of the present invention, in which the same reference numerals as el in FIG. This is a high-density p shadow region formed in the region.
次に第１図（ａ）〜（ｆ）に基づいて製造方法について
説明する。Next, the manufacturing method will be explained based on FIGS. 1(a) to 1(f).
まず、ｐ形半導体基板１の表面部に高濃度ｎ彫工部コレ
クタ層２を形成する（第１図（ａ））。次に該基板の表
面部に咳高濃度ｎ彫工部コレクタ層２に隣接して高濃度
ｐ形下面分離層３を形成すると同時に、高濃度ｎ彫工部
コレクタ層２中にも高濃度ｐ形層４をメソシュ状に形成
する（第１図（ｂ））。First, a highly doped n-carved collector layer 2 is formed on the surface of a p-type semiconductor substrate 1 (FIG. 1(a)). Next, a high concentration p-type lower surface separation layer 3 is formed on the surface of the substrate adjacent to the high concentration n carved portion collector layer 2, and at the same time, a high concentration p type layer is also formed in the high concentration n carved portion collector layer 2. 4 into a mesh shape (FIG. 1(b)).
続いてｐ形基板１上に、低濃度ｎ形エピタキシャル層５
を成長させる（第１図（Ｃ１））。次にｎ形エピタキシ
ャル層５中に高濃度ｐ形上面分鉗層６を上記高濃度ｐ形
下面分離層３に到達する様に形成し、また高濃度ｎ形コ
レクタ層７を上記高濃度ｎ彫工部コレクタ［２に到達す
る様に形成する（第１図（ｄ））。続いて、ｎ形エピタ
キシャル層５にｐ形拡散を行ってｎｐｎ）ランジスタの
ベース領域８を形成し、その後該ベース領域８にｎ形拡
散を行ってエミッタ領域９を形成して（第１図（ｅ））
、上記領域９．８．７にエミッタ電極１０、ベース電極
１１．コレクタ電極１２を被着して、ｎｐｎトランジス
タを得る（第１図（ｆ））。Subsequently, a low concentration n-type epitaxial layer 5 is formed on the p-type substrate 1.
(Fig. 1 (C1)). Next, a high-concentration p-type upper separation layer 6 is formed in the n-type epitaxial layer 5 so as to reach the high-concentration p-type lower separation layer 3, and a high-concentration n-type collector layer 7 is formed in the high-concentration n-type epitaxial layer 5. It is formed so as to reach the collector [2] (FIG. 1(d)). Subsequently, p-type diffusion is performed on the n-type epitaxial layer 5 to form a base region 8 of an npn transistor, and then n-type diffusion is performed on the base region 8 to form an emitter region 9 (see FIG. 1). e))
, an emitter electrode 10, a base electrode 11., in the region 9.8.7. A collector electrode 12 is deposited to obtain an npn transistor (FIG. 1(f)).
次に作用効果について説明する。Next, the effects will be explained.
この様にして得られた縦型トランジスタは、従来の構造
において高耐圧化を試みたトランジスタとは異なり高濃
度ｎ彫工部コレクタｒ？１２中に□高濃度ｐ形層４の領
域を持つので、エピタキシャル層５の成長時及び高濃度
ｐ形上面分離層６．高濃度ｎ形コレクタ層７の形成時に
、高濃度ｎ彫工部コレクタ層２がエピタキシャル層５へ
浮き上るのを高濃度ｐ形層４により制えることができ、
これにより第２図（ａ）、 （ｂ）に示すようにエピタ
キシャル層５の厚さは変化せず、エピタキシャルＮ５の
比抵抗が低下するのを防ぐことができる。ここで、１３
．１４．１５．ｄｓ＋ ｄ２は第４図と同一のもの、
ｄ４は基板１の上面から高濃度ｐ形層４の底面での距離
である。従って、上記ベース領域８の直下の領域でもエ
ピタキシャル層の比抵抗を規定の値に保つことができ、
エピタキシャル層５の比抵抗及び厚さで決まる耐圧とほ
ぼ同程度の耐圧を得ることができる。また、高濃度ｎ彫
工部コレクタ層２中の高濃度ｐ形層４を所定の形状（例
えばメソシュ状）にすることで高濃度ｎ彫工部コレクタ
層２中の全面にｐ形半導体の層を形成する構造と比べて
も耐圧をそれ程低下させることなく、かつ大きな電流を
確保できるという利点がある。The vertical transistor obtained in this way differs from transistors with a conventional structure in which a high breakdown voltage has been attempted, in that the collector r? 12 has a region of □highly doped p-type layer 4, so that when the epitaxial layer 5 is grown and the highly doped p-type upper surface isolation layer 6. When forming the high concentration n-type collector layer 7, the high concentration p-type layer 4 can prevent the high concentration n carved portion collector layer 2 from floating up to the epitaxial layer 5.
As a result, the thickness of the epitaxial layer 5 does not change as shown in FIGS. 2(a) and 2(b), and it is possible to prevent the specific resistance of the epitaxial layer N5 from decreasing. Here, 13
．． 14.15. ds+ d2 is the same as in Figure 4,
d4 is the distance from the top surface of the substrate 1 to the bottom surface of the highly doped p-type layer 4. Therefore, the specific resistance of the epitaxial layer can be maintained at a specified value even in the region immediately below the base region 8,
A breakdown voltage approximately equal to that determined by the resistivity and thickness of the epitaxial layer 5 can be obtained. Furthermore, by forming the highly doped p-type layer 4 in the highly doped n-carved collector layer 2 into a predetermined shape (for example, mesoche-like), a p-type semiconductor layer is formed over the entire surface of the highly doped n-carved collector layer 2. Compared to other structures, this structure has the advantage that a large current can be secured without significantly lowering the withstand voltage.
なお、上記実施例では縦型ｎｐｎ）ランジスタについて
説明したが、本発明はｐｎｐ）ランジスタにも適用でき
、この場合も上記実施例と同様な効果を奏することは言
うまでもない。In the above embodiment, a vertical npn) transistor has been described, but the present invention can also be applied to a pnp transistor, and it goes without saying that the same effects as in the above embodiment can be achieved in this case as well.
また上記実施例では上記高濃度ｐ形層４をメツシュ状に
形成したものを示したが、これはストライプ状あるいは
島状に形成してもよい。Further, in the above embodiment, the high concentration p-type layer 4 is formed in a mesh shape, but it may be formed in a stripe shape or an island shape.
以上の様に本発明にかかる半導体装置によれば、バイポ
ーラＩＣにおける縦型トランジスタのｐ形基板の高濃度
ｎ彫工部コレクタ層中に高濃度ｐ形層の領域を形成した
ので、エピタキシャル層の成長時及び高濃度ｐ形上面分
離層、高濃度ｎ形コレクタ層の形成時の高濃度ｎ彫工部
コレクタ層の浮き上りを防ぐことができ、これにより規
定の比抵抗をベース領域の直下のエピタキシャル層で確
保でき、バイポーラＩＣの高耐圧化を図ることができる
。As described above, according to the semiconductor device according to the present invention, since the region of the highly doped p-type layer is formed in the collector layer of the highly doped n carved portion of the p-type substrate of the vertical transistor in the bipolar IC, the growth of the epitaxial layer is prevented. When forming a highly doped p-type upper surface separation layer and a highly doped n-type collector layer, lifting of the highly doped n-carved collector layer can be prevented. This allows the bipolar IC to have a high breakdown voltage.
第１図は本発明の一実施例による半導体装置の構造を示
す断面図、第２図は該半導体装置の構造における拡散プ
ロファイルを示す図、第３図は従来のバイポーラＩＣに
おける縦型トランジスタの構造を示す断面図、第４図は
従来のトランジスタの構造における拡散プロファイルを
示す図である。
図中、１はｐ形基板、２は高濃度ｎ彫工部コレクタ層、
３は高濃度ｐ形下面分離層、４は高濃度ｐ形層、５は低
濃度ｎ形エピタキシャル層、６は高濃度ｐ形上面分離層
、７は高濃度ｎ形コレクタ層、８はベース領域、９はエ
ミッタ領域である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing a diffusion profile in the structure of the semiconductor device, and FIG. 3 is the structure of a vertical transistor in a conventional bipolar IC. FIG. 4 is a diagram showing a diffusion profile in the structure of a conventional transistor. In the figure, 1 is a p-type substrate, 2 is a collector layer with a high concentration n carved part,
3 is a highly doped p-type bottom isolation layer, 4 is a highly doped p-type layer, 5 is a lightly doped n-type epitaxial layer, 6 is a highly doped p-type top isolation layer, 7 is a highly doped n-type collector layer, and 8 is a base region. , 9 is an emitter region. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (4)
物濃度の第１の第２導電形半導体領域と、上記第１の半
導体領域中の所定の部分に形成された第２の第１導電形
半導体領域と、 上記半導体基板上に形成された第２導電形コレクタ領域
と、 該コレクタ領域中に形成された第１導電形ベース領域と
、 該ベース領域中に形成された第２導電形エミッタ領域と
を備えたことを特徴とする半導体装置。(1) a first conductivity type semiconductor substrate; a first second conductivity type semiconductor region having a high impurity concentration formed in a predetermined portion of the surface portion of the semiconductor substrate; and a predetermined region in the first semiconductor region; a second conductivity type semiconductor region formed on the semiconductor substrate, a second conductivity type collector region formed on the semiconductor substrate, a first conductivity type base region formed in the collector region, and the base. a second conductivity type emitter region formed in the semiconductor device.
にメッシュ状に形成されたものであることを特徴とする
特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the second semiconductor region is formed in a mesh shape in the first semiconductor region.
にストライプ状に形成されたものであることを特徴とす
る特許請求の範囲第１項記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the second semiconductor region is formed in a stripe shape in the first semiconductor region.
に島状に形成されたものであることを特徴とする特許請
求の範囲第１項記載の半導体装置。(4) The semiconductor device according to claim 1, wherein the second semiconductor region is formed in an island shape within the first semiconductor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15854386A JPS6314476A (en) | 1986-07-04 | 1986-07-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15854386A JPS6314476A (en) | 1986-07-04 | 1986-07-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6314476A true JPS6314476A (en) | 1988-01-21 |
Family
ID=15674004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15854386A Pending JPS6314476A (en) | 1986-07-04 | 1986-07-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6314476A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5530273A (en) * | 1992-11-26 | 1996-06-25 | Nec Corporation | Semiconductor device capable of preventing reduction of cut-off frequency by Kark effect even when operated within a high electric current density range |
| JP2007185082A (en) * | 2005-06-28 | 2007-07-19 | Denso Corp | Field-winding synchronous machine |
-
1986
- 1986-07-04 JP JP15854386A patent/JPS6314476A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5530273A (en) * | 1992-11-26 | 1996-06-25 | Nec Corporation | Semiconductor device capable of preventing reduction of cut-off frequency by Kark effect even when operated within a high electric current density range |
| JP2007185082A (en) * | 2005-06-28 | 2007-07-19 | Denso Corp | Field-winding synchronous machine |
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