JPS63138729U - - Google Patents
Info
- Publication number
- JPS63138729U JPS63138729U JP3111287U JP3111287U JPS63138729U JP S63138729 U JPS63138729 U JP S63138729U JP 3111287 U JP3111287 U JP 3111287U JP 3111287 U JP3111287 U JP 3111287U JP S63138729 U JPS63138729 U JP S63138729U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- circuit
- tuning circuit
- digital tuning
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Description
第1図乃至第4図はこの考案の一実施例を示す
もので、第1図はクロツク発生回路の構成を示す
ブロツク図、第2図は第1図の動作内容を示すタ
イミングチヤート、第3図は第1図のクロツク発
生回路を使用したラジオ受信機の全体構成を示す
ブロツク図、第4図は第3図のDTS回路の内部
構成を示すブロツク図、第5図は従来のクロツク
発生回路の構成を示すブロツク図、第6図は第5
図の動作内容を示すタイミングチヤートである。
11,21……発振器、31……メインROM
、32……ACS制御回路、33……ACS回路
、34……RAM、35……インストラクシヨン
・デコーダ、36……加減算回路、37……DT
S回路、38……キー入力部、39……アドレス
指定回路、40……判断部、41……POC回路
、42,65……デコーダ、43……表示部、4
4……キー判断部、45……表示制御回路、48
……レギユレータ、49……倍圧回路、50……
クロツク発生回路、55A,55B……一致回路
、59A,59B……8段立下りバイナリカウン
タ、60……タイミングカウンタ、66……ビツ
ト切換回路、69……キヤンセル回路。
1 to 4 show an embodiment of this invention. FIG. 1 is a block diagram showing the configuration of a clock generation circuit, FIG. 2 is a timing chart showing the operation contents of FIG. 1, and FIG. Figure 4 is a block diagram showing the overall configuration of a radio receiver using the clock generation circuit shown in Figure 1, Figure 4 is a block diagram showing the internal configuration of the DTS circuit shown in Figure 3, and Figure 5 is a conventional clock generation circuit. A block diagram showing the configuration of the
It is a timing chart showing the operation contents of the figure. 11, 21...Oscillator, 31...Main ROM
, 32...ACS control circuit, 33...ACS circuit, 34...RAM, 35...instruction decoder, 36...addition/subtraction circuit, 37...DT
S circuit, 38... Key input section, 39... Address designation circuit, 40... Judgment section, 41... POC circuit, 42, 65... Decoder, 43... Display section, 4
4...Key determination unit, 45...Display control circuit, 48
... Regulator, 49 ... Voltage doubler circuit, 50 ...
Clock generation circuit, 55A, 55B... Match circuit, 59A, 59B... 8-stage falling binary counter, 60... Timing counter, 66... Bit switching circuit, 69... Cancel circuit.
Claims (1)
受信を行なうためのデジタルチユーニング回路と
を備えており、該制御装置の基準クロツクに比し
て該デジタルチユーニング回路の基準クロツクの
周波数が高い電子受信装置において、 基準発振器の発振クロツクの立下がりに同期し
、これを分周して上記デジタルチユーニング回路
の基準クロツクを作成する第1のクロツク作成手
段と、 この第1のクロツク作成手段によるデジタルチ
ユーニング回路の基準クロツクの立上がりに同期
し、上記基準発振器の発振クロツクを分周して上
記制御装置の基準クロツクを作成する第2のクロ
ツク作成手段と、 を具備したことを特徴とする電子受信装置。[Claims for Utility Model Registration] Equipped with a calculation function, a control device for calculation, and a digital tuning circuit for electronic reception, the digital tuning circuit is In an electronic receiving device in which the frequency of the reference clock of the circuit is high, a first clock generation means synchronizes with the falling edge of the oscillation clock of the reference oscillator and divides the frequency of the oscillation clock to generate the reference clock of the digital tuning circuit; a second clock generating means for creating a reference clock for the control device by frequency-dividing the oscillation clock of the reference oscillator in synchronization with the rise of the reference clock of the digital tuning circuit by the first clock generating means; An electronic receiving device characterized by comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3111287U JPH066618Y2 (en) | 1987-03-05 | 1987-03-05 | Electronic receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3111287U JPH066618Y2 (en) | 1987-03-05 | 1987-03-05 | Electronic receiver |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63138729U true JPS63138729U (en) | 1988-09-13 |
JPH066618Y2 JPH066618Y2 (en) | 1994-02-16 |
Family
ID=30836550
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3111287U Expired - Lifetime JPH066618Y2 (en) | 1987-03-05 | 1987-03-05 | Electronic receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH066618Y2 (en) |
-
1987
- 1987-03-05 JP JP3111287U patent/JPH066618Y2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH066618Y2 (en) | 1994-02-16 |
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